1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
4 * Copyright (C) 2008 Dmitri Vorobiev
5 *
6 *  This program is free software; you can distribute it and/or modify it
7 *  under the terms of the GNU General Public License (Version 2) as
8 *  published by the Free Software Foundation.
9 *
10 *  This program is distributed in the hope it will be useful, but WITHOUT
11 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
13 *  for more details.
14 *
15 *  You should have received a copy of the GNU General Public License along
16 *  with this program; if not, write to the Free Software Foundation, Inc.,
17 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 */
19#include <linux/cpu.h>
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/ioport.h>
23#include <linux/irq.h>
24#include <linux/pci.h>
25#include <linux/screen_info.h>
26#include <linux/time.h>
27
28#include <asm/fw/fw.h>
29#include <asm/mips-cm.h>
30#include <asm/mips-boards/generic.h>
31#include <asm/mips-boards/malta.h>
32#include <asm/mips-boards/maltaint.h>
33#include <asm/dma.h>
34#include <asm/traps.h>
35#ifdef CONFIG_VT
36#include <linux/console.h>
37#endif
38
39extern void malta_be_init(void);
40extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
41
42static struct resource standard_io_resources[] = {
43	{
44		.name = "dma1",
45		.start = 0x00,
46		.end = 0x1f,
47		.flags = IORESOURCE_BUSY
48	},
49	{
50		.name = "timer",
51		.start = 0x40,
52		.end = 0x5f,
53		.flags = IORESOURCE_BUSY
54	},
55	{
56		.name = "keyboard",
57		.start = 0x60,
58		.end = 0x6f,
59		.flags = IORESOURCE_BUSY
60	},
61	{
62		.name = "dma page reg",
63		.start = 0x80,
64		.end = 0x8f,
65		.flags = IORESOURCE_BUSY
66	},
67	{
68		.name = "dma2",
69		.start = 0xc0,
70		.end = 0xdf,
71		.flags = IORESOURCE_BUSY
72	},
73};
74
75const char *get_system_type(void)
76{
77	return "MIPS Malta";
78}
79
80const char display_string[] = "	       LINUX ON MALTA	    ";
81
82#ifdef CONFIG_BLK_DEV_FD
83static void __init fd_activate(void)
84{
85	/*
86	 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
87	 * Controller.
88	 * Done by YAMON 2.00 onwards
89	 */
90	/* Entering config state. */
91	SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
92
93	/* Activate floppy controller. */
94	SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
95	SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
96	SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
97	SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
98
99	/* Exit config state. */
100	SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
101}
102#endif
103
104static int __init plat_enable_iocoherency(void)
105{
106	int supported = 0;
107	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
108		if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
109			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
110			pr_info("Enabled Bonito CPU coherency\n");
111			supported = 1;
112		}
113		if (strstr(fw_getcmdline(), "iobcuncached")) {
114			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
115			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
116				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
117				  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
118			pr_info("Disabled Bonito IOBC coherency\n");
119		} else {
120			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
121			BONITO_PCIMEMBASECFG |=
122				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
123				 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
124			pr_info("Enabled Bonito IOBC coherency\n");
125		}
126	} else if (mips_cm_numiocu() != 0) {
127		/* Nothing special needs to be done to enable coherency */
128		pr_info("CMP IOCU detected\n");
129		if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) {
130			pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n");
131			return 0;
132		}
133		supported = 1;
134	}
135	hw_coherentio = supported;
136	return supported;
137}
138
139static void __init plat_setup_iocoherency(void)
140{
141#ifdef CONFIG_DMA_NONCOHERENT
142	/*
143	 * Kernel has been configured with software coherency
144	 * but we might choose to turn it off and use hardware
145	 * coherency instead.
146	 */
147	if (plat_enable_iocoherency()) {
148		if (coherentio == 0)
149			pr_info("Hardware DMA cache coherency disabled\n");
150		else
151			pr_info("Hardware DMA cache coherency enabled\n");
152	} else {
153		if (coherentio == 1)
154			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
155		else
156			pr_info("Software DMA cache coherency enabled\n");
157	}
158#else
159	if (!plat_enable_iocoherency())
160		panic("Hardware DMA cache coherency not supported!");
161#endif
162}
163
164static void __init pci_clock_check(void)
165{
166	unsigned int __iomem *jmpr_p =
167		(unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
168	int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
169	static const int pciclocks[] __initconst = {
170		33, 20, 25, 30, 12, 16, 37, 10
171	};
172	int pciclock = pciclocks[jmpr];
173	char *optptr, *argptr = fw_getcmdline();
174
175	/*
176	 * If user passed a pci_clock= option, don't tack on another one
177	 */
178	optptr = strstr(argptr, "pci_clock=");
179	if (optptr && (optptr == argptr || optptr[-1] == ' '))
180		return;
181
182	if (pciclock != 33) {
183		pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n",
184			pciclock);
185		argptr += strlen(argptr);
186		sprintf(argptr, " pci_clock=%d", pciclock);
187		if (pciclock < 20 || pciclock > 66)
188			pr_warn("WARNING: IDE timing calculations will be "
189			        "incorrect\n");
190	}
191}
192
193#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
194static void __init screen_info_setup(void)
195{
196	screen_info = (struct screen_info) {
197		.orig_x = 0,
198		.orig_y = 25,
199		.ext_mem_k = 0,
200		.orig_video_page = 0,
201		.orig_video_mode = 0,
202		.orig_video_cols = 80,
203		.unused2 = 0,
204		.orig_video_ega_bx = 0,
205		.unused3 = 0,
206		.orig_video_lines = 25,
207		.orig_video_isVGA = VIDEO_TYPE_VGAC,
208		.orig_video_points = 16
209	};
210}
211#endif
212
213static void __init bonito_quirks_setup(void)
214{
215	char *argptr;
216
217	argptr = fw_getcmdline();
218	if (strstr(argptr, "debug")) {
219		BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
220		pr_info("Enabled Bonito debug mode\n");
221	} else
222		BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
223
224#ifdef CONFIG_DMA_COHERENT
225	if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
226		BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
227		pr_info("Enabled Bonito CPU coherency\n");
228
229		argptr = fw_getcmdline();
230		if (strstr(argptr, "iobcuncached")) {
231			BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
232			BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
233				~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
234					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
235			pr_info("Disabled Bonito IOBC coherency\n");
236		} else {
237			BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
238			BONITO_PCIMEMBASECFG |=
239				(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
240					BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
241			pr_info("Enabled Bonito IOBC coherency\n");
242		}
243	} else
244		panic("Hardware DMA cache coherency not supported");
245#endif
246}
247
248void __init plat_mem_setup(void)
249{
250	unsigned int i;
251
252	if (config_enabled(CONFIG_EVA))
253		/* EVA has already been configured in mach-malta/kernel-init.h */
254		pr_info("Enhanced Virtual Addressing (EVA) activated\n");
255
256	mips_pcibios_init();
257
258	/* Request I/O space for devices used on the Malta board. */
259	for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
260		request_resource(&ioport_resource, standard_io_resources+i);
261
262	/*
263	 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
264	 */
265	enable_dma(4);
266
267#ifdef CONFIG_DMA_COHERENT
268	if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
269		panic("Hardware DMA cache coherency not supported");
270#endif
271
272	if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
273		bonito_quirks_setup();
274
275	plat_setup_iocoherency();
276
277	pci_clock_check();
278
279#ifdef CONFIG_BLK_DEV_FD
280	fd_activate();
281#endif
282
283#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
284	screen_info_setup();
285#endif
286
287	board_be_init = malta_be_init;
288	board_be_handler = malta_be_handler;
289}
290