1/*
2 * Copyright (C) 2001  Dave Engebretsen & Todd Inglett IBM Corporation.
3 * Copyright 2001-2012 IBM Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
18 */
19
20#ifndef _POWERPC_EEH_H
21#define _POWERPC_EEH_H
22#ifdef __KERNEL__
23
24#include <linux/init.h>
25#include <linux/list.h>
26#include <linux/string.h>
27#include <linux/time.h>
28#include <linux/atomic.h>
29
30struct pci_dev;
31struct pci_bus;
32struct pci_dn;
33
34#ifdef CONFIG_EEH
35
36/* EEH subsystem flags */
37#define EEH_ENABLED		0x01	/* EEH enabled		*/
38#define EEH_FORCE_DISABLED	0x02	/* EEH disabled		*/
39#define EEH_PROBE_MODE_DEV	0x04	/* From PCI device	*/
40#define EEH_PROBE_MODE_DEVTREE	0x08	/* From device tree	*/
41#define EEH_VALID_PE_ZERO	0x10	/* PE#0 is valid	*/
42#define EEH_ENABLE_IO_FOR_LOG	0x20	/* Enable IO for log	*/
43#define EEH_EARLY_DUMP_LOG	0x40	/* Dump log immediately	*/
44
45/*
46 * Delay for PE reset, all in ms
47 *
48 * PCI specification has reset hold time of 100 milliseconds.
49 * We have 250 milliseconds here. The PCI bus settlement time
50 * is specified as 1.5 seconds and we have 1.8 seconds.
51 */
52#define EEH_PE_RST_HOLD_TIME		250
53#define EEH_PE_RST_SETTLE_TIME		1800
54
55/*
56 * The struct is used to trace PE related EEH functionality.
57 * In theory, there will have one instance of the struct to
58 * be created against particular PE. In nature, PEs corelate
59 * to each other. the struct has to reflect that hierarchy in
60 * order to easily pick up those affected PEs when one particular
61 * PE has EEH errors.
62 *
63 * Also, one particular PE might be composed of PCI device, PCI
64 * bus and its subordinate components. The struct also need ship
65 * the information. Further more, one particular PE is only meaingful
66 * in the corresponding PHB. Therefore, the root PEs should be created
67 * against existing PHBs in on-to-one fashion.
68 */
69#define EEH_PE_INVALID	(1 << 0)	/* Invalid   */
70#define EEH_PE_PHB	(1 << 1)	/* PHB PE    */
71#define EEH_PE_DEVICE 	(1 << 2)	/* Device PE */
72#define EEH_PE_BUS	(1 << 3)	/* Bus PE    */
73
74#define EEH_PE_ISOLATED		(1 << 0)	/* Isolated PE		*/
75#define EEH_PE_RECOVERING	(1 << 1)	/* Recovering PE	*/
76#define EEH_PE_CFG_BLOCKED	(1 << 2)	/* Block config access	*/
77#define EEH_PE_RESET		(1 << 3)	/* PE reset in progress */
78
79#define EEH_PE_KEEP		(1 << 8)	/* Keep PE on hotplug	*/
80#define EEH_PE_CFG_RESTRICTED	(1 << 9)	/* Block config on error */
81#define EEH_PE_REMOVED		(1 << 10)	/* Removed permanently	*/
82#define EEH_PE_PRI_BUS		(1 << 11)	/* Cached primary bus   */
83
84struct eeh_pe {
85	int type;			/* PE type: PHB/Bus/Device	*/
86	int state;			/* PE EEH dependent mode	*/
87	int config_addr;		/* Traditional PCI address	*/
88	int addr;			/* PE configuration address	*/
89	struct pci_controller *phb;	/* Associated PHB		*/
90	struct pci_bus *bus;		/* Top PCI bus for bus PE	*/
91	int check_count;		/* Times of ignored error	*/
92	int freeze_count;		/* Times of froze up		*/
93	struct timeval tstamp;		/* Time on first-time freeze	*/
94	int false_positives;		/* Times of reported #ff's	*/
95	atomic_t pass_dev_cnt;		/* Count of passed through devs	*/
96	struct eeh_pe *parent;		/* Parent PE			*/
97	void *data;			/* PE auxillary data		*/
98	struct list_head child_list;	/* Link PE to the child list	*/
99	struct list_head edevs;		/* Link list of EEH devices	*/
100	struct list_head child;		/* Child PEs			*/
101};
102
103#define eeh_pe_for_each_dev(pe, edev, tmp) \
104		list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
105
106static inline bool eeh_pe_passed(struct eeh_pe *pe)
107{
108	return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
109}
110
111/*
112 * The struct is used to trace EEH state for the associated
113 * PCI device node or PCI device. In future, it might
114 * represent PE as well so that the EEH device to form
115 * another tree except the currently existing tree of PCI
116 * buses and PCI devices
117 */
118#define EEH_DEV_BRIDGE		(1 << 0)	/* PCI bridge		*/
119#define EEH_DEV_ROOT_PORT	(1 << 1)	/* PCIe root port	*/
120#define EEH_DEV_DS_PORT		(1 << 2)	/* Downstream port	*/
121#define EEH_DEV_IRQ_DISABLED	(1 << 3)	/* Interrupt disabled	*/
122#define EEH_DEV_DISCONNECTED	(1 << 4)	/* Removing from PE	*/
123
124#define EEH_DEV_NO_HANDLER	(1 << 8)	/* No error handler	*/
125#define EEH_DEV_SYSFS		(1 << 9)	/* Sysfs created	*/
126#define EEH_DEV_REMOVED		(1 << 10)	/* Removed permanently	*/
127
128struct eeh_dev {
129	int mode;			/* EEH mode			*/
130	int class_code;			/* Class code of the device	*/
131	int config_addr;		/* Config address		*/
132	int pe_config_addr;		/* PE config address		*/
133	u32 config_space[16];		/* Saved PCI config space	*/
134	int pcix_cap;			/* Saved PCIx capability	*/
135	int pcie_cap;			/* Saved PCIe capability	*/
136	int aer_cap;			/* Saved AER capability		*/
137	struct eeh_pe *pe;		/* Associated PE		*/
138	struct list_head list;		/* Form link list in the PE	*/
139	struct pci_controller *phb;	/* Associated PHB		*/
140	struct pci_dn *pdn;		/* Associated PCI device node	*/
141	struct pci_dev *pdev;		/* Associated PCI device	*/
142	struct pci_bus *bus;		/* PCI bus for partial hotplug	*/
143};
144
145static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
146{
147	return edev ? edev->pdn : NULL;
148}
149
150static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
151{
152	return edev ? edev->pdev : NULL;
153}
154
155static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
156{
157	return edev ? edev->pe : NULL;
158}
159
160/* Return values from eeh_ops::next_error */
161enum {
162	EEH_NEXT_ERR_NONE = 0,
163	EEH_NEXT_ERR_INF,
164	EEH_NEXT_ERR_FROZEN_PE,
165	EEH_NEXT_ERR_FENCED_PHB,
166	EEH_NEXT_ERR_DEAD_PHB,
167	EEH_NEXT_ERR_DEAD_IOC
168};
169
170/*
171 * The struct is used to trace the registered EEH operation
172 * callback functions. Actually, those operation callback
173 * functions are heavily platform dependent. That means the
174 * platform should register its own EEH operation callback
175 * functions before any EEH further operations.
176 */
177#define EEH_OPT_DISABLE		0	/* EEH disable	*/
178#define EEH_OPT_ENABLE		1	/* EEH enable	*/
179#define EEH_OPT_THAW_MMIO	2	/* MMIO enable	*/
180#define EEH_OPT_THAW_DMA	3	/* DMA enable	*/
181#define EEH_OPT_FREEZE_PE	4	/* Freeze PE	*/
182#define EEH_STATE_UNAVAILABLE	(1 << 0)	/* State unavailable	*/
183#define EEH_STATE_NOT_SUPPORT	(1 << 1)	/* EEH not supported	*/
184#define EEH_STATE_RESET_ACTIVE	(1 << 2)	/* Active reset		*/
185#define EEH_STATE_MMIO_ACTIVE	(1 << 3)	/* Active MMIO		*/
186#define EEH_STATE_DMA_ACTIVE	(1 << 4)	/* Active DMA		*/
187#define EEH_STATE_MMIO_ENABLED	(1 << 5)	/* MMIO enabled		*/
188#define EEH_STATE_DMA_ENABLED	(1 << 6)	/* DMA enabled		*/
189#define EEH_PE_STATE_NORMAL		0	/* Normal state		*/
190#define EEH_PE_STATE_RESET		1	/* PE reset asserted	*/
191#define EEH_PE_STATE_STOPPED_IO_DMA	2	/* Frozen PE		*/
192#define EEH_PE_STATE_STOPPED_DMA	4	/* Stopped DMA, Enabled IO */
193#define EEH_PE_STATE_UNAVAIL		5	/* Unavailable		*/
194#define EEH_RESET_DEACTIVATE	0	/* Deactivate the PE reset	*/
195#define EEH_RESET_HOT		1	/* Hot reset			*/
196#define EEH_RESET_FUNDAMENTAL	3	/* Fundamental reset		*/
197#define EEH_LOG_TEMP		1	/* EEH temporary error log	*/
198#define EEH_LOG_PERM		2	/* EEH permanent error log	*/
199
200struct eeh_ops {
201	char *name;
202	int (*init)(void);
203	int (*post_init)(void);
204	void* (*probe)(struct pci_dn *pdn, void *data);
205	int (*set_option)(struct eeh_pe *pe, int option);
206	int (*get_pe_addr)(struct eeh_pe *pe);
207	int (*get_state)(struct eeh_pe *pe, int *state);
208	int (*reset)(struct eeh_pe *pe, int option);
209	int (*wait_state)(struct eeh_pe *pe, int max_wait);
210	int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
211	int (*configure_bridge)(struct eeh_pe *pe);
212	int (*err_inject)(struct eeh_pe *pe, int type, int func,
213			  unsigned long addr, unsigned long mask);
214	int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
215	int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
216	int (*next_error)(struct eeh_pe **pe);
217	int (*restore_config)(struct pci_dn *pdn);
218};
219
220extern int eeh_subsystem_flags;
221extern int eeh_max_freezes;
222extern struct eeh_ops *eeh_ops;
223extern raw_spinlock_t confirm_error_lock;
224
225static inline void eeh_add_flag(int flag)
226{
227	eeh_subsystem_flags |= flag;
228}
229
230static inline void eeh_clear_flag(int flag)
231{
232	eeh_subsystem_flags &= ~flag;
233}
234
235static inline bool eeh_has_flag(int flag)
236{
237        return !!(eeh_subsystem_flags & flag);
238}
239
240static inline bool eeh_enabled(void)
241{
242	if (eeh_has_flag(EEH_FORCE_DISABLED) ||
243	    !eeh_has_flag(EEH_ENABLED))
244		return false;
245
246	return true;
247}
248
249static inline void eeh_serialize_lock(unsigned long *flags)
250{
251	raw_spin_lock_irqsave(&confirm_error_lock, *flags);
252}
253
254static inline void eeh_serialize_unlock(unsigned long flags)
255{
256	raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
257}
258
259typedef void *(*eeh_traverse_func)(void *data, void *flag);
260void eeh_set_pe_aux_size(int size);
261int eeh_phb_pe_create(struct pci_controller *phb);
262struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
263struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
264int eeh_add_to_parent_pe(struct eeh_dev *edev);
265int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
266void eeh_pe_update_time_stamp(struct eeh_pe *pe);
267void *eeh_pe_traverse(struct eeh_pe *root,
268		eeh_traverse_func fn, void *flag);
269void *eeh_pe_dev_traverse(struct eeh_pe *root,
270		eeh_traverse_func fn, void *flag);
271void eeh_pe_restore_bars(struct eeh_pe *pe);
272const char *eeh_pe_loc_get(struct eeh_pe *pe);
273struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
274
275void *eeh_dev_init(struct pci_dn *pdn, void *data);
276void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
277int eeh_init(void);
278int __init eeh_ops_register(struct eeh_ops *ops);
279int __exit eeh_ops_unregister(const char *name);
280int eeh_check_failure(const volatile void __iomem *token);
281int eeh_dev_check_failure(struct eeh_dev *edev);
282void eeh_addr_cache_build(void);
283void eeh_add_device_early(struct pci_dn *);
284void eeh_add_device_tree_early(struct pci_dn *);
285void eeh_add_device_late(struct pci_dev *);
286void eeh_add_device_tree_late(struct pci_bus *);
287void eeh_add_sysfs_files(struct pci_bus *);
288void eeh_remove_device(struct pci_dev *);
289int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
290int eeh_pe_reset_and_recover(struct eeh_pe *pe);
291int eeh_dev_open(struct pci_dev *pdev);
292void eeh_dev_release(struct pci_dev *pdev);
293struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
294int eeh_pe_set_option(struct eeh_pe *pe, int option);
295int eeh_pe_get_state(struct eeh_pe *pe);
296int eeh_pe_reset(struct eeh_pe *pe, int option);
297int eeh_pe_configure(struct eeh_pe *pe);
298
299/**
300 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
301 *
302 * If this macro yields TRUE, the caller relays to eeh_check_failure()
303 * which does further tests out of line.
304 */
305#define EEH_POSSIBLE_ERROR(val, type)	((val) == (type)~0 && eeh_enabled())
306
307/*
308 * Reads from a device which has been isolated by EEH will return
309 * all 1s.  This macro gives an all-1s value of the given size (in
310 * bytes: 1, 2, or 4) for comparing with the result of a read.
311 */
312#define EEH_IO_ERROR_VALUE(size)	(~0U >> ((4 - (size)) * 8))
313
314#else /* !CONFIG_EEH */
315
316static inline bool eeh_enabled(void)
317{
318        return false;
319}
320
321static inline int eeh_init(void)
322{
323	return 0;
324}
325
326static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
327{
328	return NULL;
329}
330
331static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
332
333static inline int eeh_check_failure(const volatile void __iomem *token)
334{
335	return 0;
336}
337
338#define eeh_dev_check_failure(x) (0)
339
340#define eeh_addr_cache_build()
341#define eeh_add_device_early(pdn)
342#define eeh_add_device_tree_early(pdn)
343#define eeh_add_device_late(pdev)
344#define eeh_add_device_tree_late(pbus)
345#define eeh_add_sysfs_files(pbus)
346#define eeh_remove_device(pdev)
347
348#define EEH_POSSIBLE_ERROR(val, type) (0)
349#define EEH_IO_ERROR_VALUE(size) (-1UL)
350#endif /* CONFIG_EEH */
351
352#ifdef CONFIG_PPC64
353/*
354 * MMIO read/write operations with EEH support.
355 */
356static inline u8 eeh_readb(const volatile void __iomem *addr)
357{
358	u8 val = in_8(addr);
359	if (EEH_POSSIBLE_ERROR(val, u8))
360		eeh_check_failure(addr);
361	return val;
362}
363
364static inline u16 eeh_readw(const volatile void __iomem *addr)
365{
366	u16 val = in_le16(addr);
367	if (EEH_POSSIBLE_ERROR(val, u16))
368		eeh_check_failure(addr);
369	return val;
370}
371
372static inline u32 eeh_readl(const volatile void __iomem *addr)
373{
374	u32 val = in_le32(addr);
375	if (EEH_POSSIBLE_ERROR(val, u32))
376		eeh_check_failure(addr);
377	return val;
378}
379
380static inline u64 eeh_readq(const volatile void __iomem *addr)
381{
382	u64 val = in_le64(addr);
383	if (EEH_POSSIBLE_ERROR(val, u64))
384		eeh_check_failure(addr);
385	return val;
386}
387
388static inline u16 eeh_readw_be(const volatile void __iomem *addr)
389{
390	u16 val = in_be16(addr);
391	if (EEH_POSSIBLE_ERROR(val, u16))
392		eeh_check_failure(addr);
393	return val;
394}
395
396static inline u32 eeh_readl_be(const volatile void __iomem *addr)
397{
398	u32 val = in_be32(addr);
399	if (EEH_POSSIBLE_ERROR(val, u32))
400		eeh_check_failure(addr);
401	return val;
402}
403
404static inline u64 eeh_readq_be(const volatile void __iomem *addr)
405{
406	u64 val = in_be64(addr);
407	if (EEH_POSSIBLE_ERROR(val, u64))
408		eeh_check_failure(addr);
409	return val;
410}
411
412static inline void eeh_memcpy_fromio(void *dest, const
413				     volatile void __iomem *src,
414				     unsigned long n)
415{
416	_memcpy_fromio(dest, src, n);
417
418	/* Look for ffff's here at dest[n].  Assume that at least 4 bytes
419	 * were copied. Check all four bytes.
420	 */
421	if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
422		eeh_check_failure(src);
423}
424
425/* in-string eeh macros */
426static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
427			      int ns)
428{
429	_insb(addr, buf, ns);
430	if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
431		eeh_check_failure(addr);
432}
433
434static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
435			      int ns)
436{
437	_insw(addr, buf, ns);
438	if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
439		eeh_check_failure(addr);
440}
441
442static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
443			      int nl)
444{
445	_insl(addr, buf, nl);
446	if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
447		eeh_check_failure(addr);
448}
449
450#endif /* CONFIG_PPC64 */
451#endif /* __KERNEL__ */
452#endif /* _POWERPC_EEH_H */
453