1#ifndef __HEAD_BOOKE_H__ 2#define __HEAD_BOOKE_H__ 3 4#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */ 5#include <asm/kvm_asm.h> 6#include <asm/kvm_booke_hv_asm.h> 7 8/* 9 * Macros used for common Book-e exception handling 10 */ 11 12#define SET_IVOR(vector_number, vector_label) \ 13 li r26,vector_label@l; \ 14 mtspr SPRN_IVOR##vector_number,r26; \ 15 sync 16 17#if (THREAD_SHIFT < 15) 18#define ALLOC_STACK_FRAME(reg, val) \ 19 addi reg,reg,val 20#else 21#define ALLOC_STACK_FRAME(reg, val) \ 22 addis reg,reg,val@ha; \ 23 addi reg,reg,val@l 24#endif 25 26/* 27 * Macro used to get to thread save registers. 28 * Note that entries 0-3 are used for the prolog code, and the remaining 29 * entries are available for specific exception use in the event a handler 30 * requires more than 4 scratch registers. 31 */ 32#define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4)) 33 34#define NORMAL_EXCEPTION_PROLOG(intno) \ 35 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 36 mfspr r10, SPRN_SPRG_THREAD; \ 37 stw r11, THREAD_NORMSAVE(0)(r10); \ 38 stw r13, THREAD_NORMSAVE(2)(r10); \ 39 mfcr r13; /* save CR in r13 for now */\ 40 mfspr r11, SPRN_SRR1; \ 41 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ 42 andi. r11, r11, MSR_PR; /* check whether user or kernel */\ 43 mr r11, r1; \ 44 beq 1f; \ 45 /* if from user, start at top of this thread's kernel stack */ \ 46 lwz r11, THREAD_INFO-THREAD(r10); \ 47 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ 481 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \ 49 stw r13, _CCR(r11); /* save various registers */ \ 50 stw r12,GPR12(r11); \ 51 stw r9,GPR9(r11); \ 52 mfspr r13, SPRN_SPRG_RSCRATCH0; \ 53 stw r13, GPR10(r11); \ 54 lwz r12, THREAD_NORMSAVE(0)(r10); \ 55 stw r12,GPR11(r11); \ 56 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \ 57 mflr r10; \ 58 stw r10,_LINK(r11); \ 59 mfspr r12,SPRN_SRR0; \ 60 stw r1, GPR1(r11); \ 61 mfspr r9,SPRN_SRR1; \ 62 stw r1, 0(r11); \ 63 mr r1, r11; \ 64 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 65 stw r0,GPR0(r11); \ 66 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \ 67 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \ 68 stw r10, 8(r11); \ 69 SAVE_4GPRS(3, r11); \ 70 SAVE_2GPRS(7, r11) 71 72/* To handle the additional exception priority levels on 40x and Book-E 73 * processors we allocate a stack per additional priority level. 74 * 75 * On 40x critical is the only additional level 76 * On 44x/e500 we have critical and machine check 77 * On e200 we have critical and debug (machine check occurs via critical) 78 * 79 * Additionally we reserve a SPRG for each priority level so we can free up a 80 * GPR to use as the base for indirect access to the exception stacks. This 81 * is necessary since the MMU is always on, for Book-E parts, and the stacks 82 * are offset from KERNELBASE. 83 * 84 * There is some space optimization to be had here if desired. However 85 * to allow for a common kernel with support for debug exceptions either 86 * going to critical or their own debug level we aren't currently 87 * providing configurations that micro-optimize space usage. 88 */ 89 90#define MC_STACK_BASE mcheckirq_ctx 91#define CRIT_STACK_BASE critirq_ctx 92 93/* only on e500mc/e200 */ 94#define DBG_STACK_BASE dbgirq_ctx 95 96#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) 97 98#ifdef CONFIG_SMP 99#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 100 mfspr r8,SPRN_PIR; \ 101 slwi r8,r8,2; \ 102 addis r8,r8,level##_STACK_BASE@ha; \ 103 lwz r8,level##_STACK_BASE@l(r8); \ 104 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 105#else 106#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ 107 lis r8,level##_STACK_BASE@ha; \ 108 lwz r8,level##_STACK_BASE@l(r8); \ 109 addi r8,r8,EXC_LVL_FRAME_OVERHEAD; 110#endif 111 112/* 113 * Exception prolog for critical/machine check exceptions. This is a 114 * little different from the normal exception prolog above since a 115 * critical/machine check exception can potentially occur at any point 116 * during normal exception processing. Thus we cannot use the same SPRG 117 * registers as the normal prolog above. Instead we use a portion of the 118 * critical/machine check exception stack at low physical addresses. 119 */ 120#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \ 121 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \ 122 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ 123 stw r9,GPR9(r8); /* save various registers */\ 124 mfcr r9; /* save CR in r9 for now */\ 125 stw r10,GPR10(r8); \ 126 stw r11,GPR11(r8); \ 127 stw r9,_CCR(r8); /* save CR on stack */\ 128 mfspr r11,exc_level_srr1; /* check whether user or kernel */\ 129 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ 130 andi. r11,r11,MSR_PR; \ 131 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ 132 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\ 133 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ 134 beq 1f; \ 135 /* COMING FROM USER MODE */ \ 136 stw r9,_CCR(r11); /* save CR */\ 137 lwz r10,GPR10(r8); /* copy regs from exception stack */\ 138 lwz r9,GPR9(r8); \ 139 stw r10,GPR10(r11); \ 140 lwz r10,GPR11(r8); \ 141 stw r9,GPR9(r11); \ 142 stw r10,GPR11(r11); \ 143 b 2f; \ 144 /* COMING FROM PRIV MODE */ \ 1451: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \ 146 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \ 147 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \ 148 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \ 149 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \ 150 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \ 151 mr r11,r8; \ 1522: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \ 153 stw r12,GPR12(r11); /* save various registers */\ 154 mflr r10; \ 155 stw r10,_LINK(r11); \ 156 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ 157 stw r12,_DEAR(r11); /* since they may have had stuff */\ 158 mfspr r9,SPRN_ESR; /* in them at the point where the */\ 159 stw r9,_ESR(r11); /* exception was taken */\ 160 mfspr r12,exc_level_srr0; \ 161 stw r1,GPR1(r11); \ 162 mfspr r9,exc_level_srr1; \ 163 stw r1,0(r11); \ 164 mr r1,r11; \ 165 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ 166 stw r0,GPR0(r11); \ 167 SAVE_4GPRS(3, r11); \ 168 SAVE_2GPRS(7, r11) 169 170#define CRITICAL_EXCEPTION_PROLOG(intno) \ 171 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1) 172#define DEBUG_EXCEPTION_PROLOG \ 173 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1) 174#define MCHECK_EXCEPTION_PROLOG \ 175 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \ 176 SPRN_MCSRR0, SPRN_MCSRR1) 177 178/* 179 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite 180 * being delivered to the host. This exception can only happen 181 * inside a KVM guest -- so we just handle up to the DO_KVM rather 182 * than try to fit this into one of the existing prolog macros. 183 */ 184#define GUEST_DOORBELL_EXCEPTION \ 185 START_EXCEPTION(GuestDoorbell); \ 186 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ 187 mfspr r10, SPRN_SPRG_THREAD; \ 188 stw r11, THREAD_NORMSAVE(0)(r10); \ 189 mfspr r11, SPRN_SRR1; \ 190 stw r13, THREAD_NORMSAVE(2)(r10); \ 191 mfcr r13; /* save CR in r13 for now */\ 192 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \ 193 trap 194 195/* 196 * Exception vectors. 197 */ 198#define START_EXCEPTION(label) \ 199 .align 5; \ 200label: 201 202#define EXCEPTION(n, intno, label, hdlr, xfer) \ 203 START_EXCEPTION(label); \ 204 NORMAL_EXCEPTION_PROLOG(intno); \ 205 addi r3,r1,STACK_FRAME_OVERHEAD; \ 206 xfer(n, hdlr) 207 208#define CRITICAL_EXCEPTION(n, intno, label, hdlr) \ 209 START_EXCEPTION(label); \ 210 CRITICAL_EXCEPTION_PROLOG(intno); \ 211 addi r3,r1,STACK_FRAME_OVERHEAD; \ 212 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 213 NOCOPY, crit_transfer_to_handler, \ 214 ret_from_crit_exc) 215 216#define MCHECK_EXCEPTION(n, label, hdlr) \ 217 START_EXCEPTION(label); \ 218 MCHECK_EXCEPTION_PROLOG; \ 219 mfspr r5,SPRN_ESR; \ 220 stw r5,_ESR(r11); \ 221 addi r3,r1,STACK_FRAME_OVERHEAD; \ 222 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \ 223 NOCOPY, mcheck_transfer_to_handler, \ 224 ret_from_mcheck_exc) 225 226#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \ 227 li r10,trap; \ 228 stw r10,_TRAP(r11); \ 229 lis r10,msr@h; \ 230 ori r10,r10,msr@l; \ 231 copyee(r10, r9); \ 232 bl tfer; \ 233 .long hdlr; \ 234 .long ret 235 236#define COPY_EE(d, s) rlwimi d,s,0,16,16 237#define NOCOPY(d, s) 238 239#define EXC_XFER_STD(n, hdlr) \ 240 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \ 241 ret_from_except_full) 242 243#define EXC_XFER_LITE(n, hdlr) \ 244 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \ 245 ret_from_except) 246 247#define EXC_XFER_EE(n, hdlr) \ 248 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \ 249 ret_from_except_full) 250 251#define EXC_XFER_EE_LITE(n, hdlr) \ 252 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \ 253 ret_from_except) 254 255/* Check for a single step debug exception while in an exception 256 * handler before state has been saved. This is to catch the case 257 * where an instruction that we are trying to single step causes 258 * an exception (eg ITLB/DTLB miss) and thus the first instruction of 259 * the exception handler generates a single step debug exception. 260 * 261 * If we get a debug trap on the first instruction of an exception handler, 262 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is 263 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). 264 * The exception handler was handling a non-critical interrupt, so it will 265 * save (and later restore) the MSR via SPRN_CSRR1, which will still have 266 * the MSR_DE bit set. 267 */ 268#define DEBUG_DEBUG_EXCEPTION \ 269 START_EXCEPTION(DebugDebug); \ 270 DEBUG_EXCEPTION_PROLOG; \ 271 \ 272 /* \ 273 * If there is a single step or branch-taken exception in an \ 274 * exception entry sequence, it was probably meant to apply to \ 275 * the code where the exception occurred (since exception entry \ 276 * doesn't turn off DE automatically). We simulate the effect \ 277 * of turning off DE on entry to an exception handler by turning \ 278 * off DE in the DSRR1 value and clearing the debug status. \ 279 */ \ 280 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 281 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 282 beq+ 2f; \ 283 \ 284 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 285 ori r10,r10,interrupt_base@l; \ 286 cmplw r12,r10; \ 287 blt+ 2f; /* addr below exception vectors */ \ 288 \ 289 lis r10,interrupt_end@h; \ 290 ori r10,r10,interrupt_end@l; \ 291 cmplw r12,r10; \ 292 bgt+ 2f; /* addr above exception vectors */ \ 293 \ 294 /* here it looks like we got an inappropriate debug exception. */ \ 2951: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ 296 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 297 mtspr SPRN_DBSR,r10; \ 298 /* restore state and get out */ \ 299 lwz r10,_CCR(r11); \ 300 lwz r0,GPR0(r11); \ 301 lwz r1,GPR1(r11); \ 302 mtcrf 0x80,r10; \ 303 mtspr SPRN_DSRR0,r12; \ 304 mtspr SPRN_DSRR1,r9; \ 305 lwz r9,GPR9(r11); \ 306 lwz r12,GPR12(r11); \ 307 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \ 308 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \ 309 lwz r10,GPR10(r8); \ 310 lwz r11,GPR11(r8); \ 311 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \ 312 \ 313 PPC_RFDI; \ 314 b .; \ 315 \ 316 /* continue normal handling for a debug exception... */ \ 3172: mfspr r4,SPRN_DBSR; \ 318 addi r3,r1,STACK_FRAME_OVERHEAD; \ 319 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) 320 321#define DEBUG_CRIT_EXCEPTION \ 322 START_EXCEPTION(DebugCrit); \ 323 CRITICAL_EXCEPTION_PROLOG(DEBUG); \ 324 \ 325 /* \ 326 * If there is a single step or branch-taken exception in an \ 327 * exception entry sequence, it was probably meant to apply to \ 328 * the code where the exception occurred (since exception entry \ 329 * doesn't turn off DE automatically). We simulate the effect \ 330 * of turning off DE on entry to an exception handler by turning \ 331 * off DE in the CSRR1 value and clearing the debug status. \ 332 */ \ 333 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 334 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ 335 beq+ 2f; \ 336 \ 337 lis r10,interrupt_base@h; /* check if exception in vectors */ \ 338 ori r10,r10,interrupt_base@l; \ 339 cmplw r12,r10; \ 340 blt+ 2f; /* addr below exception vectors */ \ 341 \ 342 lis r10,interrupt_end@h; \ 343 ori r10,r10,interrupt_end@l; \ 344 cmplw r12,r10; \ 345 bgt+ 2f; /* addr above exception vectors */ \ 346 \ 347 /* here it looks like we got an inappropriate debug exception. */ \ 3481: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ 349 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ 350 mtspr SPRN_DBSR,r10; \ 351 /* restore state and get out */ \ 352 lwz r10,_CCR(r11); \ 353 lwz r0,GPR0(r11); \ 354 lwz r1,GPR1(r11); \ 355 mtcrf 0x80,r10; \ 356 mtspr SPRN_CSRR0,r12; \ 357 mtspr SPRN_CSRR1,r9; \ 358 lwz r9,GPR9(r11); \ 359 lwz r12,GPR12(r11); \ 360 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \ 361 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ 362 lwz r10,GPR10(r8); \ 363 lwz r11,GPR11(r8); \ 364 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \ 365 \ 366 rfci; \ 367 b .; \ 368 \ 369 /* continue normal handling for a critical exception... */ \ 3702: mfspr r4,SPRN_DBSR; \ 371 addi r3,r1,STACK_FRAME_OVERHEAD; \ 372 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) 373 374#define DATA_STORAGE_EXCEPTION \ 375 START_EXCEPTION(DataStorage) \ 376 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \ 377 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 378 stw r5,_ESR(r11); \ 379 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ 380 EXC_XFER_LITE(0x0300, handle_page_fault) 381 382#define INSTRUCTION_STORAGE_EXCEPTION \ 383 START_EXCEPTION(InstructionStorage) \ 384 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \ 385 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ 386 stw r5,_ESR(r11); \ 387 mr r4,r12; /* Pass SRR0 as arg2 */ \ 388 li r5,0; /* Pass zero as arg3 */ \ 389 EXC_XFER_LITE(0x0400, handle_page_fault) 390 391#define ALIGNMENT_EXCEPTION \ 392 START_EXCEPTION(Alignment) \ 393 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \ 394 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ 395 stw r4,_DEAR(r11); \ 396 addi r3,r1,STACK_FRAME_OVERHEAD; \ 397 EXC_XFER_EE(0x0600, alignment_exception) 398 399#define PROGRAM_EXCEPTION \ 400 START_EXCEPTION(Program) \ 401 NORMAL_EXCEPTION_PROLOG(PROGRAM); \ 402 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ 403 stw r4,_ESR(r11); \ 404 addi r3,r1,STACK_FRAME_OVERHEAD; \ 405 EXC_XFER_STD(0x0700, program_check_exception) 406 407#define DECREMENTER_EXCEPTION \ 408 START_EXCEPTION(Decrementer) \ 409 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \ 410 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ 411 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ 412 addi r3,r1,STACK_FRAME_OVERHEAD; \ 413 EXC_XFER_LITE(0x0900, timer_interrupt) 414 415#define FP_UNAVAILABLE_EXCEPTION \ 416 START_EXCEPTION(FloatingPointUnavailable) \ 417 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \ 418 beq 1f; \ 419 bl load_up_fpu; /* if from user, just load it up */ \ 420 b fast_exception_return; \ 4211: addi r3,r1,STACK_FRAME_OVERHEAD; \ 422 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) 423 424#ifndef __ASSEMBLY__ 425struct exception_regs { 426 unsigned long mas0; 427 unsigned long mas1; 428 unsigned long mas2; 429 unsigned long mas3; 430 unsigned long mas6; 431 unsigned long mas7; 432 unsigned long srr0; 433 unsigned long srr1; 434 unsigned long csrr0; 435 unsigned long csrr1; 436 unsigned long dsrr0; 437 unsigned long dsrr1; 438 unsigned long saved_ksp_limit; 439}; 440 441/* ensure this structure is always sized to a multiple of the stack alignment */ 442#define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16) 443 444#endif /* __ASSEMBLY__ */ 445#endif /* __HEAD_BOOKE_H__ */ 446