1/* 2 * IOMMU implementation for Cell Broadband Processor Architecture 3 * 4 * (C) Copyright IBM Corporation 2006-2008 5 * 6 * Author: Jeremy Kerr <jk@ozlabs.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2, or (at your option) 11 * any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#undef DEBUG 24 25#include <linux/kernel.h> 26#include <linux/init.h> 27#include <linux/interrupt.h> 28#include <linux/notifier.h> 29#include <linux/of.h> 30#include <linux/of_platform.h> 31#include <linux/slab.h> 32#include <linux/memblock.h> 33 34#include <asm/prom.h> 35#include <asm/iommu.h> 36#include <asm/machdep.h> 37#include <asm/pci-bridge.h> 38#include <asm/udbg.h> 39#include <asm/firmware.h> 40#include <asm/cell-regs.h> 41 42#include "cell.h" 43#include "interrupt.h" 44 45/* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages 46 * instead of leaving them mapped to some dummy page. This can be 47 * enabled once the appropriate workarounds for spider bugs have 48 * been enabled 49 */ 50#define CELL_IOMMU_REAL_UNMAP 51 52/* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of 53 * IO PTEs based on the transfer direction. That can be enabled 54 * once spider-net has been fixed to pass the correct direction 55 * to the DMA mapping functions 56 */ 57#define CELL_IOMMU_STRICT_PROTECTION 58 59 60#define NR_IOMMUS 2 61 62/* IOC mmap registers */ 63#define IOC_Reg_Size 0x2000 64 65#define IOC_IOPT_CacheInvd 0x908 66#define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul 67#define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul 68#define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul 69 70#define IOC_IOST_Origin 0x918 71#define IOC_IOST_Origin_E 0x8000000000000000ul 72#define IOC_IOST_Origin_HW 0x0000000000000800ul 73#define IOC_IOST_Origin_HL 0x0000000000000400ul 74 75#define IOC_IO_ExcpStat 0x920 76#define IOC_IO_ExcpStat_V 0x8000000000000000ul 77#define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul 78#define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul 79#define IOC_IO_ExcpStat_SPF_P 0x2000000000000000ul 80#define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul 81#define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul 82#define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful 83 84#define IOC_IO_ExcpMask 0x928 85#define IOC_IO_ExcpMask_SFE 0x4000000000000000ul 86#define IOC_IO_ExcpMask_PFE 0x2000000000000000ul 87 88#define IOC_IOCmd_Offset 0x1000 89 90#define IOC_IOCmd_Cfg 0xc00 91#define IOC_IOCmd_Cfg_TE 0x0000800000000000ul 92 93 94/* Segment table entries */ 95#define IOSTE_V 0x8000000000000000ul /* valid */ 96#define IOSTE_H 0x4000000000000000ul /* cache hint */ 97#define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */ 98#define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */ 99#define IOSTE_PS_Mask 0x0000000000000007ul /* page size */ 100#define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */ 101#define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */ 102#define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */ 103#define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */ 104 105 106/* IOMMU sizing */ 107#define IO_SEGMENT_SHIFT 28 108#define IO_PAGENO_BITS(shift) (IO_SEGMENT_SHIFT - (shift)) 109 110/* The high bit needs to be set on every DMA address */ 111#define SPIDER_DMA_OFFSET 0x80000000ul 112 113struct iommu_window { 114 struct list_head list; 115 struct cbe_iommu *iommu; 116 unsigned long offset; 117 unsigned long size; 118 unsigned int ioid; 119 struct iommu_table table; 120}; 121 122#define NAMESIZE 8 123struct cbe_iommu { 124 int nid; 125 char name[NAMESIZE]; 126 void __iomem *xlate_regs; 127 void __iomem *cmd_regs; 128 unsigned long *stab; 129 unsigned long *ptab; 130 void *pad_page; 131 struct list_head windows; 132}; 133 134/* Static array of iommus, one per node 135 * each contains a list of windows, keyed from dma_window property 136 * - on bus setup, look for a matching window, or create one 137 * - on dev setup, assign iommu_table ptr 138 */ 139static struct cbe_iommu iommus[NR_IOMMUS]; 140static int cbe_nr_iommus; 141 142static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, 143 long n_ptes) 144{ 145 u64 __iomem *reg; 146 u64 val; 147 long n; 148 149 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; 150 151 while (n_ptes > 0) { 152 /* we can invalidate up to 1 << 11 PTEs at once */ 153 n = min(n_ptes, 1l << 11); 154 val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask) 155 | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask) 156 | IOC_IOPT_CacheInvd_Busy; 157 158 out_be64(reg, val); 159 while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy) 160 ; 161 162 n_ptes -= n; 163 pte += n; 164 } 165} 166 167static int tce_build_cell(struct iommu_table *tbl, long index, long npages, 168 unsigned long uaddr, enum dma_data_direction direction, 169 struct dma_attrs *attrs) 170{ 171 int i; 172 unsigned long *io_pte, base_pte; 173 struct iommu_window *window = 174 container_of(tbl, struct iommu_window, table); 175 176 /* implementing proper protection causes problems with the spidernet 177 * driver - check mapping directions later, but allow read & write by 178 * default for now.*/ 179#ifdef CELL_IOMMU_STRICT_PROTECTION 180 /* to avoid referencing a global, we use a trick here to setup the 181 * protection bit. "prot" is setup to be 3 fields of 4 bits apprended 182 * together for each of the 3 supported direction values. It is then 183 * shifted left so that the fields matching the desired direction 184 * lands on the appropriate bits, and other bits are masked out. 185 */ 186 const unsigned long prot = 0xc48; 187 base_pte = 188 ((prot << (52 + 4 * direction)) & 189 (CBE_IOPTE_PP_W | CBE_IOPTE_PP_R)) | 190 CBE_IOPTE_M | CBE_IOPTE_SO_RW | 191 (window->ioid & CBE_IOPTE_IOID_Mask); 192#else 193 base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M | 194 CBE_IOPTE_SO_RW | (window->ioid & CBE_IOPTE_IOID_Mask); 195#endif 196 if (unlikely(dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs))) 197 base_pte &= ~CBE_IOPTE_SO_RW; 198 199 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 200 201 for (i = 0; i < npages; i++, uaddr += (1 << tbl->it_page_shift)) 202 io_pte[i] = base_pte | (__pa(uaddr) & CBE_IOPTE_RPN_Mask); 203 204 mb(); 205 206 invalidate_tce_cache(window->iommu, io_pte, npages); 207 208 pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n", 209 index, npages, direction, base_pte); 210 return 0; 211} 212 213static void tce_free_cell(struct iommu_table *tbl, long index, long npages) 214{ 215 216 int i; 217 unsigned long *io_pte, pte; 218 struct iommu_window *window = 219 container_of(tbl, struct iommu_window, table); 220 221 pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages); 222 223#ifdef CELL_IOMMU_REAL_UNMAP 224 pte = 0; 225#else 226 /* spider bridge does PCI reads after freeing - insert a mapping 227 * to a scratch page instead of an invalid entry */ 228 pte = CBE_IOPTE_PP_R | CBE_IOPTE_M | CBE_IOPTE_SO_RW | 229 __pa(window->iommu->pad_page) | 230 (window->ioid & CBE_IOPTE_IOID_Mask); 231#endif 232 233 io_pte = (unsigned long *)tbl->it_base + (index - tbl->it_offset); 234 235 for (i = 0; i < npages; i++) 236 io_pte[i] = pte; 237 238 mb(); 239 240 invalidate_tce_cache(window->iommu, io_pte, npages); 241} 242 243static irqreturn_t ioc_interrupt(int irq, void *data) 244{ 245 unsigned long stat, spf; 246 struct cbe_iommu *iommu = data; 247 248 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 249 spf = stat & IOC_IO_ExcpStat_SPF_Mask; 250 251 /* Might want to rate limit it */ 252 printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat); 253 printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n", 254 !!(stat & IOC_IO_ExcpStat_V), 255 (spf == IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ', 256 (spf == IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ', 257 (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write", 258 (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask)); 259 printk(KERN_ERR " page=0x%016lx\n", 260 stat & IOC_IO_ExcpStat_ADDR_Mask); 261 262 /* clear interrupt */ 263 stat &= ~IOC_IO_ExcpStat_V; 264 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); 265 266 return IRQ_HANDLED; 267} 268 269static int cell_iommu_find_ioc(int nid, unsigned long *base) 270{ 271 struct device_node *np; 272 struct resource r; 273 274 *base = 0; 275 276 /* First look for new style /be nodes */ 277 for_each_node_by_name(np, "ioc") { 278 if (of_node_to_nid(np) != nid) 279 continue; 280 if (of_address_to_resource(np, 0, &r)) { 281 printk(KERN_ERR "iommu: can't get address for %s\n", 282 np->full_name); 283 continue; 284 } 285 *base = r.start; 286 of_node_put(np); 287 return 0; 288 } 289 290 /* Ok, let's try the old way */ 291 for_each_node_by_type(np, "cpu") { 292 const unsigned int *nidp; 293 const unsigned long *tmp; 294 295 nidp = of_get_property(np, "node-id", NULL); 296 if (nidp && *nidp == nid) { 297 tmp = of_get_property(np, "ioc-translation", NULL); 298 if (tmp) { 299 *base = *tmp; 300 of_node_put(np); 301 return 0; 302 } 303 } 304 } 305 306 return -ENODEV; 307} 308 309static void cell_iommu_setup_stab(struct cbe_iommu *iommu, 310 unsigned long dbase, unsigned long dsize, 311 unsigned long fbase, unsigned long fsize) 312{ 313 struct page *page; 314 unsigned long segments, stab_size; 315 316 segments = max(dbase + dsize, fbase + fsize) >> IO_SEGMENT_SHIFT; 317 318 pr_debug("%s: iommu[%d]: segments: %lu\n", 319 __func__, iommu->nid, segments); 320 321 /* set up the segment table */ 322 stab_size = segments * sizeof(unsigned long); 323 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size)); 324 BUG_ON(!page); 325 iommu->stab = page_address(page); 326 memset(iommu->stab, 0, stab_size); 327} 328 329static unsigned long *cell_iommu_alloc_ptab(struct cbe_iommu *iommu, 330 unsigned long base, unsigned long size, unsigned long gap_base, 331 unsigned long gap_size, unsigned long page_shift) 332{ 333 struct page *page; 334 int i; 335 unsigned long reg, segments, pages_per_segment, ptab_size, 336 n_pte_pages, start_seg, *ptab; 337 338 start_seg = base >> IO_SEGMENT_SHIFT; 339 segments = size >> IO_SEGMENT_SHIFT; 340 pages_per_segment = 1ull << IO_PAGENO_BITS(page_shift); 341 /* PTEs for each segment must start on a 4K bounday */ 342 pages_per_segment = max(pages_per_segment, 343 (1 << 12) / sizeof(unsigned long)); 344 345 ptab_size = segments * pages_per_segment * sizeof(unsigned long); 346 pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __func__, 347 iommu->nid, ptab_size, get_order(ptab_size)); 348 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size)); 349 BUG_ON(!page); 350 351 ptab = page_address(page); 352 memset(ptab, 0, ptab_size); 353 354 /* number of 4K pages needed for a page table */ 355 n_pte_pages = (pages_per_segment * sizeof(unsigned long)) >> 12; 356 357 pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n", 358 __func__, iommu->nid, iommu->stab, ptab, 359 n_pte_pages); 360 361 /* initialise the STEs */ 362 reg = IOSTE_V | ((n_pte_pages - 1) << 5); 363 364 switch (page_shift) { 365 case 12: reg |= IOSTE_PS_4K; break; 366 case 16: reg |= IOSTE_PS_64K; break; 367 case 20: reg |= IOSTE_PS_1M; break; 368 case 24: reg |= IOSTE_PS_16M; break; 369 default: BUG(); 370 } 371 372 gap_base = gap_base >> IO_SEGMENT_SHIFT; 373 gap_size = gap_size >> IO_SEGMENT_SHIFT; 374 375 pr_debug("Setting up IOMMU stab:\n"); 376 for (i = start_seg; i < (start_seg + segments); i++) { 377 if (i >= gap_base && i < (gap_base + gap_size)) { 378 pr_debug("\toverlap at %d, skipping\n", i); 379 continue; 380 } 381 iommu->stab[i] = reg | (__pa(ptab) + (n_pte_pages << 12) * 382 (i - start_seg)); 383 pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]); 384 } 385 386 return ptab; 387} 388 389static void cell_iommu_enable_hardware(struct cbe_iommu *iommu) 390{ 391 int ret; 392 unsigned long reg, xlate_base; 393 unsigned int virq; 394 395 if (cell_iommu_find_ioc(iommu->nid, &xlate_base)) 396 panic("%s: missing IOC register mappings for node %d\n", 397 __func__, iommu->nid); 398 399 iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size); 400 iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset; 401 402 /* ensure that the STEs have updated */ 403 mb(); 404 405 /* setup interrupts for the iommu. */ 406 reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); 407 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, 408 reg & ~IOC_IO_ExcpStat_V); 409 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask, 410 IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE); 411 412 virq = irq_create_mapping(NULL, 413 IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT)); 414 BUG_ON(virq == NO_IRQ); 415 416 ret = request_irq(virq, ioc_interrupt, 0, iommu->name, iommu); 417 BUG_ON(ret); 418 419 /* set the IOC segment table origin register (and turn on the iommu) */ 420 reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW; 421 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg); 422 in_be64(iommu->xlate_regs + IOC_IOST_Origin); 423 424 /* turn on IO translation */ 425 reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE; 426 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg); 427} 428 429static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, 430 unsigned long base, unsigned long size) 431{ 432 cell_iommu_setup_stab(iommu, base, size, 0, 0); 433 iommu->ptab = cell_iommu_alloc_ptab(iommu, base, size, 0, 0, 434 IOMMU_PAGE_SHIFT_4K); 435 cell_iommu_enable_hardware(iommu); 436} 437 438#if 0/* Unused for now */ 439static struct iommu_window *find_window(struct cbe_iommu *iommu, 440 unsigned long offset, unsigned long size) 441{ 442 struct iommu_window *window; 443 444 /* todo: check for overlapping (but not equal) windows) */ 445 446 list_for_each_entry(window, &(iommu->windows), list) { 447 if (window->offset == offset && window->size == size) 448 return window; 449 } 450 451 return NULL; 452} 453#endif 454 455static inline u32 cell_iommu_get_ioid(struct device_node *np) 456{ 457 const u32 *ioid; 458 459 ioid = of_get_property(np, "ioid", NULL); 460 if (ioid == NULL) { 461 printk(KERN_WARNING "iommu: missing ioid for %s using 0\n", 462 np->full_name); 463 return 0; 464 } 465 466 return *ioid; 467} 468 469static struct iommu_window * __init 470cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np, 471 unsigned long offset, unsigned long size, 472 unsigned long pte_offset) 473{ 474 struct iommu_window *window; 475 struct page *page; 476 u32 ioid; 477 478 ioid = cell_iommu_get_ioid(np); 479 480 window = kzalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid); 481 BUG_ON(window == NULL); 482 483 window->offset = offset; 484 window->size = size; 485 window->ioid = ioid; 486 window->iommu = iommu; 487 488 window->table.it_blocksize = 16; 489 window->table.it_base = (unsigned long)iommu->ptab; 490 window->table.it_index = iommu->nid; 491 window->table.it_page_shift = IOMMU_PAGE_SHIFT_4K; 492 window->table.it_offset = 493 (offset >> window->table.it_page_shift) + pte_offset; 494 window->table.it_size = size >> window->table.it_page_shift; 495 496 iommu_init_table(&window->table, iommu->nid); 497 498 pr_debug("\tioid %d\n", window->ioid); 499 pr_debug("\tblocksize %ld\n", window->table.it_blocksize); 500 pr_debug("\tbase 0x%016lx\n", window->table.it_base); 501 pr_debug("\toffset 0x%lx\n", window->table.it_offset); 502 pr_debug("\tsize %ld\n", window->table.it_size); 503 504 list_add(&window->list, &iommu->windows); 505 506 if (offset != 0) 507 return window; 508 509 /* We need to map and reserve the first IOMMU page since it's used 510 * by the spider workaround. In theory, we only need to do that when 511 * running on spider but it doesn't really matter. 512 * 513 * This code also assumes that we have a window that starts at 0, 514 * which is the case on all spider based blades. 515 */ 516 page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0); 517 BUG_ON(!page); 518 iommu->pad_page = page_address(page); 519 clear_page(iommu->pad_page); 520 521 __set_bit(0, window->table.it_map); 522 tce_build_cell(&window->table, window->table.it_offset, 1, 523 (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL); 524 525 return window; 526} 527 528static struct cbe_iommu *cell_iommu_for_node(int nid) 529{ 530 int i; 531 532 for (i = 0; i < cbe_nr_iommus; i++) 533 if (iommus[i].nid == nid) 534 return &iommus[i]; 535 return NULL; 536} 537 538static unsigned long cell_dma_direct_offset; 539 540static unsigned long dma_iommu_fixed_base; 541 542/* iommu_fixed_is_weak is set if booted with iommu_fixed=weak */ 543static int iommu_fixed_is_weak; 544 545static struct iommu_table *cell_get_iommu_table(struct device *dev) 546{ 547 struct iommu_window *window; 548 struct cbe_iommu *iommu; 549 550 /* Current implementation uses the first window available in that 551 * node's iommu. We -might- do something smarter later though it may 552 * never be necessary 553 */ 554 iommu = cell_iommu_for_node(dev_to_node(dev)); 555 if (iommu == NULL || list_empty(&iommu->windows)) { 556 dev_err(dev, "iommu: missing iommu for %s (node %d)\n", 557 of_node_full_name(dev->of_node), dev_to_node(dev)); 558 return NULL; 559 } 560 window = list_entry(iommu->windows.next, struct iommu_window, list); 561 562 return &window->table; 563} 564 565/* A coherent allocation implies strong ordering */ 566 567static void *dma_fixed_alloc_coherent(struct device *dev, size_t size, 568 dma_addr_t *dma_handle, gfp_t flag, 569 struct dma_attrs *attrs) 570{ 571 if (iommu_fixed_is_weak) 572 return iommu_alloc_coherent(dev, cell_get_iommu_table(dev), 573 size, dma_handle, 574 device_to_mask(dev), flag, 575 dev_to_node(dev)); 576 else 577 return dma_direct_ops.alloc(dev, size, dma_handle, flag, 578 attrs); 579} 580 581static void dma_fixed_free_coherent(struct device *dev, size_t size, 582 void *vaddr, dma_addr_t dma_handle, 583 struct dma_attrs *attrs) 584{ 585 if (iommu_fixed_is_weak) 586 iommu_free_coherent(cell_get_iommu_table(dev), size, vaddr, 587 dma_handle); 588 else 589 dma_direct_ops.free(dev, size, vaddr, dma_handle, attrs); 590} 591 592static dma_addr_t dma_fixed_map_page(struct device *dev, struct page *page, 593 unsigned long offset, size_t size, 594 enum dma_data_direction direction, 595 struct dma_attrs *attrs) 596{ 597 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 598 return dma_direct_ops.map_page(dev, page, offset, size, 599 direction, attrs); 600 else 601 return iommu_map_page(dev, cell_get_iommu_table(dev), page, 602 offset, size, device_to_mask(dev), 603 direction, attrs); 604} 605 606static void dma_fixed_unmap_page(struct device *dev, dma_addr_t dma_addr, 607 size_t size, enum dma_data_direction direction, 608 struct dma_attrs *attrs) 609{ 610 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 611 dma_direct_ops.unmap_page(dev, dma_addr, size, direction, 612 attrs); 613 else 614 iommu_unmap_page(cell_get_iommu_table(dev), dma_addr, size, 615 direction, attrs); 616} 617 618static int dma_fixed_map_sg(struct device *dev, struct scatterlist *sg, 619 int nents, enum dma_data_direction direction, 620 struct dma_attrs *attrs) 621{ 622 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 623 return dma_direct_ops.map_sg(dev, sg, nents, direction, attrs); 624 else 625 return ppc_iommu_map_sg(dev, cell_get_iommu_table(dev), sg, 626 nents, device_to_mask(dev), 627 direction, attrs); 628} 629 630static void dma_fixed_unmap_sg(struct device *dev, struct scatterlist *sg, 631 int nents, enum dma_data_direction direction, 632 struct dma_attrs *attrs) 633{ 634 if (iommu_fixed_is_weak == dma_get_attr(DMA_ATTR_WEAK_ORDERING, attrs)) 635 dma_direct_ops.unmap_sg(dev, sg, nents, direction, attrs); 636 else 637 ppc_iommu_unmap_sg(cell_get_iommu_table(dev), sg, nents, 638 direction, attrs); 639} 640 641static int dma_fixed_dma_supported(struct device *dev, u64 mask) 642{ 643 return mask == DMA_BIT_MASK(64); 644} 645 646static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask); 647 648struct dma_map_ops dma_iommu_fixed_ops = { 649 .alloc = dma_fixed_alloc_coherent, 650 .free = dma_fixed_free_coherent, 651 .map_sg = dma_fixed_map_sg, 652 .unmap_sg = dma_fixed_unmap_sg, 653 .dma_supported = dma_fixed_dma_supported, 654 .set_dma_mask = dma_set_mask_and_switch, 655 .map_page = dma_fixed_map_page, 656 .unmap_page = dma_fixed_unmap_page, 657}; 658 659static void cell_dma_dev_setup_fixed(struct device *dev); 660 661static void cell_dma_dev_setup(struct device *dev) 662{ 663 /* Order is important here, these are not mutually exclusive */ 664 if (get_dma_ops(dev) == &dma_iommu_fixed_ops) 665 cell_dma_dev_setup_fixed(dev); 666 else if (get_pci_dma_ops() == &dma_iommu_ops) 667 set_iommu_table_base(dev, cell_get_iommu_table(dev)); 668 else if (get_pci_dma_ops() == &dma_direct_ops) 669 set_dma_offset(dev, cell_dma_direct_offset); 670 else 671 BUG(); 672} 673 674static void cell_pci_dma_dev_setup(struct pci_dev *dev) 675{ 676 cell_dma_dev_setup(&dev->dev); 677} 678 679static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action, 680 void *data) 681{ 682 struct device *dev = data; 683 684 /* We are only intereted in device addition */ 685 if (action != BUS_NOTIFY_ADD_DEVICE) 686 return 0; 687 688 /* We use the PCI DMA ops */ 689 dev->archdata.dma_ops = get_pci_dma_ops(); 690 691 cell_dma_dev_setup(dev); 692 693 return 0; 694} 695 696static struct notifier_block cell_of_bus_notifier = { 697 .notifier_call = cell_of_bus_notify 698}; 699 700static int __init cell_iommu_get_window(struct device_node *np, 701 unsigned long *base, 702 unsigned long *size) 703{ 704 const __be32 *dma_window; 705 unsigned long index; 706 707 /* Use ibm,dma-window if available, else, hard code ! */ 708 dma_window = of_get_property(np, "ibm,dma-window", NULL); 709 if (dma_window == NULL) { 710 *base = 0; 711 *size = 0x80000000u; 712 return -ENODEV; 713 } 714 715 of_parse_dma_window(np, dma_window, &index, base, size); 716 return 0; 717} 718 719static struct cbe_iommu * __init cell_iommu_alloc(struct device_node *np) 720{ 721 struct cbe_iommu *iommu; 722 int nid, i; 723 724 /* Get node ID */ 725 nid = of_node_to_nid(np); 726 if (nid < 0) { 727 printk(KERN_ERR "iommu: failed to get node for %s\n", 728 np->full_name); 729 return NULL; 730 } 731 pr_debug("iommu: setting up iommu for node %d (%s)\n", 732 nid, np->full_name); 733 734 /* XXX todo: If we can have multiple windows on the same IOMMU, which 735 * isn't the case today, we probably want here to check whether the 736 * iommu for that node is already setup. 737 * However, there might be issue with getting the size right so let's 738 * ignore that for now. We might want to completely get rid of the 739 * multiple window support since the cell iommu supports per-page ioids 740 */ 741 742 if (cbe_nr_iommus >= NR_IOMMUS) { 743 printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n", 744 np->full_name); 745 return NULL; 746 } 747 748 /* Init base fields */ 749 i = cbe_nr_iommus++; 750 iommu = &iommus[i]; 751 iommu->stab = NULL; 752 iommu->nid = nid; 753 snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i); 754 INIT_LIST_HEAD(&iommu->windows); 755 756 return iommu; 757} 758 759static void __init cell_iommu_init_one(struct device_node *np, 760 unsigned long offset) 761{ 762 struct cbe_iommu *iommu; 763 unsigned long base, size; 764 765 iommu = cell_iommu_alloc(np); 766 if (!iommu) 767 return; 768 769 /* Obtain a window for it */ 770 cell_iommu_get_window(np, &base, &size); 771 772 pr_debug("\ttranslating window 0x%lx...0x%lx\n", 773 base, base + size - 1); 774 775 /* Initialize the hardware */ 776 cell_iommu_setup_hardware(iommu, base, size); 777 778 /* Setup the iommu_table */ 779 cell_iommu_setup_window(iommu, np, base, size, 780 offset >> IOMMU_PAGE_SHIFT_4K); 781} 782 783static void __init cell_disable_iommus(void) 784{ 785 int node; 786 unsigned long base, val; 787 void __iomem *xregs, *cregs; 788 789 /* Make sure IOC translation is disabled on all nodes */ 790 for_each_online_node(node) { 791 if (cell_iommu_find_ioc(node, &base)) 792 continue; 793 xregs = ioremap(base, IOC_Reg_Size); 794 if (xregs == NULL) 795 continue; 796 cregs = xregs + IOC_IOCmd_Offset; 797 798 pr_debug("iommu: cleaning up iommu on node %d\n", node); 799 800 out_be64(xregs + IOC_IOST_Origin, 0); 801 (void)in_be64(xregs + IOC_IOST_Origin); 802 val = in_be64(cregs + IOC_IOCmd_Cfg); 803 val &= ~IOC_IOCmd_Cfg_TE; 804 out_be64(cregs + IOC_IOCmd_Cfg, val); 805 (void)in_be64(cregs + IOC_IOCmd_Cfg); 806 807 iounmap(xregs); 808 } 809} 810 811static int __init cell_iommu_init_disabled(void) 812{ 813 struct device_node *np = NULL; 814 unsigned long base = 0, size; 815 816 /* When no iommu is present, we use direct DMA ops */ 817 set_pci_dma_ops(&dma_direct_ops); 818 819 /* First make sure all IOC translation is turned off */ 820 cell_disable_iommus(); 821 822 /* If we have no Axon, we set up the spider DMA magic offset */ 823 if (of_find_node_by_name(NULL, "axon") == NULL) 824 cell_dma_direct_offset = SPIDER_DMA_OFFSET; 825 826 /* Now we need to check to see where the memory is mapped 827 * in PCI space. We assume that all busses use the same dma 828 * window which is always the case so far on Cell, thus we 829 * pick up the first pci-internal node we can find and check 830 * the DMA window from there. 831 */ 832 for_each_node_by_name(np, "axon") { 833 if (np->parent == NULL || np->parent->parent != NULL) 834 continue; 835 if (cell_iommu_get_window(np, &base, &size) == 0) 836 break; 837 } 838 if (np == NULL) { 839 for_each_node_by_name(np, "pci-internal") { 840 if (np->parent == NULL || np->parent->parent != NULL) 841 continue; 842 if (cell_iommu_get_window(np, &base, &size) == 0) 843 break; 844 } 845 } 846 of_node_put(np); 847 848 /* If we found a DMA window, we check if it's big enough to enclose 849 * all of physical memory. If not, we force enable IOMMU 850 */ 851 if (np && size < memblock_end_of_DRAM()) { 852 printk(KERN_WARNING "iommu: force-enabled, dma window" 853 " (%ldMB) smaller than total memory (%lldMB)\n", 854 size >> 20, memblock_end_of_DRAM() >> 20); 855 return -ENODEV; 856 } 857 858 cell_dma_direct_offset += base; 859 860 if (cell_dma_direct_offset != 0) 861 cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup; 862 863 printk("iommu: disabled, direct DMA offset is 0x%lx\n", 864 cell_dma_direct_offset); 865 866 return 0; 867} 868 869/* 870 * Fixed IOMMU mapping support 871 * 872 * This code adds support for setting up a fixed IOMMU mapping on certain 873 * cell machines. For 64-bit devices this avoids the performance overhead of 874 * mapping and unmapping pages at runtime. 32-bit devices are unable to use 875 * the fixed mapping. 876 * 877 * The fixed mapping is established at boot, and maps all of physical memory 878 * 1:1 into device space at some offset. On machines with < 30 GB of memory 879 * we setup the fixed mapping immediately above the normal IOMMU window. 880 * 881 * For example a machine with 4GB of memory would end up with the normal 882 * IOMMU window from 0-2GB and the fixed mapping window from 2GB to 6GB. In 883 * this case a 64-bit device wishing to DMA to 1GB would be told to DMA to 884 * 3GB, plus any offset required by firmware. The firmware offset is encoded 885 * in the "dma-ranges" property. 886 * 887 * On machines with 30GB or more of memory, we are unable to place the fixed 888 * mapping above the normal IOMMU window as we would run out of address space. 889 * Instead we move the normal IOMMU window to coincide with the hash page 890 * table, this region does not need to be part of the fixed mapping as no 891 * device should ever be DMA'ing to it. We then setup the fixed mapping 892 * from 0 to 32GB. 893 */ 894 895static u64 cell_iommu_get_fixed_address(struct device *dev) 896{ 897 u64 cpu_addr, size, best_size, dev_addr = OF_BAD_ADDR; 898 struct device_node *np; 899 const u32 *ranges = NULL; 900 int i, len, best, naddr, nsize, pna, range_size; 901 902 np = of_node_get(dev->of_node); 903 while (1) { 904 naddr = of_n_addr_cells(np); 905 nsize = of_n_size_cells(np); 906 np = of_get_next_parent(np); 907 if (!np) 908 break; 909 910 ranges = of_get_property(np, "dma-ranges", &len); 911 912 /* Ignore empty ranges, they imply no translation required */ 913 if (ranges && len > 0) 914 break; 915 } 916 917 if (!ranges) { 918 dev_dbg(dev, "iommu: no dma-ranges found\n"); 919 goto out; 920 } 921 922 len /= sizeof(u32); 923 924 pna = of_n_addr_cells(np); 925 range_size = naddr + nsize + pna; 926 927 /* dma-ranges format: 928 * child addr : naddr cells 929 * parent addr : pna cells 930 * size : nsize cells 931 */ 932 for (i = 0, best = -1, best_size = 0; i < len; i += range_size) { 933 cpu_addr = of_translate_dma_address(np, ranges + i + naddr); 934 size = of_read_number(ranges + i + naddr + pna, nsize); 935 936 if (cpu_addr == 0 && size > best_size) { 937 best = i; 938 best_size = size; 939 } 940 } 941 942 if (best >= 0) { 943 dev_addr = of_read_number(ranges + best, naddr); 944 } else 945 dev_dbg(dev, "iommu: no suitable range found!\n"); 946 947out: 948 of_node_put(np); 949 950 return dev_addr; 951} 952 953static int dma_set_mask_and_switch(struct device *dev, u64 dma_mask) 954{ 955 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 956 return -EIO; 957 958 if (dma_mask == DMA_BIT_MASK(64) && 959 cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR) 960 { 961 dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n"); 962 set_dma_ops(dev, &dma_iommu_fixed_ops); 963 } else { 964 dev_dbg(dev, "iommu: not 64-bit, using default ops\n"); 965 set_dma_ops(dev, get_pci_dma_ops()); 966 } 967 968 cell_dma_dev_setup(dev); 969 970 *dev->dma_mask = dma_mask; 971 972 return 0; 973} 974 975static void cell_dma_dev_setup_fixed(struct device *dev) 976{ 977 u64 addr; 978 979 addr = cell_iommu_get_fixed_address(dev) + dma_iommu_fixed_base; 980 set_dma_offset(dev, addr); 981 982 dev_dbg(dev, "iommu: fixed addr = %llx\n", addr); 983} 984 985static void insert_16M_pte(unsigned long addr, unsigned long *ptab, 986 unsigned long base_pte) 987{ 988 unsigned long segment, offset; 989 990 segment = addr >> IO_SEGMENT_SHIFT; 991 offset = (addr >> 24) - (segment << IO_PAGENO_BITS(24)); 992 ptab = ptab + (segment * (1 << 12) / sizeof(unsigned long)); 993 994 pr_debug("iommu: addr %lx ptab %p segment %lx offset %lx\n", 995 addr, ptab, segment, offset); 996 997 ptab[offset] = base_pte | (__pa(addr) & CBE_IOPTE_RPN_Mask); 998} 999 1000static void cell_iommu_setup_fixed_ptab(struct cbe_iommu *iommu, 1001 struct device_node *np, unsigned long dbase, unsigned long dsize, 1002 unsigned long fbase, unsigned long fsize) 1003{ 1004 unsigned long base_pte, uaddr, ioaddr, *ptab; 1005 1006 ptab = cell_iommu_alloc_ptab(iommu, fbase, fsize, dbase, dsize, 24); 1007 1008 dma_iommu_fixed_base = fbase; 1009 1010 pr_debug("iommu: mapping 0x%lx pages from 0x%lx\n", fsize, fbase); 1011 1012 base_pte = CBE_IOPTE_PP_W | CBE_IOPTE_PP_R | CBE_IOPTE_M | 1013 (cell_iommu_get_ioid(np) & CBE_IOPTE_IOID_Mask); 1014 1015 if (iommu_fixed_is_weak) 1016 pr_info("IOMMU: Using weak ordering for fixed mapping\n"); 1017 else { 1018 pr_info("IOMMU: Using strong ordering for fixed mapping\n"); 1019 base_pte |= CBE_IOPTE_SO_RW; 1020 } 1021 1022 for (uaddr = 0; uaddr < fsize; uaddr += (1 << 24)) { 1023 /* Don't touch the dynamic region */ 1024 ioaddr = uaddr + fbase; 1025 if (ioaddr >= dbase && ioaddr < (dbase + dsize)) { 1026 pr_debug("iommu: fixed/dynamic overlap, skipping\n"); 1027 continue; 1028 } 1029 1030 insert_16M_pte(uaddr, ptab, base_pte); 1031 } 1032 1033 mb(); 1034} 1035 1036static int __init cell_iommu_fixed_mapping_init(void) 1037{ 1038 unsigned long dbase, dsize, fbase, fsize, hbase, hend; 1039 struct cbe_iommu *iommu; 1040 struct device_node *np; 1041 1042 /* The fixed mapping is only supported on axon machines */ 1043 np = of_find_node_by_name(NULL, "axon"); 1044 of_node_put(np); 1045 1046 if (!np) { 1047 pr_debug("iommu: fixed mapping disabled, no axons found\n"); 1048 return -1; 1049 } 1050 1051 /* We must have dma-ranges properties for fixed mapping to work */ 1052 np = of_find_node_with_property(NULL, "dma-ranges"); 1053 of_node_put(np); 1054 1055 if (!np) { 1056 pr_debug("iommu: no dma-ranges found, no fixed mapping\n"); 1057 return -1; 1058 } 1059 1060 /* The default setup is to have the fixed mapping sit after the 1061 * dynamic region, so find the top of the largest IOMMU window 1062 * on any axon, then add the size of RAM and that's our max value. 1063 * If that is > 32GB we have to do other shennanigans. 1064 */ 1065 fbase = 0; 1066 for_each_node_by_name(np, "axon") { 1067 cell_iommu_get_window(np, &dbase, &dsize); 1068 fbase = max(fbase, dbase + dsize); 1069 } 1070 1071 fbase = _ALIGN_UP(fbase, 1 << IO_SEGMENT_SHIFT); 1072 fsize = memblock_phys_mem_size(); 1073 1074 if ((fbase + fsize) <= 0x800000000ul) 1075 hbase = 0; /* use the device tree window */ 1076 else { 1077 /* If we're over 32 GB we need to cheat. We can't map all of 1078 * RAM with the fixed mapping, and also fit the dynamic 1079 * region. So try to place the dynamic region where the hash 1080 * table sits, drivers never need to DMA to it, we don't 1081 * need a fixed mapping for that area. 1082 */ 1083 if (!htab_address) { 1084 pr_debug("iommu: htab is NULL, on LPAR? Huh?\n"); 1085 return -1; 1086 } 1087 hbase = __pa(htab_address); 1088 hend = hbase + htab_size_bytes; 1089 1090 /* The window must start and end on a segment boundary */ 1091 if ((hbase != _ALIGN_UP(hbase, 1 << IO_SEGMENT_SHIFT)) || 1092 (hend != _ALIGN_UP(hend, 1 << IO_SEGMENT_SHIFT))) { 1093 pr_debug("iommu: hash window not segment aligned\n"); 1094 return -1; 1095 } 1096 1097 /* Check the hash window fits inside the real DMA window */ 1098 for_each_node_by_name(np, "axon") { 1099 cell_iommu_get_window(np, &dbase, &dsize); 1100 1101 if (hbase < dbase || (hend > (dbase + dsize))) { 1102 pr_debug("iommu: hash window doesn't fit in" 1103 "real DMA window\n"); 1104 return -1; 1105 } 1106 } 1107 1108 fbase = 0; 1109 } 1110 1111 /* Setup the dynamic regions */ 1112 for_each_node_by_name(np, "axon") { 1113 iommu = cell_iommu_alloc(np); 1114 BUG_ON(!iommu); 1115 1116 if (hbase == 0) 1117 cell_iommu_get_window(np, &dbase, &dsize); 1118 else { 1119 dbase = hbase; 1120 dsize = htab_size_bytes; 1121 } 1122 1123 printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx " 1124 "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase, 1125 dbase + dsize, fbase, fbase + fsize); 1126 1127 cell_iommu_setup_stab(iommu, dbase, dsize, fbase, fsize); 1128 iommu->ptab = cell_iommu_alloc_ptab(iommu, dbase, dsize, 0, 0, 1129 IOMMU_PAGE_SHIFT_4K); 1130 cell_iommu_setup_fixed_ptab(iommu, np, dbase, dsize, 1131 fbase, fsize); 1132 cell_iommu_enable_hardware(iommu); 1133 cell_iommu_setup_window(iommu, np, dbase, dsize, 0); 1134 } 1135 1136 dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch; 1137 set_pci_dma_ops(&dma_iommu_ops); 1138 1139 return 0; 1140} 1141 1142static int iommu_fixed_disabled; 1143 1144static int __init setup_iommu_fixed(char *str) 1145{ 1146 struct device_node *pciep; 1147 1148 if (strcmp(str, "off") == 0) 1149 iommu_fixed_disabled = 1; 1150 1151 /* If we can find a pcie-endpoint in the device tree assume that 1152 * we're on a triblade or a CAB so by default the fixed mapping 1153 * should be set to be weakly ordered; but only if the boot 1154 * option WASN'T set for strong ordering 1155 */ 1156 pciep = of_find_node_by_type(NULL, "pcie-endpoint"); 1157 1158 if (strcmp(str, "weak") == 0 || (pciep && strcmp(str, "strong") != 0)) 1159 iommu_fixed_is_weak = 1; 1160 1161 of_node_put(pciep); 1162 1163 return 1; 1164} 1165__setup("iommu_fixed=", setup_iommu_fixed); 1166 1167static u64 cell_dma_get_required_mask(struct device *dev) 1168{ 1169 struct dma_map_ops *dma_ops; 1170 1171 if (!dev->dma_mask) 1172 return 0; 1173 1174 if (!iommu_fixed_disabled && 1175 cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR) 1176 return DMA_BIT_MASK(64); 1177 1178 dma_ops = get_dma_ops(dev); 1179 if (dma_ops->get_required_mask) 1180 return dma_ops->get_required_mask(dev); 1181 1182 WARN_ONCE(1, "no get_required_mask in %p ops", dma_ops); 1183 1184 return DMA_BIT_MASK(64); 1185} 1186 1187static int __init cell_iommu_init(void) 1188{ 1189 struct device_node *np; 1190 1191 /* If IOMMU is disabled or we have little enough RAM to not need 1192 * to enable it, we setup a direct mapping. 1193 * 1194 * Note: should we make sure we have the IOMMU actually disabled ? 1195 */ 1196 if (iommu_is_off || 1197 (!iommu_force_on && memblock_end_of_DRAM() <= 0x80000000ull)) 1198 if (cell_iommu_init_disabled() == 0) 1199 goto bail; 1200 1201 /* Setup various callbacks */ 1202 cell_pci_controller_ops.dma_dev_setup = cell_pci_dma_dev_setup; 1203 ppc_md.dma_get_required_mask = cell_dma_get_required_mask; 1204 ppc_md.tce_build = tce_build_cell; 1205 ppc_md.tce_free = tce_free_cell; 1206 1207 if (!iommu_fixed_disabled && cell_iommu_fixed_mapping_init() == 0) 1208 goto bail; 1209 1210 /* Create an iommu for each /axon node. */ 1211 for_each_node_by_name(np, "axon") { 1212 if (np->parent == NULL || np->parent->parent != NULL) 1213 continue; 1214 cell_iommu_init_one(np, 0); 1215 } 1216 1217 /* Create an iommu for each toplevel /pci-internal node for 1218 * old hardware/firmware 1219 */ 1220 for_each_node_by_name(np, "pci-internal") { 1221 if (np->parent == NULL || np->parent->parent != NULL) 1222 continue; 1223 cell_iommu_init_one(np, SPIDER_DMA_OFFSET); 1224 } 1225 1226 /* Setup default PCI iommu ops */ 1227 set_pci_dma_ops(&dma_iommu_ops); 1228 1229 bail: 1230 /* Register callbacks on OF platform device addition/removal 1231 * to handle linking them to the right DMA operations 1232 */ 1233 bus_register_notifier(&platform_bus_type, &cell_of_bus_notifier); 1234 1235 return 0; 1236} 1237machine_arch_initcall(cell, cell_iommu_init); 1238