1/*
2 * arch/powerpc/platforms/embedded6xx/hlwd-pic.c
3 *
4 * Nintendo Wii "Hollywood" interrupt controller support.
5 * Copyright (C) 2009 The GameCube Linux Team
6 * Copyright (C) 2009 Albert Herranz
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 */
14#define DRV_MODULE_NAME "hlwd-pic"
15#define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt
16
17#include <linux/kernel.h>
18#include <linux/irq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <asm/io.h>
23
24#include "hlwd-pic.h"
25
26#define HLWD_NR_IRQS	32
27
28/*
29 * Each interrupt has a corresponding bit in both
30 * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers.
31 *
32 * Enabling/disabling an interrupt line involves asserting/clearing
33 * the corresponding bit in IMR. ACK'ing a request simply involves
34 * asserting the corresponding bit in ICR.
35 */
36#define HW_BROADWAY_ICR		0x00
37#define HW_BROADWAY_IMR		0x04
38
39
40/*
41 * IRQ chip hooks.
42 *
43 */
44
45static void hlwd_pic_mask_and_ack(struct irq_data *d)
46{
47	int irq = irqd_to_hwirq(d);
48	void __iomem *io_base = irq_data_get_irq_chip_data(d);
49	u32 mask = 1 << irq;
50
51	clrbits32(io_base + HW_BROADWAY_IMR, mask);
52	out_be32(io_base + HW_BROADWAY_ICR, mask);
53}
54
55static void hlwd_pic_ack(struct irq_data *d)
56{
57	int irq = irqd_to_hwirq(d);
58	void __iomem *io_base = irq_data_get_irq_chip_data(d);
59
60	out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
61}
62
63static void hlwd_pic_mask(struct irq_data *d)
64{
65	int irq = irqd_to_hwirq(d);
66	void __iomem *io_base = irq_data_get_irq_chip_data(d);
67
68	clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
69}
70
71static void hlwd_pic_unmask(struct irq_data *d)
72{
73	int irq = irqd_to_hwirq(d);
74	void __iomem *io_base = irq_data_get_irq_chip_data(d);
75
76	setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
77}
78
79
80static struct irq_chip hlwd_pic = {
81	.name		= "hlwd-pic",
82	.irq_ack	= hlwd_pic_ack,
83	.irq_mask_ack	= hlwd_pic_mask_and_ack,
84	.irq_mask	= hlwd_pic_mask,
85	.irq_unmask	= hlwd_pic_unmask,
86};
87
88/*
89 * IRQ host hooks.
90 *
91 */
92
93static struct irq_domain *hlwd_irq_host;
94
95static int hlwd_pic_map(struct irq_domain *h, unsigned int virq,
96			   irq_hw_number_t hwirq)
97{
98	irq_set_chip_data(virq, h->host_data);
99	irq_set_status_flags(virq, IRQ_LEVEL);
100	irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
101	return 0;
102}
103
104static const struct irq_domain_ops hlwd_irq_domain_ops = {
105	.map = hlwd_pic_map,
106};
107
108static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
109{
110	void __iomem *io_base = h->host_data;
111	int irq;
112	u32 irq_status;
113
114	irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
115		     in_be32(io_base + HW_BROADWAY_IMR);
116	if (irq_status == 0)
117		return NO_IRQ;	/* no more IRQs pending */
118
119	irq = __ffs(irq_status);
120	return irq_linear_revmap(h, irq);
121}
122
123static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
124				      struct irq_desc *desc)
125{
126	struct irq_chip *chip = irq_desc_get_chip(desc);
127	struct irq_domain *irq_domain = irq_get_handler_data(cascade_virq);
128	unsigned int virq;
129
130	raw_spin_lock(&desc->lock);
131	chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
132	raw_spin_unlock(&desc->lock);
133
134	virq = __hlwd_pic_get_irq(irq_domain);
135	if (virq != NO_IRQ)
136		generic_handle_irq(virq);
137	else
138		pr_err("spurious interrupt!\n");
139
140	raw_spin_lock(&desc->lock);
141	chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
142	if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
143		chip->irq_unmask(&desc->irq_data);
144	raw_spin_unlock(&desc->lock);
145}
146
147/*
148 * Platform hooks.
149 *
150 */
151
152static void __hlwd_quiesce(void __iomem *io_base)
153{
154	/* mask and ack all IRQs */
155	out_be32(io_base + HW_BROADWAY_IMR, 0);
156	out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
157}
158
159struct irq_domain *hlwd_pic_init(struct device_node *np)
160{
161	struct irq_domain *irq_domain;
162	struct resource res;
163	void __iomem *io_base;
164	int retval;
165
166	retval = of_address_to_resource(np, 0, &res);
167	if (retval) {
168		pr_err("no io memory range found\n");
169		return NULL;
170	}
171	io_base = ioremap(res.start, resource_size(&res));
172	if (!io_base) {
173		pr_err("ioremap failed\n");
174		return NULL;
175	}
176
177	pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
178
179	__hlwd_quiesce(io_base);
180
181	irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS,
182					   &hlwd_irq_domain_ops, io_base);
183	if (!irq_domain) {
184		pr_err("failed to allocate irq_domain\n");
185		iounmap(io_base);
186		return NULL;
187	}
188
189	return irq_domain;
190}
191
192unsigned int hlwd_pic_get_irq(void)
193{
194	return __hlwd_pic_get_irq(hlwd_irq_host);
195}
196
197/*
198 * Probe function.
199 *
200 */
201
202void hlwd_pic_probe(void)
203{
204	struct irq_domain *host;
205	struct device_node *np;
206	const u32 *interrupts;
207	int cascade_virq;
208
209	for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") {
210		interrupts = of_get_property(np, "interrupts", NULL);
211		if (interrupts) {
212			host = hlwd_pic_init(np);
213			BUG_ON(!host);
214			cascade_virq = irq_of_parse_and_map(np, 0);
215			irq_set_handler_data(cascade_virq, host);
216			irq_set_chained_handler(cascade_virq,
217						hlwd_pic_irq_cascade);
218			hlwd_irq_host = host;
219			break;
220		}
221	}
222}
223
224/**
225 * hlwd_quiesce() - quiesce hollywood irq controller
226 *
227 * Mask and ack all interrupt sources.
228 *
229 */
230void hlwd_quiesce(void)
231{
232	void __iomem *io_base = hlwd_irq_host->host_data;
233
234	__hlwd_quiesce(io_base);
235}
236
237