1/* 2 * Support PCI/PCIe on PowerNV platforms 3 * 4 * Currently supports only P5IOC2 5 * 6 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/pci.h> 16#include <linux/delay.h> 17#include <linux/string.h> 18#include <linux/init.h> 19#include <linux/irq.h> 20#include <linux/io.h> 21#include <linux/msi.h> 22#include <linux/iommu.h> 23 24#include <asm/sections.h> 25#include <asm/io.h> 26#include <asm/prom.h> 27#include <asm/pci-bridge.h> 28#include <asm/machdep.h> 29#include <asm/msi_bitmap.h> 30#include <asm/ppc-pci.h> 31#include <asm/opal.h> 32#include <asm/iommu.h> 33#include <asm/tce.h> 34#include <asm/firmware.h> 35#include <asm/eeh_event.h> 36#include <asm/eeh.h> 37 38#include "powernv.h" 39#include "pci.h" 40 41/* Delay in usec */ 42#define PCI_RESET_DELAY_US 3000000 43 44#define cfg_dbg(fmt...) do { } while(0) 45//#define cfg_dbg(fmt...) printk(fmt) 46 47#ifdef CONFIG_PCI_MSI 48static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 49{ 50 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 51 struct pnv_phb *phb = hose->private_data; 52 struct msi_desc *entry; 53 struct msi_msg msg; 54 int hwirq; 55 unsigned int virq; 56 int rc; 57 58 if (WARN_ON(!phb) || !phb->msi_bmp.bitmap) 59 return -ENODEV; 60 61 if (pdev->no_64bit_msi && !phb->msi32_support) 62 return -ENODEV; 63 64 list_for_each_entry(entry, &pdev->msi_list, list) { 65 if (!entry->msi_attrib.is_64 && !phb->msi32_support) { 66 pr_warn("%s: Supports only 64-bit MSIs\n", 67 pci_name(pdev)); 68 return -ENXIO; 69 } 70 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1); 71 if (hwirq < 0) { 72 pr_warn("%s: Failed to find a free MSI\n", 73 pci_name(pdev)); 74 return -ENOSPC; 75 } 76 virq = irq_create_mapping(NULL, phb->msi_base + hwirq); 77 if (virq == NO_IRQ) { 78 pr_warn("%s: Failed to map MSI to linux irq\n", 79 pci_name(pdev)); 80 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 81 return -ENOMEM; 82 } 83 rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq, 84 virq, entry->msi_attrib.is_64, &msg); 85 if (rc) { 86 pr_warn("%s: Failed to setup MSI\n", pci_name(pdev)); 87 irq_dispose_mapping(virq); 88 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1); 89 return rc; 90 } 91 irq_set_msi_desc(virq, entry); 92 pci_write_msi_msg(virq, &msg); 93 } 94 return 0; 95} 96 97static void pnv_teardown_msi_irqs(struct pci_dev *pdev) 98{ 99 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 100 struct pnv_phb *phb = hose->private_data; 101 struct msi_desc *entry; 102 irq_hw_number_t hwirq; 103 104 if (WARN_ON(!phb)) 105 return; 106 107 list_for_each_entry(entry, &pdev->msi_list, list) { 108 if (entry->irq == NO_IRQ) 109 continue; 110 hwirq = virq_to_hw(entry->irq); 111 irq_set_msi_desc(entry->irq, NULL); 112 irq_dispose_mapping(entry->irq); 113 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, 1); 114 } 115} 116#endif /* CONFIG_PCI_MSI */ 117 118static void pnv_pci_dump_p7ioc_diag_data(struct pci_controller *hose, 119 struct OpalIoPhbErrorCommon *common) 120{ 121 struct OpalIoP7IOCPhbErrorData *data; 122 int i; 123 124 data = (struct OpalIoP7IOCPhbErrorData *)common; 125 pr_info("P7IOC PHB#%d Diag-data (Version: %d)\n", 126 hose->global_number, be32_to_cpu(common->version)); 127 128 if (data->brdgCtl) 129 pr_info("brdgCtl: %08x\n", 130 be32_to_cpu(data->brdgCtl)); 131 if (data->portStatusReg || data->rootCmplxStatus || 132 data->busAgentStatus) 133 pr_info("UtlSts: %08x %08x %08x\n", 134 be32_to_cpu(data->portStatusReg), 135 be32_to_cpu(data->rootCmplxStatus), 136 be32_to_cpu(data->busAgentStatus)); 137 if (data->deviceStatus || data->slotStatus || 138 data->linkStatus || data->devCmdStatus || 139 data->devSecStatus) 140 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 141 be32_to_cpu(data->deviceStatus), 142 be32_to_cpu(data->slotStatus), 143 be32_to_cpu(data->linkStatus), 144 be32_to_cpu(data->devCmdStatus), 145 be32_to_cpu(data->devSecStatus)); 146 if (data->rootErrorStatus || data->uncorrErrorStatus || 147 data->corrErrorStatus) 148 pr_info("RootErrSts: %08x %08x %08x\n", 149 be32_to_cpu(data->rootErrorStatus), 150 be32_to_cpu(data->uncorrErrorStatus), 151 be32_to_cpu(data->corrErrorStatus)); 152 if (data->tlpHdr1 || data->tlpHdr2 || 153 data->tlpHdr3 || data->tlpHdr4) 154 pr_info("RootErrLog: %08x %08x %08x %08x\n", 155 be32_to_cpu(data->tlpHdr1), 156 be32_to_cpu(data->tlpHdr2), 157 be32_to_cpu(data->tlpHdr3), 158 be32_to_cpu(data->tlpHdr4)); 159 if (data->sourceId || data->errorClass || 160 data->correlator) 161 pr_info("RootErrLog1: %08x %016llx %016llx\n", 162 be32_to_cpu(data->sourceId), 163 be64_to_cpu(data->errorClass), 164 be64_to_cpu(data->correlator)); 165 if (data->p7iocPlssr || data->p7iocCsr) 166 pr_info("PhbSts: %016llx %016llx\n", 167 be64_to_cpu(data->p7iocPlssr), 168 be64_to_cpu(data->p7iocCsr)); 169 if (data->lemFir) 170 pr_info("Lem: %016llx %016llx %016llx\n", 171 be64_to_cpu(data->lemFir), 172 be64_to_cpu(data->lemErrorMask), 173 be64_to_cpu(data->lemWOF)); 174 if (data->phbErrorStatus) 175 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 176 be64_to_cpu(data->phbErrorStatus), 177 be64_to_cpu(data->phbFirstErrorStatus), 178 be64_to_cpu(data->phbErrorLog0), 179 be64_to_cpu(data->phbErrorLog1)); 180 if (data->mmioErrorStatus) 181 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 182 be64_to_cpu(data->mmioErrorStatus), 183 be64_to_cpu(data->mmioFirstErrorStatus), 184 be64_to_cpu(data->mmioErrorLog0), 185 be64_to_cpu(data->mmioErrorLog1)); 186 if (data->dma0ErrorStatus) 187 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 188 be64_to_cpu(data->dma0ErrorStatus), 189 be64_to_cpu(data->dma0FirstErrorStatus), 190 be64_to_cpu(data->dma0ErrorLog0), 191 be64_to_cpu(data->dma0ErrorLog1)); 192 if (data->dma1ErrorStatus) 193 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 194 be64_to_cpu(data->dma1ErrorStatus), 195 be64_to_cpu(data->dma1FirstErrorStatus), 196 be64_to_cpu(data->dma1ErrorLog0), 197 be64_to_cpu(data->dma1ErrorLog1)); 198 199 for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) { 200 if ((data->pestA[i] >> 63) == 0 && 201 (data->pestB[i] >> 63) == 0) 202 continue; 203 204 pr_info("PE[%3d] A/B: %016llx %016llx\n", 205 i, be64_to_cpu(data->pestA[i]), 206 be64_to_cpu(data->pestB[i])); 207 } 208} 209 210static void pnv_pci_dump_phb3_diag_data(struct pci_controller *hose, 211 struct OpalIoPhbErrorCommon *common) 212{ 213 struct OpalIoPhb3ErrorData *data; 214 int i; 215 216 data = (struct OpalIoPhb3ErrorData*)common; 217 pr_info("PHB3 PHB#%d Diag-data (Version: %d)\n", 218 hose->global_number, be32_to_cpu(common->version)); 219 if (data->brdgCtl) 220 pr_info("brdgCtl: %08x\n", 221 be32_to_cpu(data->brdgCtl)); 222 if (data->portStatusReg || data->rootCmplxStatus || 223 data->busAgentStatus) 224 pr_info("UtlSts: %08x %08x %08x\n", 225 be32_to_cpu(data->portStatusReg), 226 be32_to_cpu(data->rootCmplxStatus), 227 be32_to_cpu(data->busAgentStatus)); 228 if (data->deviceStatus || data->slotStatus || 229 data->linkStatus || data->devCmdStatus || 230 data->devSecStatus) 231 pr_info("RootSts: %08x %08x %08x %08x %08x\n", 232 be32_to_cpu(data->deviceStatus), 233 be32_to_cpu(data->slotStatus), 234 be32_to_cpu(data->linkStatus), 235 be32_to_cpu(data->devCmdStatus), 236 be32_to_cpu(data->devSecStatus)); 237 if (data->rootErrorStatus || data->uncorrErrorStatus || 238 data->corrErrorStatus) 239 pr_info("RootErrSts: %08x %08x %08x\n", 240 be32_to_cpu(data->rootErrorStatus), 241 be32_to_cpu(data->uncorrErrorStatus), 242 be32_to_cpu(data->corrErrorStatus)); 243 if (data->tlpHdr1 || data->tlpHdr2 || 244 data->tlpHdr3 || data->tlpHdr4) 245 pr_info("RootErrLog: %08x %08x %08x %08x\n", 246 be32_to_cpu(data->tlpHdr1), 247 be32_to_cpu(data->tlpHdr2), 248 be32_to_cpu(data->tlpHdr3), 249 be32_to_cpu(data->tlpHdr4)); 250 if (data->sourceId || data->errorClass || 251 data->correlator) 252 pr_info("RootErrLog1: %08x %016llx %016llx\n", 253 be32_to_cpu(data->sourceId), 254 be64_to_cpu(data->errorClass), 255 be64_to_cpu(data->correlator)); 256 if (data->nFir) 257 pr_info("nFir: %016llx %016llx %016llx\n", 258 be64_to_cpu(data->nFir), 259 be64_to_cpu(data->nFirMask), 260 be64_to_cpu(data->nFirWOF)); 261 if (data->phbPlssr || data->phbCsr) 262 pr_info("PhbSts: %016llx %016llx\n", 263 be64_to_cpu(data->phbPlssr), 264 be64_to_cpu(data->phbCsr)); 265 if (data->lemFir) 266 pr_info("Lem: %016llx %016llx %016llx\n", 267 be64_to_cpu(data->lemFir), 268 be64_to_cpu(data->lemErrorMask), 269 be64_to_cpu(data->lemWOF)); 270 if (data->phbErrorStatus) 271 pr_info("PhbErr: %016llx %016llx %016llx %016llx\n", 272 be64_to_cpu(data->phbErrorStatus), 273 be64_to_cpu(data->phbFirstErrorStatus), 274 be64_to_cpu(data->phbErrorLog0), 275 be64_to_cpu(data->phbErrorLog1)); 276 if (data->mmioErrorStatus) 277 pr_info("OutErr: %016llx %016llx %016llx %016llx\n", 278 be64_to_cpu(data->mmioErrorStatus), 279 be64_to_cpu(data->mmioFirstErrorStatus), 280 be64_to_cpu(data->mmioErrorLog0), 281 be64_to_cpu(data->mmioErrorLog1)); 282 if (data->dma0ErrorStatus) 283 pr_info("InAErr: %016llx %016llx %016llx %016llx\n", 284 be64_to_cpu(data->dma0ErrorStatus), 285 be64_to_cpu(data->dma0FirstErrorStatus), 286 be64_to_cpu(data->dma0ErrorLog0), 287 be64_to_cpu(data->dma0ErrorLog1)); 288 if (data->dma1ErrorStatus) 289 pr_info("InBErr: %016llx %016llx %016llx %016llx\n", 290 be64_to_cpu(data->dma1ErrorStatus), 291 be64_to_cpu(data->dma1FirstErrorStatus), 292 be64_to_cpu(data->dma1ErrorLog0), 293 be64_to_cpu(data->dma1ErrorLog1)); 294 295 for (i = 0; i < OPAL_PHB3_NUM_PEST_REGS; i++) { 296 if ((be64_to_cpu(data->pestA[i]) >> 63) == 0 && 297 (be64_to_cpu(data->pestB[i]) >> 63) == 0) 298 continue; 299 300 pr_info("PE[%3d] A/B: %016llx %016llx\n", 301 i, be64_to_cpu(data->pestA[i]), 302 be64_to_cpu(data->pestB[i])); 303 } 304} 305 306void pnv_pci_dump_phb_diag_data(struct pci_controller *hose, 307 unsigned char *log_buff) 308{ 309 struct OpalIoPhbErrorCommon *common; 310 311 if (!hose || !log_buff) 312 return; 313 314 common = (struct OpalIoPhbErrorCommon *)log_buff; 315 switch (be32_to_cpu(common->ioType)) { 316 case OPAL_PHB_ERROR_DATA_TYPE_P7IOC: 317 pnv_pci_dump_p7ioc_diag_data(hose, common); 318 break; 319 case OPAL_PHB_ERROR_DATA_TYPE_PHB3: 320 pnv_pci_dump_phb3_diag_data(hose, common); 321 break; 322 default: 323 pr_warn("%s: Unrecognized ioType %d\n", 324 __func__, be32_to_cpu(common->ioType)); 325 } 326} 327 328static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no) 329{ 330 unsigned long flags, rc; 331 int has_diag, ret = 0; 332 333 spin_lock_irqsave(&phb->lock, flags); 334 335 /* Fetch PHB diag-data */ 336 rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob, 337 PNV_PCI_DIAG_BUF_SIZE); 338 has_diag = (rc == OPAL_SUCCESS); 339 340 /* If PHB supports compound PE, to handle it */ 341 if (phb->unfreeze_pe) { 342 ret = phb->unfreeze_pe(phb, 343 pe_no, 344 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 345 } else { 346 rc = opal_pci_eeh_freeze_clear(phb->opal_id, 347 pe_no, 348 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 349 if (rc) { 350 pr_warn("%s: Failure %ld clearing frozen " 351 "PHB#%x-PE#%x\n", 352 __func__, rc, phb->hose->global_number, 353 pe_no); 354 ret = -EIO; 355 } 356 } 357 358 /* 359 * For now, let's only display the diag buffer when we fail to clear 360 * the EEH status. We'll do more sensible things later when we have 361 * proper EEH support. We need to make sure we don't pollute ourselves 362 * with the normal errors generated when probing empty slots 363 */ 364 if (has_diag && ret) 365 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag.blob); 366 367 spin_unlock_irqrestore(&phb->lock, flags); 368} 369 370static void pnv_pci_config_check_eeh(struct pci_dn *pdn) 371{ 372 struct pnv_phb *phb = pdn->phb->private_data; 373 u8 fstate; 374 __be16 pcierr; 375 int pe_no; 376 s64 rc; 377 378 /* 379 * Get the PE#. During the PCI probe stage, we might not 380 * setup that yet. So all ER errors should be mapped to 381 * reserved PE. 382 */ 383 pe_no = pdn->pe_number; 384 if (pe_no == IODA_INVALID_PE) { 385 if (phb->type == PNV_PHB_P5IOC2) 386 pe_no = 0; 387 else 388 pe_no = phb->ioda.reserved_pe; 389 } 390 391 /* 392 * Fetch frozen state. If the PHB support compound PE, 393 * we need handle that case. 394 */ 395 if (phb->get_pe_state) { 396 fstate = phb->get_pe_state(phb, pe_no); 397 } else { 398 rc = opal_pci_eeh_freeze_status(phb->opal_id, 399 pe_no, 400 &fstate, 401 &pcierr, 402 NULL); 403 if (rc) { 404 pr_warn("%s: Failure %lld getting PHB#%x-PE#%x state\n", 405 __func__, rc, phb->hose->global_number, pe_no); 406 return; 407 } 408 } 409 410 cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n", 411 (pdn->busno << 8) | (pdn->devfn), pe_no, fstate); 412 413 /* Clear the frozen state if applicable */ 414 if (fstate == OPAL_EEH_STOPPED_MMIO_FREEZE || 415 fstate == OPAL_EEH_STOPPED_DMA_FREEZE || 416 fstate == OPAL_EEH_STOPPED_MMIO_DMA_FREEZE) { 417 /* 418 * If PHB supports compound PE, freeze it for 419 * consistency. 420 */ 421 if (phb->freeze_pe) 422 phb->freeze_pe(phb, pe_no); 423 424 pnv_pci_handle_eeh_config(phb, pe_no); 425 } 426} 427 428int pnv_pci_cfg_read(struct pci_dn *pdn, 429 int where, int size, u32 *val) 430{ 431 struct pnv_phb *phb = pdn->phb->private_data; 432 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 433 s64 rc; 434 435 switch (size) { 436 case 1: { 437 u8 v8; 438 rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8); 439 *val = (rc == OPAL_SUCCESS) ? v8 : 0xff; 440 break; 441 } 442 case 2: { 443 __be16 v16; 444 rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where, 445 &v16); 446 *val = (rc == OPAL_SUCCESS) ? be16_to_cpu(v16) : 0xffff; 447 break; 448 } 449 case 4: { 450 __be32 v32; 451 rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32); 452 *val = (rc == OPAL_SUCCESS) ? be32_to_cpu(v32) : 0xffffffff; 453 break; 454 } 455 default: 456 return PCIBIOS_FUNC_NOT_SUPPORTED; 457 } 458 459 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 460 __func__, pdn->busno, pdn->devfn, where, size, *val); 461 return PCIBIOS_SUCCESSFUL; 462} 463 464int pnv_pci_cfg_write(struct pci_dn *pdn, 465 int where, int size, u32 val) 466{ 467 struct pnv_phb *phb = pdn->phb->private_data; 468 u32 bdfn = (pdn->busno << 8) | pdn->devfn; 469 470 cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n", 471 pdn->busno, pdn->devfn, where, size, val); 472 switch (size) { 473 case 1: 474 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val); 475 break; 476 case 2: 477 opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val); 478 break; 479 case 4: 480 opal_pci_config_write_word(phb->opal_id, bdfn, where, val); 481 break; 482 default: 483 return PCIBIOS_FUNC_NOT_SUPPORTED; 484 } 485 486 return PCIBIOS_SUCCESSFUL; 487} 488 489#if CONFIG_EEH 490static bool pnv_pci_cfg_check(struct pci_dn *pdn) 491{ 492 struct eeh_dev *edev = NULL; 493 struct pnv_phb *phb = pdn->phb->private_data; 494 495 /* EEH not enabled ? */ 496 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 497 return true; 498 499 /* PE reset or device removed ? */ 500 edev = pdn->edev; 501 if (edev) { 502 if (edev->pe && 503 (edev->pe->state & EEH_PE_CFG_BLOCKED)) 504 return false; 505 506 if (edev->mode & EEH_DEV_REMOVED) 507 return false; 508 } 509 510 return true; 511} 512#else 513static inline pnv_pci_cfg_check(struct pci_dn *pdn) 514{ 515 return true; 516} 517#endif /* CONFIG_EEH */ 518 519static int pnv_pci_read_config(struct pci_bus *bus, 520 unsigned int devfn, 521 int where, int size, u32 *val) 522{ 523 struct pci_dn *pdn; 524 struct pnv_phb *phb; 525 int ret; 526 527 *val = 0xFFFFFFFF; 528 pdn = pci_get_pdn_by_devfn(bus, devfn); 529 if (!pdn) 530 return PCIBIOS_DEVICE_NOT_FOUND; 531 532 if (!pnv_pci_cfg_check(pdn)) 533 return PCIBIOS_DEVICE_NOT_FOUND; 534 535 ret = pnv_pci_cfg_read(pdn, where, size, val); 536 phb = pdn->phb->private_data; 537 if (phb->flags & PNV_PHB_FLAG_EEH && pdn->edev) { 538 if (*val == EEH_IO_ERROR_VALUE(size) && 539 eeh_dev_check_failure(pdn->edev)) 540 return PCIBIOS_DEVICE_NOT_FOUND; 541 } else { 542 pnv_pci_config_check_eeh(pdn); 543 } 544 545 return ret; 546} 547 548static int pnv_pci_write_config(struct pci_bus *bus, 549 unsigned int devfn, 550 int where, int size, u32 val) 551{ 552 struct pci_dn *pdn; 553 struct pnv_phb *phb; 554 int ret; 555 556 pdn = pci_get_pdn_by_devfn(bus, devfn); 557 if (!pdn) 558 return PCIBIOS_DEVICE_NOT_FOUND; 559 560 if (!pnv_pci_cfg_check(pdn)) 561 return PCIBIOS_DEVICE_NOT_FOUND; 562 563 ret = pnv_pci_cfg_write(pdn, where, size, val); 564 phb = pdn->phb->private_data; 565 if (!(phb->flags & PNV_PHB_FLAG_EEH)) 566 pnv_pci_config_check_eeh(pdn); 567 568 return ret; 569} 570 571struct pci_ops pnv_pci_ops = { 572 .read = pnv_pci_read_config, 573 .write = pnv_pci_write_config, 574}; 575 576static int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 577 unsigned long uaddr, enum dma_data_direction direction, 578 struct dma_attrs *attrs, bool rm) 579{ 580 u64 proto_tce; 581 __be64 *tcep, *tces; 582 u64 rpn; 583 584 proto_tce = TCE_PCI_READ; // Read allowed 585 586 if (direction != DMA_TO_DEVICE) 587 proto_tce |= TCE_PCI_WRITE; 588 589 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; 590 rpn = __pa(uaddr) >> tbl->it_page_shift; 591 592 while (npages--) 593 *(tcep++) = cpu_to_be64(proto_tce | 594 (rpn++ << tbl->it_page_shift)); 595 596 /* Some implementations won't cache invalid TCEs and thus may not 597 * need that flush. We'll probably turn it_type into a bit mask 598 * of flags if that becomes the case 599 */ 600 if (tbl->it_type & TCE_PCI_SWINV_CREATE) 601 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); 602 603 return 0; 604} 605 606static int pnv_tce_build_vm(struct iommu_table *tbl, long index, long npages, 607 unsigned long uaddr, 608 enum dma_data_direction direction, 609 struct dma_attrs *attrs) 610{ 611 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, 612 false); 613} 614 615static void pnv_tce_free(struct iommu_table *tbl, long index, long npages, 616 bool rm) 617{ 618 __be64 *tcep, *tces; 619 620 tces = tcep = ((__be64 *)tbl->it_base) + index - tbl->it_offset; 621 622 while (npages--) 623 *(tcep++) = cpu_to_be64(0); 624 625 if (tbl->it_type & TCE_PCI_SWINV_FREE) 626 pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1, rm); 627} 628 629static void pnv_tce_free_vm(struct iommu_table *tbl, long index, long npages) 630{ 631 pnv_tce_free(tbl, index, npages, false); 632} 633 634static unsigned long pnv_tce_get(struct iommu_table *tbl, long index) 635{ 636 return ((u64 *)tbl->it_base)[index - tbl->it_offset]; 637} 638 639static int pnv_tce_build_rm(struct iommu_table *tbl, long index, long npages, 640 unsigned long uaddr, 641 enum dma_data_direction direction, 642 struct dma_attrs *attrs) 643{ 644 return pnv_tce_build(tbl, index, npages, uaddr, direction, attrs, true); 645} 646 647static void pnv_tce_free_rm(struct iommu_table *tbl, long index, long npages) 648{ 649 pnv_tce_free(tbl, index, npages, true); 650} 651 652void pnv_pci_setup_iommu_table(struct iommu_table *tbl, 653 void *tce_mem, u64 tce_size, 654 u64 dma_offset, unsigned page_shift) 655{ 656 tbl->it_blocksize = 16; 657 tbl->it_base = (unsigned long)tce_mem; 658 tbl->it_page_shift = page_shift; 659 tbl->it_offset = dma_offset >> tbl->it_page_shift; 660 tbl->it_index = 0; 661 tbl->it_size = tce_size >> 3; 662 tbl->it_busno = 0; 663 tbl->it_type = TCE_PCI; 664} 665 666static void pnv_pci_dma_dev_setup(struct pci_dev *pdev) 667{ 668 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 669 struct pnv_phb *phb = hose->private_data; 670#ifdef CONFIG_PCI_IOV 671 struct pnv_ioda_pe *pe; 672 struct pci_dn *pdn; 673 674 /* Fix the VF pdn PE number */ 675 if (pdev->is_virtfn) { 676 pdn = pci_get_pdn(pdev); 677 WARN_ON(pdn->pe_number != IODA_INVALID_PE); 678 list_for_each_entry(pe, &phb->ioda.pe_list, list) { 679 if (pe->rid == ((pdev->bus->number << 8) | 680 (pdev->devfn & 0xff))) { 681 pdn->pe_number = pe->pe_number; 682 pe->pdev = pdev; 683 break; 684 } 685 } 686 } 687#endif /* CONFIG_PCI_IOV */ 688 689 if (phb && phb->dma_dev_setup) 690 phb->dma_dev_setup(phb, pdev); 691} 692 693int pnv_pci_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) 694{ 695 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 696 struct pnv_phb *phb = hose->private_data; 697 698 if (phb && phb->dma_set_mask) 699 return phb->dma_set_mask(phb, pdev, dma_mask); 700 return __dma_set_mask(&pdev->dev, dma_mask); 701} 702 703u64 pnv_pci_dma_get_required_mask(struct pci_dev *pdev) 704{ 705 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 706 struct pnv_phb *phb = hose->private_data; 707 708 if (phb && phb->dma_get_required_mask) 709 return phb->dma_get_required_mask(phb, pdev); 710 711 return __dma_get_required_mask(&pdev->dev); 712} 713 714void pnv_pci_shutdown(void) 715{ 716 struct pci_controller *hose; 717 718 list_for_each_entry(hose, &hose_list, list_node) { 719 struct pnv_phb *phb = hose->private_data; 720 721 if (phb && phb->shutdown) 722 phb->shutdown(phb); 723 } 724} 725 726/* Fixup wrong class code in p7ioc and p8 root complex */ 727static void pnv_p7ioc_rc_quirk(struct pci_dev *dev) 728{ 729 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 730} 731DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk); 732 733void __init pnv_pci_init(void) 734{ 735 struct device_node *np; 736 bool found_ioda = false; 737 738 pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN); 739 740 /* If we don't have OPAL, eg. in sim, just skip PCI probe */ 741 if (!firmware_has_feature(FW_FEATURE_OPAL)) 742 return; 743 744 /* Look for IODA IO-Hubs. We don't support mixing IODA 745 * and p5ioc2 due to the need to change some global 746 * probing flags 747 */ 748 for_each_compatible_node(np, NULL, "ibm,ioda-hub") { 749 pnv_pci_init_ioda_hub(np); 750 found_ioda = true; 751 } 752 753 /* Look for p5ioc2 IO-Hubs */ 754 if (!found_ioda) 755 for_each_compatible_node(np, NULL, "ibm,p5ioc2") 756 pnv_pci_init_p5ioc2_hub(np); 757 758 /* Look for ioda2 built-in PHB3's */ 759 for_each_compatible_node(np, NULL, "ibm,ioda2-phb") 760 pnv_pci_init_ioda2_phb(np); 761 762 /* Setup the linkage between OF nodes and PHBs */ 763 pci_devs_phb_init(); 764 765 /* Configure IOMMU DMA hooks */ 766 ppc_md.tce_build = pnv_tce_build_vm; 767 ppc_md.tce_free = pnv_tce_free_vm; 768 ppc_md.tce_build_rm = pnv_tce_build_rm; 769 ppc_md.tce_free_rm = pnv_tce_free_rm; 770 ppc_md.tce_get = pnv_tce_get; 771 set_pci_dma_ops(&dma_iommu_ops); 772 773 /* Configure MSIs */ 774#ifdef CONFIG_PCI_MSI 775 ppc_md.setup_msi_irqs = pnv_setup_msi_irqs; 776 ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs; 777#endif 778} 779 780machine_subsys_initcall_sync(powernv, tce_iommu_bus_notifier_init); 781 782struct pci_controller_ops pnv_pci_controller_ops = { 783 .dma_dev_setup = pnv_pci_dma_dev_setup, 784}; 785