1/*
2 * i8259 interrupt controller driver.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#undef DEBUG
10
11#include <linux/ioport.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/delay.h>
15#include <asm/io.h>
16#include <asm/i8259.h>
17#include <asm/prom.h>
18
19static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */
20
21static unsigned char cached_8259[2] = { 0xff, 0xff };
22#define cached_A1 (cached_8259[0])
23#define cached_21 (cached_8259[1])
24
25static DEFINE_RAW_SPINLOCK(i8259_lock);
26
27static struct irq_domain *i8259_host;
28
29/*
30 * Acknowledge the IRQ using either the PCI host bridge's interrupt
31 * acknowledge feature or poll.  How i8259_init() is called determines
32 * which is called.  It should be noted that polling is broken on some
33 * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
34 */
35unsigned int i8259_irq(void)
36{
37	int irq;
38	int lock = 0;
39
40	/* Either int-ack or poll for the IRQ */
41	if (pci_intack)
42		irq = readb(pci_intack);
43	else {
44		raw_spin_lock(&i8259_lock);
45		lock = 1;
46
47		/* Perform an interrupt acknowledge cycle on controller 1. */
48		outb(0x0C, 0x20);		/* prepare for poll */
49		irq = inb(0x20) & 7;
50		if (irq == 2 ) {
51			/*
52			 * Interrupt is cascaded so perform interrupt
53			 * acknowledge on controller 2.
54			 */
55			outb(0x0C, 0xA0);	/* prepare for poll */
56			irq = (inb(0xA0) & 7) + 8;
57		}
58	}
59
60	if (irq == 7) {
61		/*
62		 * This may be a spurious interrupt.
63		 *
64		 * Read the interrupt status register (ISR). If the most
65		 * significant bit is not set then there is no valid
66		 * interrupt.
67		 */
68		if (!pci_intack)
69			outb(0x0B, 0x20);	/* ISR register */
70		if(~inb(0x20) & 0x80)
71			irq = NO_IRQ;
72	} else if (irq == 0xff)
73		irq = NO_IRQ;
74
75	if (lock)
76		raw_spin_unlock(&i8259_lock);
77	return irq;
78}
79
80static void i8259_mask_and_ack_irq(struct irq_data *d)
81{
82	unsigned long flags;
83
84	raw_spin_lock_irqsave(&i8259_lock, flags);
85	if (d->irq > 7) {
86		cached_A1 |= 1 << (d->irq-8);
87		inb(0xA1); 	/* DUMMY */
88		outb(cached_A1, 0xA1);
89		outb(0x20, 0xA0);	/* Non-specific EOI */
90		outb(0x20, 0x20);	/* Non-specific EOI to cascade */
91	} else {
92		cached_21 |= 1 << d->irq;
93		inb(0x21); 	/* DUMMY */
94		outb(cached_21, 0x21);
95		outb(0x20, 0x20);	/* Non-specific EOI */
96	}
97	raw_spin_unlock_irqrestore(&i8259_lock, flags);
98}
99
100static void i8259_set_irq_mask(int irq_nr)
101{
102	outb(cached_A1,0xA1);
103	outb(cached_21,0x21);
104}
105
106static void i8259_mask_irq(struct irq_data *d)
107{
108	unsigned long flags;
109
110	pr_debug("i8259_mask_irq(%d)\n", d->irq);
111
112	raw_spin_lock_irqsave(&i8259_lock, flags);
113	if (d->irq < 8)
114		cached_21 |= 1 << d->irq;
115	else
116		cached_A1 |= 1 << (d->irq-8);
117	i8259_set_irq_mask(d->irq);
118	raw_spin_unlock_irqrestore(&i8259_lock, flags);
119}
120
121static void i8259_unmask_irq(struct irq_data *d)
122{
123	unsigned long flags;
124
125	pr_debug("i8259_unmask_irq(%d)\n", d->irq);
126
127	raw_spin_lock_irqsave(&i8259_lock, flags);
128	if (d->irq < 8)
129		cached_21 &= ~(1 << d->irq);
130	else
131		cached_A1 &= ~(1 << (d->irq-8));
132	i8259_set_irq_mask(d->irq);
133	raw_spin_unlock_irqrestore(&i8259_lock, flags);
134}
135
136static struct irq_chip i8259_pic = {
137	.name		= "i8259",
138	.irq_mask	= i8259_mask_irq,
139	.irq_disable	= i8259_mask_irq,
140	.irq_unmask	= i8259_unmask_irq,
141	.irq_mask_ack	= i8259_mask_and_ack_irq,
142};
143
144static struct resource pic1_iores = {
145	.name = "8259 (master)",
146	.start = 0x20,
147	.end = 0x21,
148	.flags = IORESOURCE_BUSY,
149};
150
151static struct resource pic2_iores = {
152	.name = "8259 (slave)",
153	.start = 0xa0,
154	.end = 0xa1,
155	.flags = IORESOURCE_BUSY,
156};
157
158static struct resource pic_edgectrl_iores = {
159	.name = "8259 edge control",
160	.start = 0x4d0,
161	.end = 0x4d1,
162	.flags = IORESOURCE_BUSY,
163};
164
165static int i8259_host_match(struct irq_domain *h, struct device_node *node)
166{
167	return h->of_node == NULL || h->of_node == node;
168}
169
170static int i8259_host_map(struct irq_domain *h, unsigned int virq,
171			  irq_hw_number_t hw)
172{
173	pr_debug("i8259_host_map(%d, 0x%lx)\n", virq, hw);
174
175	/* We block the internal cascade */
176	if (hw == 2)
177		irq_set_status_flags(virq, IRQ_NOREQUEST);
178
179	/* We use the level handler only for now, we might want to
180	 * be more cautious here but that works for now
181	 */
182	irq_set_status_flags(virq, IRQ_LEVEL);
183	irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
184	return 0;
185}
186
187static int i8259_host_xlate(struct irq_domain *h, struct device_node *ct,
188			    const u32 *intspec, unsigned int intsize,
189			    irq_hw_number_t *out_hwirq, unsigned int *out_flags)
190{
191	static unsigned char map_isa_senses[4] = {
192		IRQ_TYPE_LEVEL_LOW,
193		IRQ_TYPE_LEVEL_HIGH,
194		IRQ_TYPE_EDGE_FALLING,
195		IRQ_TYPE_EDGE_RISING,
196	};
197
198	*out_hwirq = intspec[0];
199	if (intsize > 1 && intspec[1] < 4)
200		*out_flags = map_isa_senses[intspec[1]];
201	else
202		*out_flags = IRQ_TYPE_NONE;
203
204	return 0;
205}
206
207static struct irq_domain_ops i8259_host_ops = {
208	.match = i8259_host_match,
209	.map = i8259_host_map,
210	.xlate = i8259_host_xlate,
211};
212
213struct irq_domain *i8259_get_host(void)
214{
215	return i8259_host;
216}
217
218/**
219 * i8259_init - Initialize the legacy controller
220 * @node: device node of the legacy PIC (can be NULL, but then, it will match
221 *        all interrupts, so beware)
222 * @intack_addr: PCI interrupt acknowledge (real) address which will return
223 *             	 the active irq from the 8259
224 */
225void i8259_init(struct device_node *node, unsigned long intack_addr)
226{
227	unsigned long flags;
228
229	/* initialize the controller */
230	raw_spin_lock_irqsave(&i8259_lock, flags);
231
232	/* Mask all first */
233	outb(0xff, 0xA1);
234	outb(0xff, 0x21);
235
236	/* init master interrupt controller */
237	outb(0x11, 0x20); /* Start init sequence */
238	outb(0x00, 0x21); /* Vector base */
239	outb(0x04, 0x21); /* edge tiggered, Cascade (slave) on IRQ2 */
240	outb(0x01, 0x21); /* Select 8086 mode */
241
242	/* init slave interrupt controller */
243	outb(0x11, 0xA0); /* Start init sequence */
244	outb(0x08, 0xA1); /* Vector base */
245	outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
246	outb(0x01, 0xA1); /* Select 8086 mode */
247
248	/* That thing is slow */
249	udelay(100);
250
251	/* always read ISR */
252	outb(0x0B, 0x20);
253	outb(0x0B, 0xA0);
254
255	/* Unmask the internal cascade */
256	cached_21 &= ~(1 << 2);
257
258	/* Set interrupt masks */
259	outb(cached_A1, 0xA1);
260	outb(cached_21, 0x21);
261
262	raw_spin_unlock_irqrestore(&i8259_lock, flags);
263
264	/* create a legacy host */
265	i8259_host = irq_domain_add_legacy_isa(node, &i8259_host_ops, NULL);
266	if (i8259_host == NULL) {
267		printk(KERN_ERR "i8259: failed to allocate irq host !\n");
268		return;
269	}
270
271	/* reserve our resources */
272	/* XXX should we continue doing that ? it seems to cause problems
273	 * with further requesting of PCI IO resources for that range...
274	 * need to look into it.
275	 */
276	request_resource(&ioport_resource, &pic1_iores);
277	request_resource(&ioport_resource, &pic2_iores);
278	request_resource(&ioport_resource, &pic_edgectrl_iores);
279
280	if (intack_addr != 0)
281		pci_intack = ioremap(intack_addr, 1);
282
283	printk(KERN_INFO "i8259 legacy interrupt controller initialized\n");
284}
285