1#ifndef _SPARC64_TSB_H 2#define _SPARC64_TSB_H 3 4/* The sparc64 TSB is similar to the powerpc hashtables. It's a 5 * power-of-2 sized table of TAG/PTE pairs. The cpu precomputes 6 * pointers into this table for 8K and 64K page sizes, and also a 7 * comparison TAG based upon the virtual address and context which 8 * faults. 9 * 10 * TLB miss trap handler software does the actual lookup via something 11 * of the form: 12 * 13 * ldxa [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1 14 * ldxa [%g0] ASI_{D,I}MMU, %g6 15 * sllx %g6, 22, %g6 16 * srlx %g6, 22, %g6 17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4 18 * cmp %g4, %g6 19 * bne,pn %xcc, tsb_miss_{d,i}tlb 20 * mov FAULT_CODE_{D,I}TLB, %g3 21 * stxa %g5, [%g0] ASI_{D,I}TLB_DATA_IN 22 * retry 23 * 24 * 25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte 26 * PTE. The TAG is of the same layout as the TLB TAG TARGET mmu 27 * register which is: 28 * 29 * ------------------------------------------------- 30 * | - | CONTEXT | - | VADDR bits 63:22 | 31 * ------------------------------------------------- 32 * 63 61 60 48 47 42 41 0 33 * 34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT 35 * field. 36 * 37 * Like the powerpc hashtables we need to use locking in order to 38 * synchronize while we update the entries. PTE updates need locking 39 * as well. 40 * 41 * We need to carefully choose a lock bits for the TSB entry. We 42 * choose to use bit 47 in the tag. Also, since we never map anything 43 * at page zero in context zero, we use zero as an invalid tag entry. 44 * When the lock bit is set, this forces a tag comparison failure. 45 */ 46 47#define TSB_TAG_LOCK_BIT 47 48#define TSB_TAG_LOCK_HIGH (1 << (TSB_TAG_LOCK_BIT - 32)) 49 50#define TSB_TAG_INVALID_BIT 46 51#define TSB_TAG_INVALID_HIGH (1 << (TSB_TAG_INVALID_BIT - 32)) 52 53/* Some cpus support physical address quad loads. We want to use 54 * those if possible so we don't need to hard-lock the TSB mapping 55 * into the TLB. We encode some instruction patching in order to 56 * support this. 57 * 58 * The kernel TSB is locked into the TLB by virtue of being in the 59 * kernel image, so we don't play these games for swapper_tsb access. 60 */ 61#ifndef __ASSEMBLY__ 62struct tsb_ldquad_phys_patch_entry { 63 unsigned int addr; 64 unsigned int sun4u_insn; 65 unsigned int sun4v_insn; 66}; 67extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch, 68 __tsb_ldquad_phys_patch_end; 69 70struct tsb_phys_patch_entry { 71 unsigned int addr; 72 unsigned int insn; 73}; 74extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; 75#endif 76#define TSB_LOAD_QUAD(TSB, REG) \ 77661: ldda [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \ 78 .section .tsb_ldquad_phys_patch, "ax"; \ 79 .word 661b; \ 80 ldda [TSB] ASI_QUAD_LDD_PHYS, REG; \ 81 ldda [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \ 82 .previous 83 84#define TSB_LOAD_TAG_HIGH(TSB, REG) \ 85661: lduwa [TSB] ASI_N, REG; \ 86 .section .tsb_phys_patch, "ax"; \ 87 .word 661b; \ 88 lduwa [TSB] ASI_PHYS_USE_EC, REG; \ 89 .previous 90 91#define TSB_LOAD_TAG(TSB, REG) \ 92661: ldxa [TSB] ASI_N, REG; \ 93 .section .tsb_phys_patch, "ax"; \ 94 .word 661b; \ 95 ldxa [TSB] ASI_PHYS_USE_EC, REG; \ 96 .previous 97 98#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \ 99661: casa [TSB] ASI_N, REG1, REG2; \ 100 .section .tsb_phys_patch, "ax"; \ 101 .word 661b; \ 102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \ 103 .previous 104 105#define TSB_CAS_TAG(TSB, REG1, REG2) \ 106661: casxa [TSB] ASI_N, REG1, REG2; \ 107 .section .tsb_phys_patch, "ax"; \ 108 .word 661b; \ 109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \ 110 .previous 111 112#define TSB_STORE(ADDR, VAL) \ 113661: stxa VAL, [ADDR] ASI_N; \ 114 .section .tsb_phys_patch, "ax"; \ 115 .word 661b; \ 116 stxa VAL, [ADDR] ASI_PHYS_USE_EC; \ 117 .previous 118 119#define TSB_LOCK_TAG(TSB, REG1, REG2) \ 12099: TSB_LOAD_TAG_HIGH(TSB, REG1); \ 121 sethi %hi(TSB_TAG_LOCK_HIGH), REG2;\ 122 andcc REG1, REG2, %g0; \ 123 bne,pn %icc, 99b; \ 124 nop; \ 125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \ 126 cmp REG1, REG2; \ 127 bne,pn %icc, 99b; \ 128 nop; \ 129 130#define TSB_WRITE(TSB, TTE, TAG) \ 131 add TSB, 0x8, TSB; \ 132 TSB_STORE(TSB, TTE); \ 133 sub TSB, 0x8, TSB; \ 134 TSB_STORE(TSB, TAG); 135 136 /* Do a kernel page table walk. Leaves valid PTE value in 137 * REG1. Jumps to FAIL_LABEL on early page table walk 138 * termination. VADDR will not be clobbered, but REG2 will. 139 * 140 * There are two masks we must apply to propagate bits from 141 * the virtual address into the PTE physical address field 142 * when dealing with huge pages. This is because the page 143 * table boundaries do not match the huge page size(s) the 144 * hardware supports. 145 * 146 * In these cases we propagate the bits that are below the 147 * page table level where we saw the huge page mapping, but 148 * are still within the relevant physical bits for the huge 149 * page size in question. So for PMD mappings (which fall on 150 * bit 23, for 8MB per PMD) we must propagate bit 22 for a 151 * 4MB huge page. For huge PUDs (which fall on bit 33, for 152 * 8GB per PUD), we have to accomodate 256MB and 2GB huge 153 * pages. So for those we propagate bits 32 to 28. 154 */ 155#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \ 156 sethi %hi(swapper_pg_dir), REG1; \ 157 or REG1, %lo(swapper_pg_dir), REG1; \ 158 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \ 159 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 160 andn REG2, 0x7, REG2; \ 161 ldx [REG1 + REG2], REG1; \ 162 brz,pn REG1, FAIL_LABEL; \ 163 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \ 164 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 165 andn REG2, 0x7, REG2; \ 166 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \ 167 brz,pn REG1, FAIL_LABEL; \ 168 sethi %uhi(_PAGE_PUD_HUGE), REG2; \ 169 brz,pn REG1, FAIL_LABEL; \ 170 sllx REG2, 32, REG2; \ 171 andcc REG1, REG2, %g0; \ 172 sethi %hi(0xf8000000), REG2; \ 173 bne,pt %xcc, 697f; \ 174 sllx REG2, 1, REG2; \ 175 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \ 176 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 177 andn REG2, 0x7, REG2; \ 178 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \ 179 sethi %uhi(_PAGE_PMD_HUGE), REG2; \ 180 brz,pn REG1, FAIL_LABEL; \ 181 sllx REG2, 32, REG2; \ 182 andcc REG1, REG2, %g0; \ 183 be,pn %xcc, 698f; \ 184 sethi %hi(0x400000), REG2; \ 185697: brgez,pn REG1, FAIL_LABEL; \ 186 andn REG1, REG2, REG1; \ 187 and VADDR, REG2, REG2; \ 188 ba,pt %xcc, 699f; \ 189 or REG1, REG2, REG1; \ 190698: sllx VADDR, 64 - PMD_SHIFT, REG2; \ 191 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 192 andn REG2, 0x7, REG2; \ 193 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \ 194 brgez,pn REG1, FAIL_LABEL; \ 195 nop; \ 196699: 197 198 /* PMD has been loaded into REG1, interpret the value, seeing 199 * if it is a HUGE PMD or a normal one. If it is not valid 200 * then jump to FAIL_LABEL. If it is a HUGE PMD, and it 201 * translates to a valid PTE, branch to PTE_LABEL. 202 * 203 * We have to propagate the 4MB bit of the virtual address 204 * because we are fabricating 8MB pages using 4MB hw pages. 205 */ 206#ifdef CONFIG_TRANSPARENT_HUGEPAGE 207#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ 208 brz,pn REG1, FAIL_LABEL; \ 209 sethi %uhi(_PAGE_PMD_HUGE), REG2; \ 210 sllx REG2, 32, REG2; \ 211 andcc REG1, REG2, %g0; \ 212 be,pt %xcc, 700f; \ 213 sethi %hi(4 * 1024 * 1024), REG2; \ 214 brgez,pn REG1, FAIL_LABEL; \ 215 andn REG1, REG2, REG1; \ 216 and VADDR, REG2, REG2; \ 217 brlz,pt REG1, PTE_LABEL; \ 218 or REG1, REG2, REG1; \ 219700: 220#else 221#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \ 222 brz,pn REG1, FAIL_LABEL; \ 223 nop; 224#endif 225 226 /* Do a user page table walk in MMU globals. Leaves final, 227 * valid, PTE value in REG1. Jumps to FAIL_LABEL on early 228 * page table walk termination or if the PTE is not valid. 229 * 230 * Physical base of page tables is in PHYS_PGD which will not 231 * be modified. 232 * 233 * VADDR will not be clobbered, but REG1 and REG2 will. 234 */ 235#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \ 236 sllx VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \ 237 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 238 andn REG2, 0x7, REG2; \ 239 ldxa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \ 240 brz,pn REG1, FAIL_LABEL; \ 241 sllx VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \ 242 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 243 andn REG2, 0x7, REG2; \ 244 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \ 245 brz,pn REG1, FAIL_LABEL; \ 246 sllx VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \ 247 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 248 andn REG2, 0x7, REG2; \ 249 ldxa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \ 250 USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \ 251 sllx VADDR, 64 - PMD_SHIFT, REG2; \ 252 srlx REG2, 64 - PAGE_SHIFT, REG2; \ 253 andn REG2, 0x7, REG2; \ 254 add REG1, REG2, REG1; \ 255 ldxa [REG1] ASI_PHYS_USE_EC, REG1; \ 256 brgez,pn REG1, FAIL_LABEL; \ 257 nop; \ 258800: 259 260/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0. 261 * If no entry is found, FAIL_LABEL will be branched to. On success 262 * the resulting PTE value will be left in REG1. VADDR is preserved 263 * by this routine. 264 */ 265#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \ 266 sethi %hi(prom_trans), REG1; \ 267 or REG1, %lo(prom_trans), REG1; \ 26897: ldx [REG1 + 0x00], REG2; \ 269 brz,pn REG2, FAIL_LABEL; \ 270 nop; \ 271 ldx [REG1 + 0x08], REG3; \ 272 add REG2, REG3, REG3; \ 273 cmp REG2, VADDR; \ 274 bgu,pt %xcc, 98f; \ 275 cmp VADDR, REG3; \ 276 bgeu,pt %xcc, 98f; \ 277 ldx [REG1 + 0x10], REG3; \ 278 sub VADDR, REG2, REG2; \ 279 ba,pt %xcc, 99f; \ 280 add REG3, REG2, REG1; \ 28198: ba,pt %xcc, 97b; \ 282 add REG1, (3 * 8), REG1; \ 28399: 284 285 /* We use a 32K TSB for the whole kernel, this allows to 286 * handle about 16MB of modules and vmalloc mappings without 287 * incurring many hash conflicts. 288 */ 289#define KERNEL_TSB_SIZE_BYTES (32 * 1024) 290#define KERNEL_TSB_NENTRIES \ 291 (KERNEL_TSB_SIZE_BYTES / 16) 292#define KERNEL_TSB4M_NENTRIES 4096 293 294 /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL 295 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries 296 * and the found TTE will be left in REG1. REG3 and REG4 must 297 * be an even/odd pair of registers. 298 * 299 * VADDR and TAG will be preserved and not clobbered by this macro. 300 */ 301#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ 302661: sethi %uhi(swapper_tsb), REG1; \ 303 sethi %hi(swapper_tsb), REG2; \ 304 or REG1, %ulo(swapper_tsb), REG1; \ 305 or REG2, %lo(swapper_tsb), REG2; \ 306 .section .swapper_tsb_phys_patch, "ax"; \ 307 .word 661b; \ 308 .previous; \ 309 sllx REG1, 32, REG1; \ 310 or REG1, REG2, REG1; \ 311 srlx VADDR, PAGE_SHIFT, REG2; \ 312 and REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \ 313 sllx REG2, 4, REG2; \ 314 add REG1, REG2, REG2; \ 315 TSB_LOAD_QUAD(REG2, REG3); \ 316 cmp REG3, TAG; \ 317 be,a,pt %xcc, OK_LABEL; \ 318 mov REG4, REG1; 319 320#ifndef CONFIG_DEBUG_PAGEALLOC 321 /* This version uses a trick, the TAG is already (VADDR >> 22) so 322 * we can make use of that for the index computation. 323 */ 324#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \ 325661: sethi %uhi(swapper_4m_tsb), REG1; \ 326 sethi %hi(swapper_4m_tsb), REG2; \ 327 or REG1, %ulo(swapper_4m_tsb), REG1; \ 328 or REG2, %lo(swapper_4m_tsb), REG2; \ 329 .section .swapper_4m_tsb_phys_patch, "ax"; \ 330 .word 661b; \ 331 .previous; \ 332 sllx REG1, 32, REG1; \ 333 or REG1, REG2, REG1; \ 334 and TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \ 335 sllx REG2, 4, REG2; \ 336 add REG1, REG2, REG2; \ 337 TSB_LOAD_QUAD(REG2, REG3); \ 338 cmp REG3, TAG; \ 339 be,a,pt %xcc, OK_LABEL; \ 340 mov REG4, REG1; 341#endif 342 343#endif /* !(_SPARC64_TSB_H) */ 344