1#ifndef _ASM_X86_AMD_NB_H
2#define _ASM_X86_AMD_NB_H
3
4#include <linux/ioport.h>
5#include <linux/pci.h>
6
7struct amd_nb_bus_dev_range {
8	u8 bus;
9	u8 dev_base;
10	u8 dev_limit;
11};
12
13extern const struct pci_device_id amd_nb_misc_ids[];
14extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
15
16extern bool early_is_amd_nb(u32 value);
17extern struct resource *amd_get_mmconfig_range(struct resource *res);
18extern int amd_cache_northbridges(void);
19extern void amd_flush_garts(void);
20extern int amd_numa_init(void);
21extern int amd_get_subcaches(int);
22extern int amd_set_subcaches(int, unsigned long);
23
24struct amd_l3_cache {
25	unsigned indices;
26	u8	 subcaches[4];
27};
28
29struct threshold_block {
30	unsigned int		block;
31	unsigned int		bank;
32	unsigned int		cpu;
33	u32			address;
34	u16			interrupt_enable;
35	bool			interrupt_capable;
36	u16			threshold_limit;
37	struct kobject		kobj;
38	struct list_head	miscj;
39};
40
41struct threshold_bank {
42	struct kobject		*kobj;
43	struct threshold_block	*blocks;
44
45	/* initialized to the number of CPUs on the node sharing this bank */
46	atomic_t		cpus;
47};
48
49struct amd_northbridge {
50	struct pci_dev *misc;
51	struct pci_dev *link;
52	struct amd_l3_cache l3_cache;
53	struct threshold_bank *bank4;
54};
55
56struct amd_northbridge_info {
57	u16 num;
58	u64 flags;
59	struct amd_northbridge *nb;
60};
61extern struct amd_northbridge_info amd_northbridges;
62
63#define AMD_NB_GART			BIT(0)
64#define AMD_NB_L3_INDEX_DISABLE		BIT(1)
65#define AMD_NB_L3_PARTITIONING		BIT(2)
66
67#ifdef CONFIG_AMD_NB
68
69static inline u16 amd_nb_num(void)
70{
71	return amd_northbridges.num;
72}
73
74static inline bool amd_nb_has_feature(unsigned feature)
75{
76	return ((amd_northbridges.flags & feature) == feature);
77}
78
79static inline struct amd_northbridge *node_to_amd_nb(int node)
80{
81	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
82}
83
84static inline u16 amd_get_node_id(struct pci_dev *pdev)
85{
86	struct pci_dev *misc;
87	int i;
88
89	for (i = 0; i != amd_nb_num(); i++) {
90		misc = node_to_amd_nb(i)->misc;
91
92		if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
93		    PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
94			return i;
95	}
96
97	WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
98	return 0;
99}
100
101#else
102
103#define amd_nb_num(x)		0
104#define amd_nb_has_feature(x)	false
105#define node_to_amd_nb(x)	NULL
106
107#endif
108
109
110#endif /* _ASM_X86_AMD_NB_H */
111