1#ifndef _ASM_X86_MPSPEC_H
2#define _ASM_X86_MPSPEC_H
3
4
5#include <asm/mpspec_def.h>
6#include <asm/x86_init.h>
7#include <asm/apicdef.h>
8
9extern int apic_version[];
10extern int pic_mode;
11
12#ifdef CONFIG_X86_32
13
14/*
15 * Summit or generic (i.e. installer) kernels need lots of bus entries.
16 * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
17 */
18#if CONFIG_BASE_SMALL == 0
19# define MAX_MP_BUSSES		260
20#else
21# define MAX_MP_BUSSES		32
22#endif
23
24#define MAX_IRQ_SOURCES		256
25
26extern unsigned int def_to_bigsmp;
27
28#else /* CONFIG_X86_64: */
29
30#define MAX_MP_BUSSES		256
31/* Each PCI slot may be a combo card with its own bus.  4 IRQ pins per slot. */
32#define MAX_IRQ_SOURCES		(MAX_MP_BUSSES * 4)
33
34#endif /* CONFIG_X86_64 */
35
36#ifdef CONFIG_EISA
37extern int mp_bus_id_to_type[MAX_MP_BUSSES];
38#endif
39
40extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
41
42extern unsigned int boot_cpu_physical_apicid;
43extern unsigned long mp_lapic_addr;
44
45#ifdef CONFIG_X86_LOCAL_APIC
46extern int smp_found_config;
47#else
48# define smp_found_config 0
49#endif
50
51static inline void get_smp_config(void)
52{
53	x86_init.mpparse.get_smp_config(0);
54}
55
56static inline void early_get_smp_config(void)
57{
58	x86_init.mpparse.get_smp_config(1);
59}
60
61static inline void find_smp_config(void)
62{
63	x86_init.mpparse.find_smp_config();
64}
65
66#ifdef CONFIG_X86_MPPARSE
67extern void early_reserve_e820_mpc_new(void);
68extern int enable_update_mptable;
69extern int default_mpc_apic_id(struct mpc_cpu *m);
70extern void default_smp_read_mpc_oem(struct mpc_table *mpc);
71# ifdef CONFIG_X86_IO_APIC
72extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str);
73# else
74#  define default_mpc_oem_bus_info NULL
75# endif
76extern void default_find_smp_config(void);
77extern void default_get_smp_config(unsigned int early);
78#else
79static inline void early_reserve_e820_mpc_new(void) { }
80#define enable_update_mptable 0
81#define default_mpc_apic_id NULL
82#define default_smp_read_mpc_oem NULL
83#define default_mpc_oem_bus_info NULL
84#define default_find_smp_config x86_init_noop
85#define default_get_smp_config x86_init_uint_noop
86#endif
87
88int generic_processor_info(int apicid, int version);
89
90#define PHYSID_ARRAY_SIZE	BITS_TO_LONGS(MAX_LOCAL_APIC)
91
92struct physid_mask {
93	unsigned long mask[PHYSID_ARRAY_SIZE];
94};
95
96typedef struct physid_mask physid_mask_t;
97
98#define physid_set(physid, map)			set_bit(physid, (map).mask)
99#define physid_clear(physid, map)		clear_bit(physid, (map).mask)
100#define physid_isset(physid, map)		test_bit(physid, (map).mask)
101#define physid_test_and_set(physid, map)			\
102	test_and_set_bit(physid, (map).mask)
103
104#define physids_and(dst, src1, src2)					\
105	bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
106
107#define physids_or(dst, src1, src2)					\
108	bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
109
110#define physids_clear(map)					\
111	bitmap_zero((map).mask, MAX_LOCAL_APIC)
112
113#define physids_complement(dst, src)				\
114	bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
115
116#define physids_empty(map)					\
117	bitmap_empty((map).mask, MAX_LOCAL_APIC)
118
119#define physids_equal(map1, map2)				\
120	bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
121
122#define physids_weight(map)					\
123	bitmap_weight((map).mask, MAX_LOCAL_APIC)
124
125#define physids_shift_right(d, s, n)				\
126	bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
127
128#define physids_shift_left(d, s, n)				\
129	bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
130
131static inline unsigned long physids_coerce(physid_mask_t *map)
132{
133	return map->mask[0];
134}
135
136static inline void physids_promote(unsigned long physids, physid_mask_t *map)
137{
138	physids_clear(*map);
139	map->mask[0] = physids;
140}
141
142static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
143{
144	physids_clear(*map);
145	physid_set(physid, *map);
146}
147
148#define PHYSID_MASK_ALL		{ {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
149#define PHYSID_MASK_NONE	{ {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
150
151extern physid_mask_t phys_cpu_present_map;
152
153#endif /* _ASM_X86_MPSPEC_H */
154