1/*
2 *	Low-Level PCI Access for i386 machines.
3 *
4 *	(c) 1999 Martin Mares <mj@ucw.cz>
5 */
6
7#undef DEBUG
8
9#ifdef DEBUG
10#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
11#else
12#define DBG(fmt, ...)				\
13do {						\
14	if (0)					\
15		printk(fmt, ##__VA_ARGS__);	\
16} while (0)
17#endif
18
19#define PCI_PROBE_BIOS		0x0001
20#define PCI_PROBE_CONF1		0x0002
21#define PCI_PROBE_CONF2		0x0004
22#define PCI_PROBE_MMCONF	0x0008
23#define PCI_PROBE_MASK		0x000f
24#define PCI_PROBE_NOEARLY	0x0010
25
26#define PCI_NO_CHECKS		0x0400
27#define PCI_USE_PIRQ_MASK	0x0800
28#define PCI_ASSIGN_ROMS		0x1000
29#define PCI_BIOS_IRQ_SCAN	0x2000
30#define PCI_ASSIGN_ALL_BUSSES	0x4000
31#define PCI_CAN_SKIP_ISA_ALIGN	0x8000
32#define PCI_USE__CRS		0x10000
33#define PCI_CHECK_ENABLE_AMD_MMCONF	0x20000
34#define PCI_HAS_IO_ECS		0x40000
35#define PCI_NOASSIGN_ROMS	0x80000
36#define PCI_ROOT_NO_CRS		0x100000
37#define PCI_NOASSIGN_BARS	0x200000
38
39extern unsigned int pci_probe;
40extern unsigned long pirq_table_addr;
41
42enum pci_bf_sort_state {
43	pci_bf_sort_default,
44	pci_force_nobf,
45	pci_force_bf,
46	pci_dmi_bf,
47};
48
49/* pci-i386.c */
50
51void pcibios_resource_survey(void);
52void pcibios_set_cache_line_size(void);
53
54/* pci-pc.c */
55
56extern int pcibios_last_bus;
57extern struct pci_ops pci_root_ops;
58
59void pcibios_scan_specific_bus(int busn);
60
61/* pci-irq.c */
62
63struct irq_info {
64	u8 bus, devfn;			/* Bus, device and function */
65	struct {
66		u8 link;		/* IRQ line ID, chipset dependent,
67					   0 = not routed */
68		u16 bitmap;		/* Available IRQs */
69	} __attribute__((packed)) irq[4];
70	u8 slot;			/* Slot number, 0=onboard */
71	u8 rfu;
72} __attribute__((packed));
73
74struct irq_routing_table {
75	u32 signature;			/* PIRQ_SIGNATURE should be here */
76	u16 version;			/* PIRQ_VERSION */
77	u16 size;			/* Table size in bytes */
78	u8 rtr_bus, rtr_devfn;		/* Where the interrupt router lies */
79	u16 exclusive_irqs;		/* IRQs devoted exclusively to
80					   PCI usage */
81	u16 rtr_vendor, rtr_device;	/* Vendor and device ID of
82					   interrupt router */
83	u32 miniport_data;		/* Crap */
84	u8 rfu[11];
85	u8 checksum;			/* Modulo 256 checksum must give 0 */
86	struct irq_info slots[0];
87} __attribute__((packed));
88
89extern unsigned int pcibios_irq_mask;
90
91extern raw_spinlock_t pci_config_lock;
92
93extern int (*pcibios_enable_irq)(struct pci_dev *dev);
94extern void (*pcibios_disable_irq)(struct pci_dev *dev);
95
96extern bool mp_should_keep_irq(struct device *dev);
97
98struct pci_raw_ops {
99	int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
100						int reg, int len, u32 *val);
101	int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
102						int reg, int len, u32 val);
103};
104
105extern const struct pci_raw_ops *raw_pci_ops;
106extern const struct pci_raw_ops *raw_pci_ext_ops;
107
108extern const struct pci_raw_ops pci_mmcfg;
109extern const struct pci_raw_ops pci_direct_conf1;
110extern bool port_cf9_safe;
111
112/* arch_initcall level */
113extern int pci_direct_probe(void);
114extern void pci_direct_init(int type);
115extern void pci_pcbios_init(void);
116extern void __init dmi_check_pciprobe(void);
117extern void __init dmi_check_skip_isa_align(void);
118
119/* some common used subsys_initcalls */
120extern int __init pci_acpi_init(void);
121extern void __init pcibios_irq_init(void);
122extern int __init pcibios_init(void);
123extern int pci_legacy_init(void);
124extern void pcibios_fixup_irqs(void);
125
126/* pci-mmconfig.c */
127
128/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
129#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
130
131struct pci_mmcfg_region {
132	struct list_head list;
133	struct resource res;
134	u64 address;
135	char __iomem *virt;
136	u16 segment;
137	u8 start_bus;
138	u8 end_bus;
139	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
140};
141
142extern int __init pci_mmcfg_arch_init(void);
143extern void __init pci_mmcfg_arch_free(void);
144extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
145extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
146extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
147			       phys_addr_t addr);
148extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
149extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
150
151extern struct list_head pci_mmcfg_list;
152
153#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)
154
155/*
156 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
157 * on their northbrige except through the * %eax register. As such, you MUST
158 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
159 * accessor functions.
160 * In fact just use pci_config_*, nothing else please.
161 */
162static inline unsigned char mmio_config_readb(void __iomem *pos)
163{
164	u8 val;
165	asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
166	return val;
167}
168
169static inline unsigned short mmio_config_readw(void __iomem *pos)
170{
171	u16 val;
172	asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
173	return val;
174}
175
176static inline unsigned int mmio_config_readl(void __iomem *pos)
177{
178	u32 val;
179	asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
180	return val;
181}
182
183static inline void mmio_config_writeb(void __iomem *pos, u8 val)
184{
185	asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
186}
187
188static inline void mmio_config_writew(void __iomem *pos, u16 val)
189{
190	asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
191}
192
193static inline void mmio_config_writel(void __iomem *pos, u32 val)
194{
195	asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
196}
197
198#ifdef CONFIG_PCI
199# ifdef CONFIG_ACPI
200#  define x86_default_pci_init		pci_acpi_init
201# else
202#  define x86_default_pci_init		pci_legacy_init
203# endif
204# define x86_default_pci_init_irq	pcibios_irq_init
205# define x86_default_pci_fixup_irqs	pcibios_fixup_irqs
206#else
207# define x86_default_pci_init		NULL
208# define x86_default_pci_init_irq	NULL
209# define x86_default_pci_fixup_irqs	NULL
210#endif
211