1/* 2 * vmx.h: VMX Architecture related definitions 3 * Copyright (c) 2004, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 16 * Place - Suite 330, Boston, MA 02111-1307 USA. 17 * 18 * A few random additions are: 19 * Copyright (C) 2006 Qumranet 20 * Avi Kivity <avi@qumranet.com> 21 * Yaniv Kamay <yaniv@qumranet.com> 22 * 23 */ 24#ifndef VMX_H 25#define VMX_H 26 27 28#include <linux/types.h> 29#include <uapi/asm/vmx.h> 30 31/* 32 * Definitions of Primary Processor-Based VM-Execution Controls. 33 */ 34#define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 35#define CPU_BASED_USE_TSC_OFFSETING 0x00000008 36#define CPU_BASED_HLT_EXITING 0x00000080 37#define CPU_BASED_INVLPG_EXITING 0x00000200 38#define CPU_BASED_MWAIT_EXITING 0x00000400 39#define CPU_BASED_RDPMC_EXITING 0x00000800 40#define CPU_BASED_RDTSC_EXITING 0x00001000 41#define CPU_BASED_CR3_LOAD_EXITING 0x00008000 42#define CPU_BASED_CR3_STORE_EXITING 0x00010000 43#define CPU_BASED_CR8_LOAD_EXITING 0x00080000 44#define CPU_BASED_CR8_STORE_EXITING 0x00100000 45#define CPU_BASED_TPR_SHADOW 0x00200000 46#define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 47#define CPU_BASED_MOV_DR_EXITING 0x00800000 48#define CPU_BASED_UNCOND_IO_EXITING 0x01000000 49#define CPU_BASED_USE_IO_BITMAPS 0x02000000 50#define CPU_BASED_USE_MSR_BITMAPS 0x10000000 51#define CPU_BASED_MONITOR_EXITING 0x20000000 52#define CPU_BASED_PAUSE_EXITING 0x40000000 53#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 54 55#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172 56 57/* 58 * Definitions of Secondary Processor-Based VM-Execution Controls. 59 */ 60#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 61#define SECONDARY_EXEC_ENABLE_EPT 0x00000002 62#define SECONDARY_EXEC_RDTSCP 0x00000008 63#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 64#define SECONDARY_EXEC_ENABLE_VPID 0x00000020 65#define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 66#define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 67#define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 68#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 69#define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 70#define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 71#define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 72#define SECONDARY_EXEC_ENABLE_PML 0x00020000 73#define SECONDARY_EXEC_XSAVES 0x00100000 74 75 76#define PIN_BASED_EXT_INTR_MASK 0x00000001 77#define PIN_BASED_NMI_EXITING 0x00000008 78#define PIN_BASED_VIRTUAL_NMIS 0x00000020 79#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 80#define PIN_BASED_POSTED_INTR 0x00000080 81 82#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 83 84#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 85#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 86#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 87#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 88#define VM_EXIT_SAVE_IA32_PAT 0x00040000 89#define VM_EXIT_LOAD_IA32_PAT 0x00080000 90#define VM_EXIT_SAVE_IA32_EFER 0x00100000 91#define VM_EXIT_LOAD_IA32_EFER 0x00200000 92#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 93#define VM_EXIT_CLEAR_BNDCFGS 0x00800000 94 95#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 96 97#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 98#define VM_ENTRY_IA32E_MODE 0x00000200 99#define VM_ENTRY_SMM 0x00000400 100#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 101#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 102#define VM_ENTRY_LOAD_IA32_PAT 0x00004000 103#define VM_ENTRY_LOAD_IA32_EFER 0x00008000 104#define VM_ENTRY_LOAD_BNDCFGS 0x00010000 105 106#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 107 108#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 109#define VMX_MISC_SAVE_EFER_LMA 0x00000020 110#define VMX_MISC_ACTIVITY_HLT 0x00000040 111 112/* VMCS Encodings */ 113enum vmcs_field { 114 VIRTUAL_PROCESSOR_ID = 0x00000000, 115 POSTED_INTR_NV = 0x00000002, 116 GUEST_ES_SELECTOR = 0x00000800, 117 GUEST_CS_SELECTOR = 0x00000802, 118 GUEST_SS_SELECTOR = 0x00000804, 119 GUEST_DS_SELECTOR = 0x00000806, 120 GUEST_FS_SELECTOR = 0x00000808, 121 GUEST_GS_SELECTOR = 0x0000080a, 122 GUEST_LDTR_SELECTOR = 0x0000080c, 123 GUEST_TR_SELECTOR = 0x0000080e, 124 GUEST_INTR_STATUS = 0x00000810, 125 GUEST_PML_INDEX = 0x00000812, 126 HOST_ES_SELECTOR = 0x00000c00, 127 HOST_CS_SELECTOR = 0x00000c02, 128 HOST_SS_SELECTOR = 0x00000c04, 129 HOST_DS_SELECTOR = 0x00000c06, 130 HOST_FS_SELECTOR = 0x00000c08, 131 HOST_GS_SELECTOR = 0x00000c0a, 132 HOST_TR_SELECTOR = 0x00000c0c, 133 IO_BITMAP_A = 0x00002000, 134 IO_BITMAP_A_HIGH = 0x00002001, 135 IO_BITMAP_B = 0x00002002, 136 IO_BITMAP_B_HIGH = 0x00002003, 137 MSR_BITMAP = 0x00002004, 138 MSR_BITMAP_HIGH = 0x00002005, 139 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 140 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 141 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 142 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 143 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 144 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 145 PML_ADDRESS = 0x0000200e, 146 PML_ADDRESS_HIGH = 0x0000200f, 147 TSC_OFFSET = 0x00002010, 148 TSC_OFFSET_HIGH = 0x00002011, 149 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 150 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 151 APIC_ACCESS_ADDR = 0x00002014, 152 APIC_ACCESS_ADDR_HIGH = 0x00002015, 153 POSTED_INTR_DESC_ADDR = 0x00002016, 154 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 155 EPT_POINTER = 0x0000201a, 156 EPT_POINTER_HIGH = 0x0000201b, 157 EOI_EXIT_BITMAP0 = 0x0000201c, 158 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 159 EOI_EXIT_BITMAP1 = 0x0000201e, 160 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 161 EOI_EXIT_BITMAP2 = 0x00002020, 162 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 163 EOI_EXIT_BITMAP3 = 0x00002022, 164 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 165 VMREAD_BITMAP = 0x00002026, 166 VMWRITE_BITMAP = 0x00002028, 167 XSS_EXIT_BITMAP = 0x0000202C, 168 XSS_EXIT_BITMAP_HIGH = 0x0000202D, 169 GUEST_PHYSICAL_ADDRESS = 0x00002400, 170 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 171 VMCS_LINK_POINTER = 0x00002800, 172 VMCS_LINK_POINTER_HIGH = 0x00002801, 173 GUEST_IA32_DEBUGCTL = 0x00002802, 174 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 175 GUEST_IA32_PAT = 0x00002804, 176 GUEST_IA32_PAT_HIGH = 0x00002805, 177 GUEST_IA32_EFER = 0x00002806, 178 GUEST_IA32_EFER_HIGH = 0x00002807, 179 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 180 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 181 GUEST_PDPTR0 = 0x0000280a, 182 GUEST_PDPTR0_HIGH = 0x0000280b, 183 GUEST_PDPTR1 = 0x0000280c, 184 GUEST_PDPTR1_HIGH = 0x0000280d, 185 GUEST_PDPTR2 = 0x0000280e, 186 GUEST_PDPTR2_HIGH = 0x0000280f, 187 GUEST_PDPTR3 = 0x00002810, 188 GUEST_PDPTR3_HIGH = 0x00002811, 189 GUEST_BNDCFGS = 0x00002812, 190 GUEST_BNDCFGS_HIGH = 0x00002813, 191 HOST_IA32_PAT = 0x00002c00, 192 HOST_IA32_PAT_HIGH = 0x00002c01, 193 HOST_IA32_EFER = 0x00002c02, 194 HOST_IA32_EFER_HIGH = 0x00002c03, 195 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 196 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 197 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 198 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 199 EXCEPTION_BITMAP = 0x00004004, 200 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 201 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 202 CR3_TARGET_COUNT = 0x0000400a, 203 VM_EXIT_CONTROLS = 0x0000400c, 204 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 205 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 206 VM_ENTRY_CONTROLS = 0x00004012, 207 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 208 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 209 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 210 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 211 TPR_THRESHOLD = 0x0000401c, 212 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 213 PLE_GAP = 0x00004020, 214 PLE_WINDOW = 0x00004022, 215 VM_INSTRUCTION_ERROR = 0x00004400, 216 VM_EXIT_REASON = 0x00004402, 217 VM_EXIT_INTR_INFO = 0x00004404, 218 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 219 IDT_VECTORING_INFO_FIELD = 0x00004408, 220 IDT_VECTORING_ERROR_CODE = 0x0000440a, 221 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 222 VMX_INSTRUCTION_INFO = 0x0000440e, 223 GUEST_ES_LIMIT = 0x00004800, 224 GUEST_CS_LIMIT = 0x00004802, 225 GUEST_SS_LIMIT = 0x00004804, 226 GUEST_DS_LIMIT = 0x00004806, 227 GUEST_FS_LIMIT = 0x00004808, 228 GUEST_GS_LIMIT = 0x0000480a, 229 GUEST_LDTR_LIMIT = 0x0000480c, 230 GUEST_TR_LIMIT = 0x0000480e, 231 GUEST_GDTR_LIMIT = 0x00004810, 232 GUEST_IDTR_LIMIT = 0x00004812, 233 GUEST_ES_AR_BYTES = 0x00004814, 234 GUEST_CS_AR_BYTES = 0x00004816, 235 GUEST_SS_AR_BYTES = 0x00004818, 236 GUEST_DS_AR_BYTES = 0x0000481a, 237 GUEST_FS_AR_BYTES = 0x0000481c, 238 GUEST_GS_AR_BYTES = 0x0000481e, 239 GUEST_LDTR_AR_BYTES = 0x00004820, 240 GUEST_TR_AR_BYTES = 0x00004822, 241 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 242 GUEST_ACTIVITY_STATE = 0X00004826, 243 GUEST_SYSENTER_CS = 0x0000482A, 244 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 245 HOST_IA32_SYSENTER_CS = 0x00004c00, 246 CR0_GUEST_HOST_MASK = 0x00006000, 247 CR4_GUEST_HOST_MASK = 0x00006002, 248 CR0_READ_SHADOW = 0x00006004, 249 CR4_READ_SHADOW = 0x00006006, 250 CR3_TARGET_VALUE0 = 0x00006008, 251 CR3_TARGET_VALUE1 = 0x0000600a, 252 CR3_TARGET_VALUE2 = 0x0000600c, 253 CR3_TARGET_VALUE3 = 0x0000600e, 254 EXIT_QUALIFICATION = 0x00006400, 255 GUEST_LINEAR_ADDRESS = 0x0000640a, 256 GUEST_CR0 = 0x00006800, 257 GUEST_CR3 = 0x00006802, 258 GUEST_CR4 = 0x00006804, 259 GUEST_ES_BASE = 0x00006806, 260 GUEST_CS_BASE = 0x00006808, 261 GUEST_SS_BASE = 0x0000680a, 262 GUEST_DS_BASE = 0x0000680c, 263 GUEST_FS_BASE = 0x0000680e, 264 GUEST_GS_BASE = 0x00006810, 265 GUEST_LDTR_BASE = 0x00006812, 266 GUEST_TR_BASE = 0x00006814, 267 GUEST_GDTR_BASE = 0x00006816, 268 GUEST_IDTR_BASE = 0x00006818, 269 GUEST_DR7 = 0x0000681a, 270 GUEST_RSP = 0x0000681c, 271 GUEST_RIP = 0x0000681e, 272 GUEST_RFLAGS = 0x00006820, 273 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 274 GUEST_SYSENTER_ESP = 0x00006824, 275 GUEST_SYSENTER_EIP = 0x00006826, 276 HOST_CR0 = 0x00006c00, 277 HOST_CR3 = 0x00006c02, 278 HOST_CR4 = 0x00006c04, 279 HOST_FS_BASE = 0x00006c06, 280 HOST_GS_BASE = 0x00006c08, 281 HOST_TR_BASE = 0x00006c0a, 282 HOST_GDTR_BASE = 0x00006c0c, 283 HOST_IDTR_BASE = 0x00006c0e, 284 HOST_IA32_SYSENTER_ESP = 0x00006c10, 285 HOST_IA32_SYSENTER_EIP = 0x00006c12, 286 HOST_RSP = 0x00006c14, 287 HOST_RIP = 0x00006c16, 288}; 289 290/* 291 * Interruption-information format 292 */ 293#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 294#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 295#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 296#define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ 297#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 298#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 299 300#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK 301#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK 302#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK 303#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK 304 305#define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 306#define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 307#define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 308#define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 309#define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 310 311/* GUEST_INTERRUPTIBILITY_INFO flags. */ 312#define GUEST_INTR_STATE_STI 0x00000001 313#define GUEST_INTR_STATE_MOV_SS 0x00000002 314#define GUEST_INTR_STATE_SMI 0x00000004 315#define GUEST_INTR_STATE_NMI 0x00000008 316 317/* GUEST_ACTIVITY_STATE flags */ 318#define GUEST_ACTIVITY_ACTIVE 0 319#define GUEST_ACTIVITY_HLT 1 320#define GUEST_ACTIVITY_SHUTDOWN 2 321#define GUEST_ACTIVITY_WAIT_SIPI 3 322 323/* 324 * Exit Qualifications for MOV for Control Register Access 325 */ 326#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/ 327#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */ 328#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */ 329#define LMSW_SOURCE_DATA_SHIFT 16 330#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */ 331#define REG_EAX (0 << 8) 332#define REG_ECX (1 << 8) 333#define REG_EDX (2 << 8) 334#define REG_EBX (3 << 8) 335#define REG_ESP (4 << 8) 336#define REG_EBP (5 << 8) 337#define REG_ESI (6 << 8) 338#define REG_EDI (7 << 8) 339#define REG_R8 (8 << 8) 340#define REG_R9 (9 << 8) 341#define REG_R10 (10 << 8) 342#define REG_R11 (11 << 8) 343#define REG_R12 (12 << 8) 344#define REG_R13 (13 << 8) 345#define REG_R14 (14 << 8) 346#define REG_R15 (15 << 8) 347 348/* 349 * Exit Qualifications for MOV for Debug Register Access 350 */ 351#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */ 352#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */ 353#define TYPE_MOV_TO_DR (0 << 4) 354#define TYPE_MOV_FROM_DR (1 << 4) 355#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */ 356 357 358/* 359 * Exit Qualifications for APIC-Access 360 */ 361#define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */ 362#define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */ 363#define TYPE_LINEAR_APIC_INST_READ (0 << 12) 364#define TYPE_LINEAR_APIC_INST_WRITE (1 << 12) 365#define TYPE_LINEAR_APIC_INST_FETCH (2 << 12) 366#define TYPE_LINEAR_APIC_EVENT (3 << 12) 367#define TYPE_PHYSICAL_APIC_EVENT (10 << 12) 368#define TYPE_PHYSICAL_APIC_INST (15 << 12) 369 370/* segment AR */ 371#define SEGMENT_AR_L_MASK (1 << 13) 372 373#define AR_TYPE_ACCESSES_MASK 1 374#define AR_TYPE_READABLE_MASK (1 << 1) 375#define AR_TYPE_WRITEABLE_MASK (1 << 2) 376#define AR_TYPE_CODE_MASK (1 << 3) 377#define AR_TYPE_MASK 0x0f 378#define AR_TYPE_BUSY_64_TSS 11 379#define AR_TYPE_BUSY_32_TSS 11 380#define AR_TYPE_BUSY_16_TSS 3 381#define AR_TYPE_LDT 2 382 383#define AR_UNUSABLE_MASK (1 << 16) 384#define AR_S_MASK (1 << 4) 385#define AR_P_MASK (1 << 7) 386#define AR_L_MASK (1 << 13) 387#define AR_DB_MASK (1 << 14) 388#define AR_G_MASK (1 << 15) 389#define AR_DPL_SHIFT 5 390#define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3) 391 392#define AR_RESERVD_MASK 0xfffe0f00 393 394#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0) 395#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1) 396#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2) 397 398#define VMX_NR_VPIDS (1 << 16) 399#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 400#define VMX_VPID_EXTENT_ALL_CONTEXT 2 401 402#define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0 403#define VMX_EPT_EXTENT_CONTEXT 1 404#define VMX_EPT_EXTENT_GLOBAL 2 405#define VMX_EPT_EXTENT_SHIFT 24 406 407#define VMX_EPT_EXECUTE_ONLY_BIT (1ull) 408#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6) 409#define VMX_EPTP_UC_BIT (1ull << 8) 410#define VMX_EPTP_WB_BIT (1ull << 14) 411#define VMX_EPT_2MB_PAGE_BIT (1ull << 16) 412#define VMX_EPT_1GB_PAGE_BIT (1ull << 17) 413#define VMX_EPT_INVEPT_BIT (1ull << 20) 414#define VMX_EPT_AD_BIT (1ull << 21) 415#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) 416#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) 417 418#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */ 419#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */ 420 421#define VMX_EPT_DEFAULT_GAW 3 422#define VMX_EPT_MAX_GAW 0x4 423#define VMX_EPT_MT_EPTE_SHIFT 3 424#define VMX_EPT_GAW_EPTP_SHIFT 3 425#define VMX_EPT_AD_ENABLE_BIT (1ull << 6) 426#define VMX_EPT_DEFAULT_MT 0x6ull 427#define VMX_EPT_READABLE_MASK 0x1ull 428#define VMX_EPT_WRITABLE_MASK 0x2ull 429#define VMX_EPT_EXECUTABLE_MASK 0x4ull 430#define VMX_EPT_IPAT_BIT (1ull << 6) 431#define VMX_EPT_ACCESS_BIT (1ull << 8) 432#define VMX_EPT_DIRTY_BIT (1ull << 9) 433 434#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul 435 436 437#define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30" 438#define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2" 439#define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3" 440#define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30" 441#define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0" 442#define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0" 443#define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4" 444#define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4" 445#define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30" 446#define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08" 447#define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" 448 449struct vmx_msr_entry { 450 u32 index; 451 u32 reserved; 452 u64 value; 453} __aligned(16); 454 455/* 456 * Exit Qualifications for entry failure during or after loading guest state 457 */ 458#define ENTRY_FAIL_DEFAULT 0 459#define ENTRY_FAIL_PDPTE 2 460#define ENTRY_FAIL_NMI 3 461#define ENTRY_FAIL_VMCS_LINK_PTR 4 462 463/* 464 * VM-instruction error numbers 465 */ 466enum vm_instruction_error_number { 467 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 468 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 469 VMXERR_VMCLEAR_VMXON_POINTER = 3, 470 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 471 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 472 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 473 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 474 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 475 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 476 VMXERR_VMPTRLD_VMXON_POINTER = 10, 477 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 478 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 479 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 480 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 481 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 482 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 483 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 484 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 485 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 486 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 487 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 488 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 489 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 490 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 491 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 492}; 493 494#endif 495