1/******************************************************************************
2 * arch-x86_32.h
3 *
4 * Guest OS interface to x86 Xen.
5 *
6 * Copyright (c) 2004, K A Fraser
7 */
8
9#ifndef _ASM_X86_XEN_INTERFACE_H
10#define _ASM_X86_XEN_INTERFACE_H
11
12#ifdef __XEN__
13#define __DEFINE_GUEST_HANDLE(name, type) \
14    typedef struct { type *p; } __guest_handle_ ## name
15#else
16#define __DEFINE_GUEST_HANDLE(name, type) \
17    typedef type * __guest_handle_ ## name
18#endif
19
20#define DEFINE_GUEST_HANDLE_STRUCT(name) \
21	__DEFINE_GUEST_HANDLE(name, struct name)
22#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
23#define GUEST_HANDLE(name)        __guest_handle_ ## name
24
25#ifdef __XEN__
26#if defined(__i386__)
27#define set_xen_guest_handle(hnd, val)			\
28	do {						\
29		if (sizeof(hnd) == 8)			\
30			*(uint64_t *)&(hnd) = 0;	\
31		(hnd).p = val;				\
32	} while (0)
33#elif defined(__x86_64__)
34#define set_xen_guest_handle(hnd, val)	do { (hnd).p = val; } while (0)
35#endif
36#else
37#if defined(__i386__)
38#define set_xen_guest_handle(hnd, val)			\
39	do {						\
40		if (sizeof(hnd) == 8)			\
41			*(uint64_t *)&(hnd) = 0;	\
42		(hnd) = val;				\
43	} while (0)
44#elif defined(__x86_64__)
45#define set_xen_guest_handle(hnd, val)	do { (hnd) = val; } while (0)
46#endif
47#endif
48
49#ifndef __ASSEMBLY__
50/* Explicitly size integers that represent pfns in the public interface
51 * with Xen so that on ARM we can have one ABI that works for 32 and 64
52 * bit guests. */
53typedef unsigned long xen_pfn_t;
54#define PRI_xen_pfn "lx"
55typedef unsigned long xen_ulong_t;
56#define PRI_xen_ulong "lx"
57typedef long xen_long_t;
58#define PRI_xen_long "lx"
59
60/* Guest handles for primitive C types. */
61__DEFINE_GUEST_HANDLE(uchar, unsigned char);
62__DEFINE_GUEST_HANDLE(uint,  unsigned int);
63DEFINE_GUEST_HANDLE(char);
64DEFINE_GUEST_HANDLE(int);
65DEFINE_GUEST_HANDLE(void);
66DEFINE_GUEST_HANDLE(uint64_t);
67DEFINE_GUEST_HANDLE(uint32_t);
68DEFINE_GUEST_HANDLE(xen_pfn_t);
69DEFINE_GUEST_HANDLE(xen_ulong_t);
70#endif
71
72#ifndef HYPERVISOR_VIRT_START
73#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
74#endif
75
76#define MACH2PHYS_VIRT_START  mk_unsigned_long(__MACH2PHYS_VIRT_START)
77#define MACH2PHYS_VIRT_END    mk_unsigned_long(__MACH2PHYS_VIRT_END)
78#define MACH2PHYS_NR_ENTRIES  ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
79
80/* Maximum number of virtual CPUs in multi-processor guests. */
81#define MAX_VIRT_CPUS 32
82
83/*
84 * SEGMENT DESCRIPTOR TABLES
85 */
86/*
87 * A number of GDT entries are reserved by Xen. These are not situated at the
88 * start of the GDT because some stupid OSes export hard-coded selector values
89 * in their ABI. These hard-coded values are always near the start of the GDT,
90 * so Xen places itself out of the way, at the far end of the GDT.
91 */
92#define FIRST_RESERVED_GDT_PAGE  14
93#define FIRST_RESERVED_GDT_BYTE  (FIRST_RESERVED_GDT_PAGE * 4096)
94#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
95
96/*
97 * Send an array of these to HYPERVISOR_set_trap_table()
98 * The privilege level specifies which modes may enter a trap via a software
99 * interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate
100 * privilege levels as follows:
101 *  Level == 0: No one may enter
102 *  Level == 1: Kernel may enter
103 *  Level == 2: Kernel may enter
104 *  Level == 3: Everyone may enter
105 */
106#define TI_GET_DPL(_ti)		((_ti)->flags & 3)
107#define TI_GET_IF(_ti)		((_ti)->flags & 4)
108#define TI_SET_DPL(_ti, _dpl)	((_ti)->flags |= (_dpl))
109#define TI_SET_IF(_ti, _if)	((_ti)->flags |= ((!!(_if))<<2))
110
111#ifndef __ASSEMBLY__
112struct trap_info {
113    uint8_t       vector;  /* exception vector                              */
114    uint8_t       flags;   /* 0-3: privilege level; 4: clear event enable?  */
115    uint16_t      cs;      /* code selector                                 */
116    unsigned long address; /* code offset                                   */
117};
118DEFINE_GUEST_HANDLE_STRUCT(trap_info);
119
120struct arch_shared_info {
121    unsigned long max_pfn;                  /* max pfn that appears in table */
122    /* Frame containing list of mfns containing list of mfns containing p2m. */
123    unsigned long pfn_to_mfn_frame_list_list;
124    unsigned long nmi_reason;
125};
126#endif	/* !__ASSEMBLY__ */
127
128#ifdef CONFIG_X86_32
129#include <asm/xen/interface_32.h>
130#else
131#include <asm/xen/interface_64.h>
132#endif
133
134#include <asm/pvclock-abi.h>
135
136#ifndef __ASSEMBLY__
137/*
138 * The following is all CPU context. Note that the fpu_ctxt block is filled
139 * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
140 */
141struct vcpu_guest_context {
142    /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
143    struct { char x[512]; } fpu_ctxt;       /* User-level FPU registers     */
144#define VGCF_I387_VALID (1<<0)
145#define VGCF_HVM_GUEST  (1<<1)
146#define VGCF_IN_KERNEL  (1<<2)
147    unsigned long flags;                    /* VGCF_* flags                 */
148    struct cpu_user_regs user_regs;         /* User-level CPU registers     */
149    struct trap_info trap_ctxt[256];        /* Virtual IDT                  */
150    unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
151    unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
152    unsigned long kernel_ss, kernel_sp;     /* Virtual TSS (only SS1/SP1)   */
153    /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */
154    unsigned long ctrlreg[8];               /* CR0-CR7 (control registers)  */
155    unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
156#ifdef __i386__
157    unsigned long event_callback_cs;        /* CS:EIP of event callback     */
158    unsigned long event_callback_eip;
159    unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
160    unsigned long failsafe_callback_eip;
161#else
162    unsigned long event_callback_eip;
163    unsigned long failsafe_callback_eip;
164    unsigned long syscall_callback_eip;
165#endif
166    unsigned long vm_assist;                /* VMASST_TYPE_* bitmap */
167#ifdef __x86_64__
168    /* Segment base addresses. */
169    uint64_t      fs_base;
170    uint64_t      gs_base_kernel;
171    uint64_t      gs_base_user;
172#endif
173};
174DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
175#endif	/* !__ASSEMBLY__ */
176
177/*
178 * Prefix forces emulation of some non-trapping instructions.
179 * Currently only CPUID.
180 */
181#ifdef __ASSEMBLY__
182#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ;
183#define XEN_CPUID          XEN_EMULATE_PREFIX cpuid
184#else
185#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; "
186#define XEN_CPUID          XEN_EMULATE_PREFIX "cpuid"
187#endif
188
189#endif /* _ASM_X86_XEN_INTERFACE_H */
190