1/*
2 * Suspend support specific for i386/x86-64.
3 *
4 * Distribute under GPLv2
5 *
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
9 */
10
11#include <linux/suspend.h>
12#include <linux/export.h>
13#include <linux/smp.h>
14#include <linux/perf_event.h>
15
16#include <asm/pgtable.h>
17#include <asm/proto.h>
18#include <asm/mtrr.h>
19#include <asm/page.h>
20#include <asm/mce.h>
21#include <asm/xcr.h>
22#include <asm/suspend.h>
23#include <asm/debugreg.h>
24#include <asm/fpu-internal.h> /* pcntxt_mask */
25#include <asm/cpu.h>
26#include <asm/mmu_context.h>
27
28#ifdef CONFIG_X86_32
29__visible unsigned long saved_context_ebx;
30__visible unsigned long saved_context_esp, saved_context_ebp;
31__visible unsigned long saved_context_esi, saved_context_edi;
32__visible unsigned long saved_context_eflags;
33#endif
34struct saved_context saved_context;
35
36/**
37 *	__save_processor_state - save CPU registers before creating a
38 *		hibernation image and before restoring the memory state from it
39 *	@ctxt - structure to store the registers contents in
40 *
41 *	NOTE: If there is a CPU register the modification of which by the
42 *	boot kernel (ie. the kernel used for loading the hibernation image)
43 *	might affect the operations of the restored target kernel (ie. the one
44 *	saved in the hibernation image), then its contents must be saved by this
45 *	function.  In other words, if kernel A is hibernated and different
46 *	kernel B is used for loading the hibernation image into memory, the
47 *	kernel A's __save_processor_state() function must save all registers
48 *	needed by kernel A, so that it can operate correctly after the resume
49 *	regardless of what kernel B does in the meantime.
50 */
51static void __save_processor_state(struct saved_context *ctxt)
52{
53#ifdef CONFIG_X86_32
54	mtrr_save_fixed_ranges(NULL);
55#endif
56	kernel_fpu_begin();
57
58	/*
59	 * descriptor tables
60	 */
61#ifdef CONFIG_X86_32
62	store_idt(&ctxt->idt);
63#else
64/* CONFIG_X86_64 */
65	store_idt((struct desc_ptr *)&ctxt->idt_limit);
66#endif
67	/*
68	 * We save it here, but restore it only in the hibernate case.
69	 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
70	 * mode in "secondary_startup_64". In 32-bit mode it is done via
71	 * 'pmode_gdt' in wakeup_start.
72	 */
73	ctxt->gdt_desc.size = GDT_SIZE - 1;
74	ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
75
76	store_tr(ctxt->tr);
77
78	/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
79	/*
80	 * segment registers
81	 */
82#ifdef CONFIG_X86_32
83	savesegment(es, ctxt->es);
84	savesegment(fs, ctxt->fs);
85	savesegment(gs, ctxt->gs);
86	savesegment(ss, ctxt->ss);
87#else
88/* CONFIG_X86_64 */
89	asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
90	asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
91	asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
92	asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
93	asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
94
95	rdmsrl(MSR_FS_BASE, ctxt->fs_base);
96	rdmsrl(MSR_GS_BASE, ctxt->gs_base);
97	rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
98	mtrr_save_fixed_ranges(NULL);
99
100	rdmsrl(MSR_EFER, ctxt->efer);
101#endif
102
103	/*
104	 * control registers
105	 */
106	ctxt->cr0 = read_cr0();
107	ctxt->cr2 = read_cr2();
108	ctxt->cr3 = read_cr3();
109	ctxt->cr4 = __read_cr4_safe();
110#ifdef CONFIG_X86_64
111	ctxt->cr8 = read_cr8();
112#endif
113	ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
114					       &ctxt->misc_enable);
115}
116
117/* Needed by apm.c */
118void save_processor_state(void)
119{
120	__save_processor_state(&saved_context);
121	x86_platform.save_sched_clock_state();
122}
123#ifdef CONFIG_X86_32
124EXPORT_SYMBOL(save_processor_state);
125#endif
126
127static void do_fpu_end(void)
128{
129	/*
130	 * Restore FPU regs if necessary.
131	 */
132	kernel_fpu_end();
133}
134
135static void fix_processor_context(void)
136{
137	int cpu = smp_processor_id();
138	struct tss_struct *t = &per_cpu(cpu_tss, cpu);
139#ifdef CONFIG_X86_64
140	struct desc_struct *desc = get_cpu_gdt_table(cpu);
141	tss_desc tss;
142#endif
143	set_tss_desc(cpu, t);	/*
144				 * This just modifies memory; should not be
145				 * necessary. But... This is necessary, because
146				 * 386 hardware has concept of busy TSS or some
147				 * similar stupidity.
148				 */
149
150#ifdef CONFIG_X86_64
151	memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
152	tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
153	write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
154
155	syscall_init();				/* This sets MSR_*STAR and related */
156#endif
157	load_TR_desc();				/* This does ltr */
158	load_mm_ldt(current->active_mm);	/* This does lldt */
159}
160
161/**
162 *	__restore_processor_state - restore the contents of CPU registers saved
163 *		by __save_processor_state()
164 *	@ctxt - structure to load the registers contents from
165 */
166static void notrace __restore_processor_state(struct saved_context *ctxt)
167{
168	if (ctxt->misc_enable_saved)
169		wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
170	/*
171	 * control registers
172	 */
173	/* cr4 was introduced in the Pentium CPU */
174#ifdef CONFIG_X86_32
175	if (ctxt->cr4)
176		__write_cr4(ctxt->cr4);
177#else
178/* CONFIG X86_64 */
179	wrmsrl(MSR_EFER, ctxt->efer);
180	write_cr8(ctxt->cr8);
181	__write_cr4(ctxt->cr4);
182#endif
183	write_cr3(ctxt->cr3);
184	write_cr2(ctxt->cr2);
185	write_cr0(ctxt->cr0);
186
187	/*
188	 * now restore the descriptor tables to their proper values
189	 * ltr is done i fix_processor_context().
190	 */
191#ifdef CONFIG_X86_32
192	load_idt(&ctxt->idt);
193#else
194/* CONFIG_X86_64 */
195	load_idt((const struct desc_ptr *)&ctxt->idt_limit);
196#endif
197
198	/*
199	 * segment registers
200	 */
201#ifdef CONFIG_X86_32
202	loadsegment(es, ctxt->es);
203	loadsegment(fs, ctxt->fs);
204	loadsegment(gs, ctxt->gs);
205	loadsegment(ss, ctxt->ss);
206
207	/*
208	 * sysenter MSRs
209	 */
210	if (boot_cpu_has(X86_FEATURE_SEP))
211		enable_sep_cpu();
212#else
213/* CONFIG_X86_64 */
214	asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
215	asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
216	asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
217	load_gs_index(ctxt->gs);
218	asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
219
220	wrmsrl(MSR_FS_BASE, ctxt->fs_base);
221	wrmsrl(MSR_GS_BASE, ctxt->gs_base);
222	wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
223#endif
224
225	/*
226	 * restore XCR0 for xsave capable cpu's.
227	 */
228	if (cpu_has_xsave)
229		xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
230
231	fix_processor_context();
232
233	do_fpu_end();
234	x86_platform.restore_sched_clock_state();
235	mtrr_bp_restore();
236	perf_restore_debug_store();
237}
238
239/* Needed by apm.c */
240void notrace restore_processor_state(void)
241{
242	__restore_processor_state(&saved_context);
243}
244#ifdef CONFIG_X86_32
245EXPORT_SYMBOL(restore_processor_state);
246#endif
247
248/*
249 * When bsp_check() is called in hibernate and suspend, cpu hotplug
250 * is disabled already. So it's unnessary to handle race condition between
251 * cpumask query and cpu hotplug.
252 */
253static int bsp_check(void)
254{
255	if (cpumask_first(cpu_online_mask) != 0) {
256		pr_warn("CPU0 is offline.\n");
257		return -ENODEV;
258	}
259
260	return 0;
261}
262
263static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
264			   void *ptr)
265{
266	int ret = 0;
267
268	switch (action) {
269	case PM_SUSPEND_PREPARE:
270	case PM_HIBERNATION_PREPARE:
271		ret = bsp_check();
272		break;
273#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
274	case PM_RESTORE_PREPARE:
275		/*
276		 * When system resumes from hibernation, online CPU0 because
277		 * 1. it's required for resume and
278		 * 2. the CPU was online before hibernation
279		 */
280		if (!cpu_online(0))
281			_debug_hotplug_cpu(0, 1);
282		break;
283	case PM_POST_RESTORE:
284		/*
285		 * When a resume really happens, this code won't be called.
286		 *
287		 * This code is called only when user space hibernation software
288		 * prepares for snapshot device during boot time. So we just
289		 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
290		 * preparing the snapshot device.
291		 *
292		 * This works for normal boot case in our CPU0 hotplug debug
293		 * mode, i.e. CPU0 is offline and user mode hibernation
294		 * software initializes during boot time.
295		 *
296		 * If CPU0 is online and user application accesses snapshot
297		 * device after boot time, this will offline CPU0 and user may
298		 * see different CPU0 state before and after accessing
299		 * the snapshot device. But hopefully this is not a case when
300		 * user debugging CPU0 hotplug. Even if users hit this case,
301		 * they can easily online CPU0 back.
302		 *
303		 * To simplify this debug code, we only consider normal boot
304		 * case. Otherwise we need to remember CPU0's state and restore
305		 * to that state and resolve racy conditions etc.
306		 */
307		_debug_hotplug_cpu(0, 0);
308		break;
309#endif
310	default:
311		break;
312	}
313	return notifier_from_errno(ret);
314}
315
316static int __init bsp_pm_check_init(void)
317{
318	/*
319	 * Set this bsp_pm_callback as lower priority than
320	 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
321	 * earlier to disable cpu hotplug before bsp online check.
322	 */
323	pm_notifier(bsp_pm_callback, -INT_MAX);
324	return 0;
325}
326
327core_initcall(bsp_pm_check_init);
328