1/* 2 * pata_sil680.c - SIL680 PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * 5 * based upon 6 * 7 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003 8 * 9 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org> 10 * Copyright (C) 2003 Red Hat <alan@redhat.com> 11 * 12 * May be copied or modified under the terms of the GNU General Public License 13 * 14 * Documentation publicly available. 15 * 16 * If you have strange problems with nVidia chipset systems please 17 * see the SI support documentation and update your system BIOS 18 * if necessary 19 * 20 * TODO 21 * If we know all our devices are LBA28 (or LBA28 sized) we could use 22 * the command fifo mode. 23 */ 24 25#include <linux/kernel.h> 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/blkdev.h> 29#include <linux/delay.h> 30#include <scsi/scsi_host.h> 31#include <linux/libata.h> 32 33#define DRV_NAME "pata_sil680" 34#define DRV_VERSION "0.4.9" 35 36#define SIL680_MMIO_BAR 5 37 38/** 39 * sil680_selreg - return register base 40 * @ap: ATA interface 41 * @r: config offset 42 * 43 * Turn a config register offset into the right address in PCI space 44 * to access the control register in question. 45 * 46 * Thankfully this is a configuration operation so isn't performance 47 * criticial. 48 */ 49 50static unsigned long sil680_selreg(struct ata_port *ap, int r) 51{ 52 unsigned long base = 0xA0 + r; 53 base += (ap->port_no << 4); 54 return base; 55} 56 57/** 58 * sil680_seldev - return register base 59 * @ap: ATA interface 60 * @r: config offset 61 * 62 * Turn a config register offset into the right address in PCI space 63 * to access the control register in question including accounting for 64 * the unit shift. 65 */ 66 67static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r) 68{ 69 unsigned long base = 0xA0 + r; 70 base += (ap->port_no << 4); 71 base |= adev->devno ? 2 : 0; 72 return base; 73} 74 75 76/** 77 * sil680_cable_detect - cable detection 78 * @ap: ATA port 79 * 80 * Perform cable detection. The SIL680 stores this in PCI config 81 * space for us. 82 */ 83 84static int sil680_cable_detect(struct ata_port *ap) 85{ 86 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 87 unsigned long addr = sil680_selreg(ap, 0); 88 u8 ata66; 89 pci_read_config_byte(pdev, addr, &ata66); 90 if (ata66 & 1) 91 return ATA_CBL_PATA80; 92 else 93 return ATA_CBL_PATA40; 94} 95 96/** 97 * sil680_set_piomode - set PIO mode data 98 * @ap: ATA interface 99 * @adev: ATA device 100 * 101 * Program the SIL680 registers for PIO mode. Note that the task speed 102 * registers are shared between the devices so we must pick the lowest 103 * mode for command work. 104 */ 105 106static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev) 107{ 108 static const u16 speed_p[5] = { 109 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 110 }; 111 static const u16 speed_t[5] = { 112 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 113 }; 114 115 unsigned long tfaddr = sil680_selreg(ap, 0x02); 116 unsigned long addr = sil680_seldev(ap, adev, 0x04); 117 unsigned long addr_mask = 0x80 + 4 * ap->port_no; 118 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 119 int pio = adev->pio_mode - XFER_PIO_0; 120 int lowest_pio = pio; 121 int port_shift = 4 * adev->devno; 122 u16 reg; 123 u8 mode; 124 125 struct ata_device *pair = ata_dev_pair(adev); 126 127 if (pair != NULL && adev->pio_mode > pair->pio_mode) 128 lowest_pio = pair->pio_mode - XFER_PIO_0; 129 130 pci_write_config_word(pdev, addr, speed_p[pio]); 131 pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]); 132 133 pci_read_config_word(pdev, tfaddr-2, ®); 134 pci_read_config_byte(pdev, addr_mask, &mode); 135 136 reg &= ~0x0200; /* Clear IORDY */ 137 mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */ 138 139 if (ata_pio_need_iordy(adev)) { 140 reg |= 0x0200; /* Enable IORDY */ 141 mode |= 1 << port_shift; 142 } 143 pci_write_config_word(pdev, tfaddr-2, reg); 144 pci_write_config_byte(pdev, addr_mask, mode); 145} 146 147/** 148 * sil680_set_dmamode - set DMA mode data 149 * @ap: ATA interface 150 * @adev: ATA device 151 * 152 * Program the MWDMA/UDMA modes for the sil680 chipset. 153 * 154 * The MWDMA mode values are pulled from a lookup table 155 * while the chipset uses mode number for UDMA. 156 */ 157 158static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev) 159{ 160 static const u8 ultra_table[2][7] = { 161 { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */ 162 { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */ 163 }; 164 static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 }; 165 166 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 167 unsigned long ma = sil680_seldev(ap, adev, 0x08); 168 unsigned long ua = sil680_seldev(ap, adev, 0x0C); 169 unsigned long addr_mask = 0x80 + 4 * ap->port_no; 170 int port_shift = adev->devno * 4; 171 u8 scsc, mode; 172 u16 multi, ultra; 173 174 pci_read_config_byte(pdev, 0x8A, &scsc); 175 pci_read_config_byte(pdev, addr_mask, &mode); 176 pci_read_config_word(pdev, ma, &multi); 177 pci_read_config_word(pdev, ua, &ultra); 178 179 /* Mask timing bits */ 180 ultra &= ~0x3F; 181 mode &= ~(0x03 << port_shift); 182 183 /* Extract scsc */ 184 scsc = (scsc & 0x30) ? 1 : 0; 185 186 if (adev->dma_mode >= XFER_UDMA_0) { 187 multi = 0x10C1; 188 ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0]; 189 mode |= (0x03 << port_shift); 190 } else { 191 multi = dma_table[adev->dma_mode - XFER_MW_DMA_0]; 192 mode |= (0x02 << port_shift); 193 } 194 pci_write_config_byte(pdev, addr_mask, mode); 195 pci_write_config_word(pdev, ma, multi); 196 pci_write_config_word(pdev, ua, ultra); 197} 198 199/** 200 * sil680_sff_exec_command - issue ATA command to host controller 201 * @ap: port to which command is being issued 202 * @tf: ATA taskfile register set 203 * 204 * Issues ATA command, with proper synchronization with interrupt 205 * handler / other threads. Use our MMIO space for PCI posting to avoid 206 * a hideously slow cycle all the way to the device. 207 * 208 * LOCKING: 209 * spin_lock_irqsave(host lock) 210 */ 211static void sil680_sff_exec_command(struct ata_port *ap, 212 const struct ata_taskfile *tf) 213{ 214 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 215 iowrite8(tf->command, ap->ioaddr.command_addr); 216 ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD); 217} 218 219static bool sil680_sff_irq_check(struct ata_port *ap) 220{ 221 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 222 unsigned long addr = sil680_selreg(ap, 1); 223 u8 val; 224 225 pci_read_config_byte(pdev, addr, &val); 226 227 return val & 0x08; 228} 229 230static struct scsi_host_template sil680_sht = { 231 ATA_BMDMA_SHT(DRV_NAME), 232}; 233 234 235static struct ata_port_operations sil680_port_ops = { 236 .inherits = &ata_bmdma32_port_ops, 237 .sff_exec_command = sil680_sff_exec_command, 238 .sff_irq_check = sil680_sff_irq_check, 239 .cable_detect = sil680_cable_detect, 240 .set_piomode = sil680_set_piomode, 241 .set_dmamode = sil680_set_dmamode, 242}; 243 244/** 245 * sil680_init_chip - chip setup 246 * @pdev: PCI device 247 * 248 * Perform all the chip setup which must be done both when the device 249 * is powered up on boot and when we resume in case we resumed from RAM. 250 * Returns the final clock settings. 251 */ 252 253static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio) 254{ 255 u8 tmpbyte = 0; 256 257 /* FIXME: double check */ 258 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 259 pdev->revision ? 1 : 255); 260 261 pci_write_config_byte(pdev, 0x80, 0x00); 262 pci_write_config_byte(pdev, 0x84, 0x00); 263 264 pci_read_config_byte(pdev, 0x8A, &tmpbyte); 265 266 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", 267 tmpbyte & 1, tmpbyte & 0x30); 268 269 *try_mmio = 0; 270#ifdef CONFIG_PPC 271 if (machine_is(cell)) 272 *try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5); 273#endif 274 275 switch (tmpbyte & 0x30) { 276 case 0x00: 277 /* 133 clock attempt to force it on */ 278 pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10); 279 break; 280 case 0x30: 281 /* if clocking is disabled */ 282 /* 133 clock attempt to force it on */ 283 pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20); 284 break; 285 case 0x10: 286 /* 133 already */ 287 break; 288 case 0x20: 289 /* BIOS set PCI x2 clocking */ 290 break; 291 } 292 293 pci_read_config_byte(pdev, 0x8A, &tmpbyte); 294 dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n", 295 tmpbyte & 1, tmpbyte & 0x30); 296 297 pci_write_config_byte(pdev, 0xA1, 0x72); 298 pci_write_config_word(pdev, 0xA2, 0x328A); 299 pci_write_config_dword(pdev, 0xA4, 0x62DD62DD); 300 pci_write_config_dword(pdev, 0xA8, 0x43924392); 301 pci_write_config_dword(pdev, 0xAC, 0x40094009); 302 pci_write_config_byte(pdev, 0xB1, 0x72); 303 pci_write_config_word(pdev, 0xB2, 0x328A); 304 pci_write_config_dword(pdev, 0xB4, 0x62DD62DD); 305 pci_write_config_dword(pdev, 0xB8, 0x43924392); 306 pci_write_config_dword(pdev, 0xBC, 0x40094009); 307 308 switch (tmpbyte & 0x30) { 309 case 0x00: 310 printk(KERN_INFO "sil680: 100MHz clock.\n"); 311 break; 312 case 0x10: 313 printk(KERN_INFO "sil680: 133MHz clock.\n"); 314 break; 315 case 0x20: 316 printk(KERN_INFO "sil680: Using PCI clock.\n"); 317 break; 318 /* This last case is _NOT_ ok */ 319 case 0x30: 320 printk(KERN_ERR "sil680: Clock disabled ?\n"); 321 } 322 return tmpbyte & 0x30; 323} 324 325static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 326{ 327 static const struct ata_port_info info = { 328 .flags = ATA_FLAG_SLAVE_POSS, 329 .pio_mask = ATA_PIO4, 330 .mwdma_mask = ATA_MWDMA2, 331 .udma_mask = ATA_UDMA6, 332 .port_ops = &sil680_port_ops 333 }; 334 static const struct ata_port_info info_slow = { 335 .flags = ATA_FLAG_SLAVE_POSS, 336 .pio_mask = ATA_PIO4, 337 .mwdma_mask = ATA_MWDMA2, 338 .udma_mask = ATA_UDMA5, 339 .port_ops = &sil680_port_ops 340 }; 341 const struct ata_port_info *ppi[] = { &info, NULL }; 342 struct ata_host *host; 343 void __iomem *mmio_base; 344 int rc, try_mmio; 345 346 ata_print_version_once(&pdev->dev, DRV_VERSION); 347 348 rc = pcim_enable_device(pdev); 349 if (rc) 350 return rc; 351 352 switch (sil680_init_chip(pdev, &try_mmio)) { 353 case 0: 354 ppi[0] = &info_slow; 355 break; 356 case 0x30: 357 return -ENODEV; 358 } 359 360 if (!try_mmio) 361 goto use_ioports; 362 363 /* Try to acquire MMIO resources and fallback to PIO if 364 * that fails 365 */ 366 rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME); 367 if (rc) 368 goto use_ioports; 369 370 /* Allocate host and set it up */ 371 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2); 372 if (!host) 373 return -ENOMEM; 374 host->iomap = pcim_iomap_table(pdev); 375 376 /* Setup DMA masks */ 377 rc = dma_set_mask(&pdev->dev, ATA_DMA_MASK); 378 if (rc) 379 return rc; 380 rc = dma_set_coherent_mask(&pdev->dev, ATA_DMA_MASK); 381 if (rc) 382 return rc; 383 pci_set_master(pdev); 384 385 /* Get MMIO base and initialize port addresses */ 386 mmio_base = host->iomap[SIL680_MMIO_BAR]; 387 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; 388 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; 389 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; 390 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; 391 ata_sff_std_ports(&host->ports[0]->ioaddr); 392 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; 393 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; 394 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; 395 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; 396 ata_sff_std_ports(&host->ports[1]->ioaddr); 397 398 /* Register & activate */ 399 return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, 400 IRQF_SHARED, &sil680_sht); 401 402use_ioports: 403 return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0); 404} 405 406#ifdef CONFIG_PM_SLEEP 407static int sil680_reinit_one(struct pci_dev *pdev) 408{ 409 struct ata_host *host = pci_get_drvdata(pdev); 410 int try_mmio, rc; 411 412 rc = ata_pci_device_do_resume(pdev); 413 if (rc) 414 return rc; 415 sil680_init_chip(pdev, &try_mmio); 416 ata_host_resume(host); 417 return 0; 418} 419#endif 420 421static const struct pci_device_id sil680[] = { 422 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), }, 423 424 { }, 425}; 426 427static struct pci_driver sil680_pci_driver = { 428 .name = DRV_NAME, 429 .id_table = sil680, 430 .probe = sil680_init_one, 431 .remove = ata_pci_remove_one, 432#ifdef CONFIG_PM_SLEEP 433 .suspend = ata_pci_device_suspend, 434 .resume = sil680_reinit_one, 435#endif 436}; 437 438module_pci_driver(sil680_pci_driver); 439 440MODULE_AUTHOR("Alan Cox"); 441MODULE_DESCRIPTION("low-level driver for SI680 PATA"); 442MODULE_LICENSE("GPL"); 443MODULE_DEVICE_TABLE(pci, sil680); 444MODULE_VERSION(DRV_VERSION); 445