1/*
2 * Marvell EBU SoC common clock handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
8 * Andrew Lunn <andrew@lunn.ch>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __CLK_MVEBU_COMMON_H_
16#define __CLK_MVEBU_COMMON_H_
17
18#include <linux/kernel.h>
19
20extern spinlock_t ctrl_gating_lock;
21
22struct device_node;
23
24struct coreclk_ratio {
25	int id;
26	const char *name;
27};
28
29struct coreclk_soc_desc {
30	u32 (*get_tclk_freq)(void __iomem *sar);
31	u32 (*get_cpu_freq)(void __iomem *sar);
32	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
33	u32 (*get_refclk_freq)(void __iomem *sar);
34	bool (*is_sscg_enabled)(void __iomem *sar);
35	u32 (*fix_sscg_deviation)(u32 system_clk);
36	const struct coreclk_ratio *ratios;
37	int num_ratios;
38};
39
40struct clk_gating_soc_desc {
41	const char *name;
42	const char *parent;
43	int bit_idx;
44	unsigned long flags;
45};
46
47void __init mvebu_coreclk_setup(struct device_node *np,
48				const struct coreclk_soc_desc *desc);
49
50void __init mvebu_clk_gating_setup(struct device_node *np,
51				   const struct clk_gating_soc_desc *desc);
52
53/*
54 * This function is shared among the Kirkwood, Armada 370, Armada XP
55 * and Armada 375 SoC
56 */
57u32 kirkwood_fix_sscg_deviation(u32 system_clk);
58#endif
59