1/*
2 * Marvell PXA family clocks
3 *
4 * Copyright (C) 2014 Robert Jarzmik
5 *
6 * Common clock code for PXA clocks ("CKEN" type clocks + DT)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 */
13#ifndef _CLK_PXA_
14#define _CLK_PXA_
15
16#define PARENTS(name) \
17	static const char *name ## _parents[] __initdata
18#define MUX_RO_RATE_RO_OPS(name, clk_name)			\
19	static struct clk_hw name ## _mux_hw;			\
20	static struct clk_hw name ## _rate_hw;			\
21	static struct clk_ops name ## _mux_ops = {		\
22		.get_parent = name ## _get_parent,		\
23		.set_parent = dummy_clk_set_parent,		\
24	};							\
25	static struct clk_ops name ## _rate_ops = {		\
26		.recalc_rate = name ## _get_rate,		\
27	};							\
28	static struct clk * __init clk_register_ ## name(void)	\
29	{							\
30		return clk_register_composite(NULL, clk_name,	\
31			name ## _parents,			\
32			ARRAY_SIZE(name ## _parents),		\
33			&name ## _mux_hw, &name ## _mux_ops,	\
34			&name ## _rate_hw, &name ## _rate_ops,	\
35			NULL, NULL, CLK_GET_RATE_NOCACHE);	\
36	}
37
38#define RATE_RO_OPS(name, clk_name)			\
39	static struct clk_hw name ## _rate_hw;			\
40	static struct clk_ops name ## _rate_ops = {		\
41		.recalc_rate = name ## _get_rate,		\
42	};							\
43	static struct clk * __init clk_register_ ## name(void)	\
44	{							\
45		return clk_register_composite(NULL, clk_name,	\
46			name ## _parents,			\
47			ARRAY_SIZE(name ## _parents),		\
48			NULL, NULL,				\
49			&name ## _rate_hw, &name ## _rate_ops,	\
50			NULL, NULL, CLK_GET_RATE_NOCACHE);	\
51	}
52
53/*
54 * CKEN clock type
55 * This clock takes it source from 2 possible parents :
56 *  - a low power parent
57 *  - a normal parent
58 *
59 *  +------------+     +-----------+
60 *  |  Low Power | --- | x mult_lp |
61 *  |    Clock   |     | / div_lp  |\
62 *  +------------+     +-----------+ \+-----+   +-----------+
63 *                                    | Mux |---| CKEN gate |
64 *  +------------+     +-----------+ /+-----+   +-----------+
65 *  | High Power |     | x mult_hp |/
66 *  |    Clock   | --- | / div_hp  |
67 *  +------------+     +-----------+
68 */
69struct desc_clk_cken {
70	struct clk_hw hw;
71	int ckid;
72	const char *name;
73	const char *dev_id;
74	const char *con_id;
75	const char **parent_names;
76	struct clk_fixed_factor lp;
77	struct clk_fixed_factor hp;
78	struct clk_gate gate;
79	bool (*is_in_low_power)(void);
80	const unsigned long flags;
81};
82
83#define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp,	\
84		 _mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag)	\
85	{ .ckid = CLK_ ## _name, .name = #_name,			\
86	  .dev_id = _dev_id, .con_id = _con_id,	.parent_names = parents,\
87	  .lp = { .mult = _mult_lp, .div = _div_lp },			\
88	  .hp = { .mult = _mult_hp, .div = _div_hp },			\
89	  .is_in_low_power = is_lp,					\
90	  .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
91	  .flags = flag,						\
92	}
93#define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg,		\
94			    cken_bit, flag)				\
95	PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1,		\
96		 NULL, cken_reg, cken_bit, flag)
97
98static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
99{
100	return 0;
101}
102
103extern void clkdev_pxa_register(int ckid, const char *con_id,
104				const char *dev_id, struct clk *clk);
105extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
106void clk_pxa_dt_common_init(struct device_node *np);
107
108#endif
109