1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/clkdev.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20
21static DEFINE_SPINLOCK(clk_lock);
22
23/*
24 * Gate clocks
25 */
26
27static void __init rk2928_gate_clk_init(struct device_node *node)
28{
29	struct clk_onecell_data *clk_data;
30	const char *clk_parent;
31	const char *clk_name;
32	void __iomem *reg;
33	void __iomem *reg_idx;
34	int flags;
35	int qty;
36	int reg_bit;
37	int clkflags = CLK_SET_RATE_PARENT;
38	int i;
39
40	qty = of_property_count_strings(node, "clock-output-names");
41	if (qty < 0) {
42		pr_err("%s: error in clock-output-names %d\n", __func__, qty);
43		return;
44	}
45
46	if (qty == 0) {
47		pr_info("%s: nothing to do\n", __func__);
48		return;
49	}
50
51	reg = of_iomap(node, 0);
52
53	clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
54	if (!clk_data)
55		return;
56
57	clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
58	if (!clk_data->clks) {
59		kfree(clk_data);
60		return;
61	}
62
63	flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
64
65	for (i = 0; i < qty; i++) {
66		of_property_read_string_index(node, "clock-output-names",
67					      i, &clk_name);
68
69		/* ignore empty slots */
70		if (!strcmp("reserved", clk_name))
71			continue;
72
73		clk_parent = of_clk_get_parent_name(node, i);
74
75		/* keep all gates untouched for now */
76		clkflags |= CLK_IGNORE_UNUSED;
77
78		reg_idx = reg + (4 * (i / 16));
79		reg_bit = (i % 16);
80
81		clk_data->clks[i] = clk_register_gate(NULL, clk_name,
82						      clk_parent, clkflags,
83						      reg_idx, reg_bit,
84						      flags,
85						      &clk_lock);
86		WARN_ON(IS_ERR(clk_data->clks[i]));
87	}
88
89	clk_data->clk_num = qty;
90
91	of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
92}
93CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
94