1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 *		http://www.samsung.com
4 *
5 * EXYNOS4X12 - CPU frequency scaling support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/cpufreq.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21
22#include "exynos-cpufreq.h"
23
24static struct clk *cpu_clk;
25static struct clk *moutcore;
26static struct clk *mout_mpll;
27static struct clk *mout_apll;
28static struct exynos_dvfs_info *cpufreq;
29
30static unsigned int exynos4x12_volt_table[] = {
31	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
32	1000000,  987500,  975000,  950000,  925000,  900000,  900000
33};
34
35static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
36	{CPUFREQ_BOOST_FREQ, L0, 1500 * 1000},
37	{0, L1, 1400 * 1000},
38	{0, L2, 1300 * 1000},
39	{0, L3, 1200 * 1000},
40	{0, L4, 1100 * 1000},
41	{0, L5, 1000 * 1000},
42	{0, L6,  900 * 1000},
43	{0, L7,  800 * 1000},
44	{0, L8,  700 * 1000},
45	{0, L9,  600 * 1000},
46	{0, L10, 500 * 1000},
47	{0, L11, 400 * 1000},
48	{0, L12, 300 * 1000},
49	{0, L13, 200 * 1000},
50	{0, 0, CPUFREQ_TABLE_END},
51};
52
53static struct apll_freq *apll_freq_4x12;
54
55static struct apll_freq apll_freq_4212[] = {
56	/*
57	 * values:
58	 * freq
59	 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
60	 * clock divider for COPY, HPM, RESERVED
61	 * PLL M, P, S
62	 */
63	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
64	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
65	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
66	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
67	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
68	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
69	APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
70	APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
71	APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
72	APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
73	APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
74	APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
75	APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
76	APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
77};
78
79static struct apll_freq apll_freq_4412[] = {
80	/*
81	 * values:
82	 * freq
83	 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
84	 * clock divider for COPY, HPM, CORES
85	 * PLL M, P, S
86	 */
87	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
88	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
89	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
90	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
91	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
92	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
93	APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
94	APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
95	APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
96	APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
97	APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
98	APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
99	APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
100	APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
101};
102
103static void exynos4x12_set_clkdiv(unsigned int div_index)
104{
105	unsigned int tmp;
106
107	/* Change Divider - CPU0 */
108
109	tmp = apll_freq_4x12[div_index].clk_div_cpu0;
110
111	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
112
113	while (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU)
114	       & 0x11111111)
115		cpu_relax();
116
117	/* Change Divider - CPU1 */
118	tmp = apll_freq_4x12[div_index].clk_div_cpu1;
119
120	__raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
121
122	do {
123		cpu_relax();
124		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
125	} while (tmp != 0x0);
126}
127
128static void exynos4x12_set_apll(unsigned int index)
129{
130	unsigned int tmp, freq = apll_freq_4x12[index].freq;
131
132	/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
133	clk_set_parent(moutcore, mout_mpll);
134
135	do {
136		cpu_relax();
137		tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
138			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
139		tmp &= 0x7;
140	} while (tmp != 0x2);
141
142	clk_set_rate(mout_apll, freq * 1000);
143
144	/* MUX_CORE_SEL = APLL */
145	clk_set_parent(moutcore, mout_apll);
146
147	do {
148		cpu_relax();
149		tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
150		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
151	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
152}
153
154static void exynos4x12_set_frequency(unsigned int old_index,
155				  unsigned int new_index)
156{
157	if (old_index > new_index) {
158		exynos4x12_set_clkdiv(new_index);
159		exynos4x12_set_apll(new_index);
160	} else if (old_index < new_index) {
161		exynos4x12_set_apll(new_index);
162		exynos4x12_set_clkdiv(new_index);
163	}
164}
165
166int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
167{
168	struct device_node *np;
169	unsigned long rate;
170
171	/*
172	 * HACK: This is a temporary workaround to get access to clock
173	 * controller registers directly and remove static mappings and
174	 * dependencies on platform headers. It is necessary to enable
175	 * Exynos multi-platform support and will be removed together with
176	 * this whole driver as soon as Exynos gets migrated to use
177	 * cpufreq-dt driver.
178	 */
179	np = of_find_compatible_node(NULL, NULL, "samsung,exynos4412-clock");
180	if (!np) {
181		pr_err("%s: failed to find clock controller DT node\n",
182			__func__);
183		return -ENODEV;
184	}
185
186	info->cmu_regs = of_iomap(np, 0);
187	if (!info->cmu_regs) {
188		pr_err("%s: failed to map CMU registers\n", __func__);
189		return -EFAULT;
190	}
191
192	cpu_clk = clk_get(NULL, "armclk");
193	if (IS_ERR(cpu_clk))
194		return PTR_ERR(cpu_clk);
195
196	moutcore = clk_get(NULL, "moutcore");
197	if (IS_ERR(moutcore))
198		goto err_moutcore;
199
200	mout_mpll = clk_get(NULL, "mout_mpll");
201	if (IS_ERR(mout_mpll))
202		goto err_mout_mpll;
203
204	rate = clk_get_rate(mout_mpll) / 1000;
205
206	mout_apll = clk_get(NULL, "mout_apll");
207	if (IS_ERR(mout_apll))
208		goto err_mout_apll;
209
210	if (info->type == EXYNOS_SOC_4212)
211		apll_freq_4x12 = apll_freq_4212;
212	else
213		apll_freq_4x12 = apll_freq_4412;
214
215	info->mpll_freq_khz = rate;
216	/* 800Mhz */
217	info->pll_safe_idx = L7;
218	info->cpu_clk = cpu_clk;
219	info->volt_table = exynos4x12_volt_table;
220	info->freq_table = exynos4x12_freq_table;
221	info->set_freq = exynos4x12_set_frequency;
222
223	cpufreq = info;
224
225	return 0;
226
227err_mout_apll:
228	clk_put(mout_mpll);
229err_mout_mpll:
230	clk_put(moutcore);
231err_moutcore:
232	clk_put(cpu_clk);
233
234	pr_debug("%s: failed initialization\n", __func__);
235	return -EINVAL;
236}
237