1/*
2 * AMD Cryptographic Coprocessor (CCP) driver
3 *
4 * Copyright (C) 2013 Advanced Micro Devices, Inc.
5 *
6 * Author: Tom Lendacky <thomas.lendacky@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __CCP_DEV_H__
14#define __CCP_DEV_H__
15
16#include <linux/device.h>
17#include <linux/pci.h>
18#include <linux/spinlock.h>
19#include <linux/mutex.h>
20#include <linux/list.h>
21#include <linux/wait.h>
22#include <linux/dmapool.h>
23#include <linux/hw_random.h>
24#include <linux/bitops.h>
25
26#define MAX_DMAPOOL_NAME_LEN		32
27
28#define MAX_HW_QUEUES			5
29#define MAX_CMD_QLEN			100
30
31#define TRNG_RETRIES			10
32
33#define CACHE_NONE			0x00
34#define CACHE_WB_NO_ALLOC		0xb7
35
36/****** Register Mappings ******/
37#define Q_MASK_REG			0x000
38#define TRNG_OUT_REG			0x00c
39#define IRQ_MASK_REG			0x040
40#define IRQ_STATUS_REG			0x200
41
42#define DEL_CMD_Q_JOB			0x124
43#define DEL_Q_ACTIVE			0x00000200
44#define DEL_Q_ID_SHIFT			6
45
46#define CMD_REQ0			0x180
47#define CMD_REQ_INCR			0x04
48
49#define CMD_Q_STATUS_BASE		0x210
50#define CMD_Q_INT_STATUS_BASE		0x214
51#define CMD_Q_STATUS_INCR		0x20
52
53#define CMD_Q_CACHE_BASE		0x228
54#define CMD_Q_CACHE_INC			0x20
55
56#define CMD_Q_ERROR(__qs)		((__qs) & 0x0000003f)
57#define CMD_Q_DEPTH(__qs)		(((__qs) >> 12) & 0x0000000f)
58
59/****** REQ0 Related Values ******/
60#define REQ0_WAIT_FOR_WRITE		0x00000004
61#define REQ0_INT_ON_COMPLETE		0x00000002
62#define REQ0_STOP_ON_COMPLETE		0x00000001
63
64#define REQ0_CMD_Q_SHIFT		9
65#define REQ0_JOBID_SHIFT		3
66
67/****** REQ1 Related Values ******/
68#define REQ1_PROTECT_SHIFT		27
69#define REQ1_ENGINE_SHIFT		23
70#define REQ1_KEY_KSB_SHIFT		2
71
72#define REQ1_EOM			0x00000002
73#define REQ1_INIT			0x00000001
74
75/* AES Related Values */
76#define REQ1_AES_TYPE_SHIFT		21
77#define REQ1_AES_MODE_SHIFT		18
78#define REQ1_AES_ACTION_SHIFT		17
79#define REQ1_AES_CFB_SIZE_SHIFT		10
80
81/* XTS-AES Related Values */
82#define REQ1_XTS_AES_SIZE_SHIFT		10
83
84/* SHA Related Values */
85#define REQ1_SHA_TYPE_SHIFT		21
86
87/* RSA Related Values */
88#define REQ1_RSA_MOD_SIZE_SHIFT		10
89
90/* Pass-Through Related Values */
91#define REQ1_PT_BW_SHIFT		12
92#define REQ1_PT_BS_SHIFT		10
93
94/* ECC Related Values */
95#define REQ1_ECC_AFFINE_CONVERT		0x00200000
96#define REQ1_ECC_FUNCTION_SHIFT		18
97
98/****** REQ4 Related Values ******/
99#define REQ4_KSB_SHIFT			18
100#define REQ4_MEMTYPE_SHIFT		16
101
102/****** REQ6 Related Values ******/
103#define REQ6_MEMTYPE_SHIFT		16
104
105/****** Key Storage Block ******/
106#define KSB_START			77
107#define KSB_END				127
108#define KSB_COUNT			(KSB_END - KSB_START + 1)
109#define CCP_KSB_BITS			256
110#define CCP_KSB_BYTES			32
111
112#define CCP_JOBID_MASK			0x0000003f
113
114#define CCP_DMAPOOL_MAX_SIZE		64
115#define CCP_DMAPOOL_ALIGN		BIT(5)
116
117#define CCP_REVERSE_BUF_SIZE		64
118
119#define CCP_AES_KEY_KSB_COUNT		1
120#define CCP_AES_CTX_KSB_COUNT		1
121
122#define CCP_XTS_AES_KEY_KSB_COUNT	1
123#define CCP_XTS_AES_CTX_KSB_COUNT	1
124
125#define CCP_SHA_KSB_COUNT		1
126
127#define CCP_RSA_MAX_WIDTH		4096
128
129#define CCP_PASSTHRU_BLOCKSIZE		256
130#define CCP_PASSTHRU_MASKSIZE		32
131#define CCP_PASSTHRU_KSB_COUNT		1
132
133#define CCP_ECC_MODULUS_BYTES		48      /* 384-bits */
134#define CCP_ECC_MAX_OPERANDS		6
135#define CCP_ECC_MAX_OUTPUTS		3
136#define CCP_ECC_SRC_BUF_SIZE		448
137#define CCP_ECC_DST_BUF_SIZE		192
138#define CCP_ECC_OPERAND_SIZE		64
139#define CCP_ECC_OUTPUT_SIZE		64
140#define CCP_ECC_RESULT_OFFSET		60
141#define CCP_ECC_RESULT_SUCCESS		0x0001
142
143struct ccp_device;
144struct ccp_cmd;
145
146struct ccp_cmd_queue {
147	struct ccp_device *ccp;
148
149	/* Queue identifier */
150	u32 id;
151
152	/* Queue dma pool */
153	struct dma_pool *dma_pool;
154
155	/* Queue reserved KSB regions */
156	u32 ksb_key;
157	u32 ksb_ctx;
158
159	/* Queue processing thread */
160	struct task_struct *kthread;
161	unsigned int active;
162	unsigned int suspended;
163
164	/* Number of free command slots available */
165	unsigned int free_slots;
166
167	/* Interrupt masks */
168	u32 int_ok;
169	u32 int_err;
170
171	/* Register addresses for queue */
172	void __iomem *reg_status;
173	void __iomem *reg_int_status;
174
175	/* Status values from job */
176	u32 int_status;
177	u32 q_status;
178	u32 q_int_status;
179	u32 cmd_error;
180
181	/* Interrupt wait queue */
182	wait_queue_head_t int_queue;
183	unsigned int int_rcvd;
184} ____cacheline_aligned;
185
186struct ccp_device {
187	struct device *dev;
188
189	/*
190	 * Bus specific device information
191	 */
192	void *dev_specific;
193	int (*get_irq)(struct ccp_device *ccp);
194	void (*free_irq)(struct ccp_device *ccp);
195	unsigned int irq;
196
197	/*
198	 * I/O area used for device communication. The register mapping
199	 * starts at an offset into the mapped bar.
200	 *   The CMD_REQx registers and the Delete_Cmd_Queue_Job register
201	 *   need to be protected while a command queue thread is accessing
202	 *   them.
203	 */
204	struct mutex req_mutex ____cacheline_aligned;
205	void __iomem *io_map;
206	void __iomem *io_regs;
207
208	/*
209	 * Master lists that all cmds are queued on. Because there can be
210	 * more than one CCP command queue that can process a cmd a separate
211	 * backlog list is neeeded so that the backlog completion call
212	 * completes before the cmd is available for execution.
213	 */
214	spinlock_t cmd_lock ____cacheline_aligned;
215	unsigned int cmd_count;
216	struct list_head cmd;
217	struct list_head backlog;
218
219	/*
220	 * The command queues. These represent the queues available on the
221	 * CCP that are available for processing cmds
222	 */
223	struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
224	unsigned int cmd_q_count;
225
226	/*
227	 * Support for the CCP True RNG
228	 */
229	struct hwrng hwrng;
230	unsigned int hwrng_retries;
231
232	/*
233	 * A counter used to generate job-ids for cmds submitted to the CCP
234	 */
235	atomic_t current_id ____cacheline_aligned;
236
237	/*
238	 * The CCP uses key storage blocks (KSB) to maintain context for certain
239	 * operations. To prevent multiple cmds from using the same KSB range
240	 * a command queue reserves a KSB range for the duration of the cmd.
241	 * Each queue, will however, reserve 2 KSB blocks for operations that
242	 * only require single KSB entries (eg. AES context/iv and key) in order
243	 * to avoid allocation contention.  This will reserve at most 10 KSB
244	 * entries, leaving 40 KSB entries available for dynamic allocation.
245	 */
246	struct mutex ksb_mutex ____cacheline_aligned;
247	DECLARE_BITMAP(ksb, KSB_COUNT);
248	wait_queue_head_t ksb_queue;
249	unsigned int ksb_avail;
250	unsigned int ksb_count;
251	u32 ksb_start;
252
253	/* Suspend support */
254	unsigned int suspending;
255	wait_queue_head_t suspend_queue;
256
257	/* DMA caching attribute support */
258	unsigned int axcache;
259};
260
261int ccp_pci_init(void);
262void ccp_pci_exit(void);
263
264int ccp_platform_init(void);
265void ccp_platform_exit(void);
266
267struct ccp_device *ccp_alloc_struct(struct device *dev);
268int ccp_init(struct ccp_device *ccp);
269void ccp_destroy(struct ccp_device *ccp);
270bool ccp_queues_suspended(struct ccp_device *ccp);
271
272irqreturn_t ccp_irq_handler(int irq, void *data);
273
274int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
275
276#endif
277