1/* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27#include <linux/dmi.h> 28#include <linux/i2c.h> 29#include <linux/slab.h> 30#include <drm/drmP.h> 31#include <drm/drm_atomic_helper.h> 32#include <drm/drm_crtc.h> 33#include <drm/drm_crtc_helper.h> 34#include <drm/drm_edid.h> 35#include "intel_drv.h" 36#include <drm/i915_drm.h> 37#include "i915_drv.h" 38 39/* Here's the desired hotplug mode */ 40#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 41 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 42 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 43 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 44 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 45 ADPA_CRT_HOTPLUG_ENABLE) 46 47struct intel_crt { 48 struct intel_encoder base; 49 /* DPMS state is stored in the connector, which we need in the 50 * encoder's enable/disable callbacks */ 51 struct intel_connector *connector; 52 bool force_hotplug_required; 53 u32 adpa_reg; 54}; 55 56static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 57{ 58 return container_of(encoder, struct intel_crt, base); 59} 60 61static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 62{ 63 return intel_encoder_to_crt(intel_attached_encoder(connector)); 64} 65 66static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 67 enum pipe *pipe) 68{ 69 struct drm_device *dev = encoder->base.dev; 70 struct drm_i915_private *dev_priv = dev->dev_private; 71 struct intel_crt *crt = intel_encoder_to_crt(encoder); 72 enum intel_display_power_domain power_domain; 73 u32 tmp; 74 75 power_domain = intel_display_port_power_domain(encoder); 76 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 77 return false; 78 79 tmp = I915_READ(crt->adpa_reg); 80 81 if (!(tmp & ADPA_DAC_ENABLE)) 82 return false; 83 84 if (HAS_PCH_CPT(dev)) 85 *pipe = PORT_TO_PIPE_CPT(tmp); 86 else 87 *pipe = PORT_TO_PIPE(tmp); 88 89 return true; 90} 91 92static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 93{ 94 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 95 struct intel_crt *crt = intel_encoder_to_crt(encoder); 96 u32 tmp, flags = 0; 97 98 tmp = I915_READ(crt->adpa_reg); 99 100 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 101 flags |= DRM_MODE_FLAG_PHSYNC; 102 else 103 flags |= DRM_MODE_FLAG_NHSYNC; 104 105 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 106 flags |= DRM_MODE_FLAG_PVSYNC; 107 else 108 flags |= DRM_MODE_FLAG_NVSYNC; 109 110 return flags; 111} 112 113static void intel_crt_get_config(struct intel_encoder *encoder, 114 struct intel_crtc_state *pipe_config) 115{ 116 struct drm_device *dev = encoder->base.dev; 117 int dotclock; 118 119 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 120 121 dotclock = pipe_config->port_clock; 122 123 if (HAS_PCH_SPLIT(dev)) 124 ironlake_check_encoder_dotclock(pipe_config, dotclock); 125 126 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 127} 128 129static void hsw_crt_get_config(struct intel_encoder *encoder, 130 struct intel_crtc_state *pipe_config) 131{ 132 intel_ddi_get_config(encoder, pipe_config); 133 134 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 135 DRM_MODE_FLAG_NHSYNC | 136 DRM_MODE_FLAG_PVSYNC | 137 DRM_MODE_FLAG_NVSYNC); 138 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 139} 140 141static void hsw_crt_pre_enable(struct intel_encoder *encoder) 142{ 143 struct drm_device *dev = encoder->base.dev; 144 struct drm_i915_private *dev_priv = dev->dev_private; 145 146 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); 147 I915_WRITE(SPLL_CTL, 148 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); 149 POSTING_READ(SPLL_CTL); 150 udelay(20); 151} 152 153/* Note: The caller is required to filter out dpms modes not supported by the 154 * platform. */ 155static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 156{ 157 struct drm_device *dev = encoder->base.dev; 158 struct drm_i915_private *dev_priv = dev->dev_private; 159 struct intel_crt *crt = intel_encoder_to_crt(encoder); 160 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 161 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 162 u32 adpa; 163 164 if (INTEL_INFO(dev)->gen >= 5) 165 adpa = ADPA_HOTPLUG_BITS; 166 else 167 adpa = 0; 168 169 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 170 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 171 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 172 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 173 174 /* For CPT allow 3 pipe config, for others just use A or B */ 175 if (HAS_PCH_LPT(dev)) 176 ; /* Those bits don't exist here */ 177 else if (HAS_PCH_CPT(dev)) 178 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 179 else if (crtc->pipe == 0) 180 adpa |= ADPA_PIPE_A_SELECT; 181 else 182 adpa |= ADPA_PIPE_B_SELECT; 183 184 if (!HAS_PCH_SPLIT(dev)) 185 I915_WRITE(BCLRPAT(crtc->pipe), 0); 186 187 switch (mode) { 188 case DRM_MODE_DPMS_ON: 189 adpa |= ADPA_DAC_ENABLE; 190 break; 191 case DRM_MODE_DPMS_STANDBY: 192 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 193 break; 194 case DRM_MODE_DPMS_SUSPEND: 195 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 196 break; 197 case DRM_MODE_DPMS_OFF: 198 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 199 break; 200 } 201 202 I915_WRITE(crt->adpa_reg, adpa); 203} 204 205static void intel_disable_crt(struct intel_encoder *encoder) 206{ 207 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 208} 209 210 211static void hsw_crt_post_disable(struct intel_encoder *encoder) 212{ 213 struct drm_device *dev = encoder->base.dev; 214 struct drm_i915_private *dev_priv = dev->dev_private; 215 uint32_t val; 216 217 DRM_DEBUG_KMS("Disabling SPLL\n"); 218 val = I915_READ(SPLL_CTL); 219 WARN_ON(!(val & SPLL_PLL_ENABLE)); 220 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); 221 POSTING_READ(SPLL_CTL); 222} 223 224static void intel_enable_crt(struct intel_encoder *encoder) 225{ 226 struct intel_crt *crt = intel_encoder_to_crt(encoder); 227 228 intel_crt_set_dpms(encoder, crt->connector->base.dpms); 229} 230 231/* Special dpms function to support cloning between dvo/sdvo/crt. */ 232static void intel_crt_dpms(struct drm_connector *connector, int mode) 233{ 234 struct drm_device *dev = connector->dev; 235 struct intel_encoder *encoder = intel_attached_encoder(connector); 236 struct drm_crtc *crtc; 237 int old_dpms; 238 239 /* PCH platforms and VLV only support on/off. */ 240 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) 241 mode = DRM_MODE_DPMS_OFF; 242 243 if (mode == connector->dpms) 244 return; 245 246 old_dpms = connector->dpms; 247 connector->dpms = mode; 248 249 /* Only need to change hw state when actually enabled */ 250 crtc = encoder->base.crtc; 251 if (!crtc) { 252 encoder->connectors_active = false; 253 return; 254 } 255 256 /* We need the pipe to run for anything but OFF. */ 257 if (mode == DRM_MODE_DPMS_OFF) 258 encoder->connectors_active = false; 259 else 260 encoder->connectors_active = true; 261 262 /* We call connector dpms manually below in case pipe dpms doesn't 263 * change due to cloning. */ 264 if (mode < old_dpms) { 265 /* From off to on, enable the pipe first. */ 266 intel_crtc_update_dpms(crtc); 267 268 intel_crt_set_dpms(encoder, mode); 269 } else { 270 intel_crt_set_dpms(encoder, mode); 271 272 intel_crtc_update_dpms(crtc); 273 } 274 275 intel_modeset_check_state(connector->dev); 276} 277 278static enum drm_mode_status 279intel_crt_mode_valid(struct drm_connector *connector, 280 struct drm_display_mode *mode) 281{ 282 struct drm_device *dev = connector->dev; 283 284 int max_clock = 0; 285 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 286 return MODE_NO_DBLESCAN; 287 288 if (mode->clock < 25000) 289 return MODE_CLOCK_LOW; 290 291 if (IS_GEN2(dev)) 292 max_clock = 350000; 293 else 294 max_clock = 400000; 295 if (mode->clock > max_clock) 296 return MODE_CLOCK_HIGH; 297 298 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 299 if (HAS_PCH_LPT(dev) && 300 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 301 return MODE_CLOCK_HIGH; 302 303 return MODE_OK; 304} 305 306static bool intel_crt_compute_config(struct intel_encoder *encoder, 307 struct intel_crtc_state *pipe_config) 308{ 309 struct drm_device *dev = encoder->base.dev; 310 311 if (HAS_PCH_SPLIT(dev)) 312 pipe_config->has_pch_encoder = true; 313 314 /* LPT FDI RX only supports 8bpc. */ 315 if (HAS_PCH_LPT(dev)) { 316 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 317 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 318 return false; 319 } 320 321 pipe_config->pipe_bpp = 24; 322 } 323 324 /* FDI must always be 2.7 GHz */ 325 if (HAS_DDI(dev)) { 326 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 327 pipe_config->port_clock = 135000 * 2; 328 } 329 330 return true; 331} 332 333static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 334{ 335 struct drm_device *dev = connector->dev; 336 struct intel_crt *crt = intel_attached_crt(connector); 337 struct drm_i915_private *dev_priv = dev->dev_private; 338 u32 adpa; 339 bool ret; 340 341 /* The first time through, trigger an explicit detection cycle */ 342 if (crt->force_hotplug_required) { 343 bool turn_off_dac = HAS_PCH_SPLIT(dev); 344 u32 save_adpa; 345 346 crt->force_hotplug_required = 0; 347 348 save_adpa = adpa = I915_READ(crt->adpa_reg); 349 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 350 351 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 352 if (turn_off_dac) 353 adpa &= ~ADPA_DAC_ENABLE; 354 355 I915_WRITE(crt->adpa_reg, adpa); 356 357 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 358 1000)) 359 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 360 361 if (turn_off_dac) { 362 I915_WRITE(crt->adpa_reg, save_adpa); 363 POSTING_READ(crt->adpa_reg); 364 } 365 } 366 367 /* Check the status to see if both blue and green are on now */ 368 adpa = I915_READ(crt->adpa_reg); 369 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 370 ret = true; 371 else 372 ret = false; 373 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 374 375 return ret; 376} 377 378static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 379{ 380 struct drm_device *dev = connector->dev; 381 struct intel_crt *crt = intel_attached_crt(connector); 382 struct drm_i915_private *dev_priv = dev->dev_private; 383 u32 adpa; 384 bool ret; 385 u32 save_adpa; 386 387 save_adpa = adpa = I915_READ(crt->adpa_reg); 388 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 389 390 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 391 392 I915_WRITE(crt->adpa_reg, adpa); 393 394 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 395 1000)) { 396 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 397 I915_WRITE(crt->adpa_reg, save_adpa); 398 } 399 400 /* Check the status to see if both blue and green are on now */ 401 adpa = I915_READ(crt->adpa_reg); 402 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 403 ret = true; 404 else 405 ret = false; 406 407 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 408 409 return ret; 410} 411 412/** 413 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 414 * 415 * Not for i915G/i915GM 416 * 417 * \return true if CRT is connected. 418 * \return false if CRT is disconnected. 419 */ 420static bool intel_crt_detect_hotplug(struct drm_connector *connector) 421{ 422 struct drm_device *dev = connector->dev; 423 struct drm_i915_private *dev_priv = dev->dev_private; 424 u32 hotplug_en, orig, stat; 425 bool ret = false; 426 int i, tries = 0; 427 428 if (HAS_PCH_SPLIT(dev)) 429 return intel_ironlake_crt_detect_hotplug(connector); 430 431 if (IS_VALLEYVIEW(dev)) 432 return valleyview_crt_detect_hotplug(connector); 433 434 /* 435 * On 4 series desktop, CRT detect sequence need to be done twice 436 * to get a reliable result. 437 */ 438 439 if (IS_G4X(dev) && !IS_GM45(dev)) 440 tries = 2; 441 else 442 tries = 1; 443 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); 444 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; 445 446 for (i = 0; i < tries ; i++) { 447 /* turn on the FORCE_DETECT */ 448 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 449 /* wait for FORCE_DETECT to go off */ 450 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 451 CRT_HOTPLUG_FORCE_DETECT) == 0, 452 1000)) 453 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 454 } 455 456 stat = I915_READ(PORT_HOTPLUG_STAT); 457 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 458 ret = true; 459 460 /* clear the interrupt we just generated, if any */ 461 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 462 463 /* and put the bits back */ 464 I915_WRITE(PORT_HOTPLUG_EN, orig); 465 466 return ret; 467} 468 469static struct edid *intel_crt_get_edid(struct drm_connector *connector, 470 struct i2c_adapter *i2c) 471{ 472 struct edid *edid; 473 474 edid = drm_get_edid(connector, i2c); 475 476 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 477 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 478 intel_gmbus_force_bit(i2c, true); 479 edid = drm_get_edid(connector, i2c); 480 intel_gmbus_force_bit(i2c, false); 481 } 482 483 return edid; 484} 485 486/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 487static int intel_crt_ddc_get_modes(struct drm_connector *connector, 488 struct i2c_adapter *adapter) 489{ 490 struct edid *edid; 491 int ret; 492 493 edid = intel_crt_get_edid(connector, adapter); 494 if (!edid) 495 return 0; 496 497 ret = intel_connector_update_modes(connector, edid); 498 kfree(edid); 499 500 return ret; 501} 502 503static bool intel_crt_detect_ddc(struct drm_connector *connector) 504{ 505 struct intel_crt *crt = intel_attached_crt(connector); 506 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 507 struct edid *edid; 508 struct i2c_adapter *i2c; 509 510 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 511 512 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 513 edid = intel_crt_get_edid(connector, i2c); 514 515 if (edid) { 516 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 517 518 /* 519 * This may be a DVI-I connector with a shared DDC 520 * link between analog and digital outputs, so we 521 * have to check the EDID input spec of the attached device. 522 */ 523 if (!is_digital) { 524 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 525 return true; 526 } 527 528 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 529 } else { 530 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 531 } 532 533 kfree(edid); 534 535 return false; 536} 537 538static enum drm_connector_status 539intel_crt_load_detect(struct intel_crt *crt) 540{ 541 struct drm_device *dev = crt->base.base.dev; 542 struct drm_i915_private *dev_priv = dev->dev_private; 543 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; 544 uint32_t save_bclrpat; 545 uint32_t save_vtotal; 546 uint32_t vtotal, vactive; 547 uint32_t vsample; 548 uint32_t vblank, vblank_start, vblank_end; 549 uint32_t dsl; 550 uint32_t bclrpat_reg; 551 uint32_t vtotal_reg; 552 uint32_t vblank_reg; 553 uint32_t vsync_reg; 554 uint32_t pipeconf_reg; 555 uint32_t pipe_dsl_reg; 556 uint8_t st00; 557 enum drm_connector_status status; 558 559 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 560 561 bclrpat_reg = BCLRPAT(pipe); 562 vtotal_reg = VTOTAL(pipe); 563 vblank_reg = VBLANK(pipe); 564 vsync_reg = VSYNC(pipe); 565 pipeconf_reg = PIPECONF(pipe); 566 pipe_dsl_reg = PIPEDSL(pipe); 567 568 save_bclrpat = I915_READ(bclrpat_reg); 569 save_vtotal = I915_READ(vtotal_reg); 570 vblank = I915_READ(vblank_reg); 571 572 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 573 vactive = (save_vtotal & 0x7ff) + 1; 574 575 vblank_start = (vblank & 0xfff) + 1; 576 vblank_end = ((vblank >> 16) & 0xfff) + 1; 577 578 /* Set the border color to purple. */ 579 I915_WRITE(bclrpat_reg, 0x500050); 580 581 if (!IS_GEN2(dev)) { 582 uint32_t pipeconf = I915_READ(pipeconf_reg); 583 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 584 POSTING_READ(pipeconf_reg); 585 /* Wait for next Vblank to substitue 586 * border color for Color info */ 587 intel_wait_for_vblank(dev, pipe); 588 st00 = I915_READ8(VGA_MSR_WRITE); 589 status = ((st00 & (1 << 4)) != 0) ? 590 connector_status_connected : 591 connector_status_disconnected; 592 593 I915_WRITE(pipeconf_reg, pipeconf); 594 } else { 595 bool restore_vblank = false; 596 int count, detect; 597 598 /* 599 * If there isn't any border, add some. 600 * Yes, this will flicker 601 */ 602 if (vblank_start <= vactive && vblank_end >= vtotal) { 603 uint32_t vsync = I915_READ(vsync_reg); 604 uint32_t vsync_start = (vsync & 0xffff) + 1; 605 606 vblank_start = vsync_start; 607 I915_WRITE(vblank_reg, 608 (vblank_start - 1) | 609 ((vblank_end - 1) << 16)); 610 restore_vblank = true; 611 } 612 /* sample in the vertical border, selecting the larger one */ 613 if (vblank_start - vactive >= vtotal - vblank_end) 614 vsample = (vblank_start + vactive) >> 1; 615 else 616 vsample = (vtotal + vblank_end) >> 1; 617 618 /* 619 * Wait for the border to be displayed 620 */ 621 while (I915_READ(pipe_dsl_reg) >= vactive) 622 ; 623 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 624 ; 625 /* 626 * Watch ST00 for an entire scanline 627 */ 628 detect = 0; 629 count = 0; 630 do { 631 count++; 632 /* Read the ST00 VGA status register */ 633 st00 = I915_READ8(VGA_MSR_WRITE); 634 if (st00 & (1 << 4)) 635 detect++; 636 } while ((I915_READ(pipe_dsl_reg) == dsl)); 637 638 /* restore vblank if necessary */ 639 if (restore_vblank) 640 I915_WRITE(vblank_reg, vblank); 641 /* 642 * If more than 3/4 of the scanline detected a monitor, 643 * then it is assumed to be present. This works even on i830, 644 * where there isn't any way to force the border color across 645 * the screen 646 */ 647 status = detect * 4 > count * 3 ? 648 connector_status_connected : 649 connector_status_disconnected; 650 } 651 652 /* Restore previous settings */ 653 I915_WRITE(bclrpat_reg, save_bclrpat); 654 655 return status; 656} 657 658static enum drm_connector_status 659intel_crt_detect(struct drm_connector *connector, bool force) 660{ 661 struct drm_device *dev = connector->dev; 662 struct drm_i915_private *dev_priv = dev->dev_private; 663 struct intel_crt *crt = intel_attached_crt(connector); 664 struct intel_encoder *intel_encoder = &crt->base; 665 enum intel_display_power_domain power_domain; 666 enum drm_connector_status status; 667 struct intel_load_detect_pipe tmp; 668 struct drm_modeset_acquire_ctx ctx; 669 670 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 671 connector->base.id, connector->name, 672 force); 673 674 power_domain = intel_display_port_power_domain(intel_encoder); 675 intel_display_power_get(dev_priv, power_domain); 676 677 if (I915_HAS_HOTPLUG(dev)) { 678 /* We can not rely on the HPD pin always being correctly wired 679 * up, for example many KVM do not pass it through, and so 680 * only trust an assertion that the monitor is connected. 681 */ 682 if (intel_crt_detect_hotplug(connector)) { 683 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 684 status = connector_status_connected; 685 goto out; 686 } else 687 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 688 } 689 690 if (intel_crt_detect_ddc(connector)) { 691 status = connector_status_connected; 692 goto out; 693 } 694 695 /* Load detection is broken on HPD capable machines. Whoever wants a 696 * broken monitor (without edid) to work behind a broken kvm (that fails 697 * to have the right resistors for HP detection) needs to fix this up. 698 * For now just bail out. */ 699 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 700 status = connector_status_disconnected; 701 goto out; 702 } 703 704 if (!force) { 705 status = connector->status; 706 goto out; 707 } 708 709 drm_modeset_acquire_init(&ctx, 0); 710 711 /* for pre-945g platforms use load detect */ 712 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 713 if (intel_crt_detect_ddc(connector)) 714 status = connector_status_connected; 715 else if (INTEL_INFO(dev)->gen < 4) 716 status = intel_crt_load_detect(crt); 717 else 718 status = connector_status_unknown; 719 intel_release_load_detect_pipe(connector, &tmp, &ctx); 720 } else 721 status = connector_status_unknown; 722 723 drm_modeset_drop_locks(&ctx); 724 drm_modeset_acquire_fini(&ctx); 725 726out: 727 intel_display_power_put(dev_priv, power_domain); 728 return status; 729} 730 731static void intel_crt_destroy(struct drm_connector *connector) 732{ 733 drm_connector_cleanup(connector); 734 kfree(connector); 735} 736 737static int intel_crt_get_modes(struct drm_connector *connector) 738{ 739 struct drm_device *dev = connector->dev; 740 struct drm_i915_private *dev_priv = dev->dev_private; 741 struct intel_crt *crt = intel_attached_crt(connector); 742 struct intel_encoder *intel_encoder = &crt->base; 743 enum intel_display_power_domain power_domain; 744 int ret; 745 struct i2c_adapter *i2c; 746 747 power_domain = intel_display_port_power_domain(intel_encoder); 748 intel_display_power_get(dev_priv, power_domain); 749 750 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 751 ret = intel_crt_ddc_get_modes(connector, i2c); 752 if (ret || !IS_G4X(dev)) 753 goto out; 754 755 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 756 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); 757 ret = intel_crt_ddc_get_modes(connector, i2c); 758 759out: 760 intel_display_power_put(dev_priv, power_domain); 761 762 return ret; 763} 764 765static int intel_crt_set_property(struct drm_connector *connector, 766 struct drm_property *property, 767 uint64_t value) 768{ 769 return 0; 770} 771 772static void intel_crt_reset(struct drm_connector *connector) 773{ 774 struct drm_device *dev = connector->dev; 775 struct drm_i915_private *dev_priv = dev->dev_private; 776 struct intel_crt *crt = intel_attached_crt(connector); 777 778 if (INTEL_INFO(dev)->gen >= 5) { 779 u32 adpa; 780 781 adpa = I915_READ(crt->adpa_reg); 782 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 783 adpa |= ADPA_HOTPLUG_BITS; 784 I915_WRITE(crt->adpa_reg, adpa); 785 POSTING_READ(crt->adpa_reg); 786 787 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 788 crt->force_hotplug_required = 1; 789 } 790 791} 792 793/* 794 * Routines for controlling stuff on the analog port 795 */ 796 797static const struct drm_connector_funcs intel_crt_connector_funcs = { 798 .reset = intel_crt_reset, 799 .dpms = intel_crt_dpms, 800 .detect = intel_crt_detect, 801 .fill_modes = drm_helper_probe_single_connector_modes, 802 .destroy = intel_crt_destroy, 803 .set_property = intel_crt_set_property, 804 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 805 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 806 .atomic_get_property = intel_connector_atomic_get_property, 807}; 808 809static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 810 .mode_valid = intel_crt_mode_valid, 811 .get_modes = intel_crt_get_modes, 812 .best_encoder = intel_best_encoder, 813}; 814 815static const struct drm_encoder_funcs intel_crt_enc_funcs = { 816 .destroy = intel_encoder_destroy, 817}; 818 819static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 820{ 821 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 822 return 1; 823} 824 825static const struct dmi_system_id intel_no_crt[] = { 826 { 827 .callback = intel_no_crt_dmi_callback, 828 .ident = "ACER ZGB", 829 .matches = { 830 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 831 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 832 }, 833 }, 834 { 835 .callback = intel_no_crt_dmi_callback, 836 .ident = "DELL XPS 8700", 837 .matches = { 838 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 839 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 840 }, 841 }, 842 { } 843}; 844 845void intel_crt_init(struct drm_device *dev) 846{ 847 struct drm_connector *connector; 848 struct intel_crt *crt; 849 struct intel_connector *intel_connector; 850 struct drm_i915_private *dev_priv = dev->dev_private; 851 852 /* Skip machines without VGA that falsely report hotplug events */ 853 if (dmi_check_system(intel_no_crt)) 854 return; 855 856 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 857 if (!crt) 858 return; 859 860 intel_connector = intel_connector_alloc(); 861 if (!intel_connector) { 862 kfree(crt); 863 return; 864 } 865 866 connector = &intel_connector->base; 867 crt->connector = intel_connector; 868 drm_connector_init(dev, &intel_connector->base, 869 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 870 871 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 872 DRM_MODE_ENCODER_DAC); 873 874 intel_connector_attach_encoder(intel_connector, &crt->base); 875 876 crt->base.type = INTEL_OUTPUT_ANALOG; 877 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 878 if (IS_I830(dev)) 879 crt->base.crtc_mask = (1 << 0); 880 else 881 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 882 883 if (IS_GEN2(dev)) 884 connector->interlace_allowed = 0; 885 else 886 connector->interlace_allowed = 1; 887 connector->doublescan_allowed = 0; 888 889 if (HAS_PCH_SPLIT(dev)) 890 crt->adpa_reg = PCH_ADPA; 891 else if (IS_VALLEYVIEW(dev)) 892 crt->adpa_reg = VLV_ADPA; 893 else 894 crt->adpa_reg = ADPA; 895 896 crt->base.compute_config = intel_crt_compute_config; 897 crt->base.disable = intel_disable_crt; 898 crt->base.enable = intel_enable_crt; 899 if (I915_HAS_HOTPLUG(dev)) 900 crt->base.hpd_pin = HPD_CRT; 901 if (HAS_DDI(dev)) { 902 crt->base.get_config = hsw_crt_get_config; 903 crt->base.get_hw_state = intel_ddi_get_hw_state; 904 crt->base.pre_enable = hsw_crt_pre_enable; 905 crt->base.post_disable = hsw_crt_post_disable; 906 } else { 907 crt->base.get_config = intel_crt_get_config; 908 crt->base.get_hw_state = intel_crt_get_hw_state; 909 } 910 intel_connector->get_hw_state = intel_connector_get_hw_state; 911 intel_connector->unregister = intel_connector_unregister; 912 913 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 914 915 drm_connector_register(connector); 916 917 if (!I915_HAS_HOTPLUG(dev)) 918 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 919 920 /* 921 * Configure the automatic hotplug detection stuff 922 */ 923 crt->force_hotplug_required = 0; 924 925 /* 926 * TODO: find a proper way to discover whether we need to set the the 927 * polarity and link reversal bits or not, instead of relying on the 928 * BIOS. 929 */ 930 if (HAS_PCH_LPT(dev)) { 931 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 932 FDI_RX_LINK_REVERSAL_OVERRIDE; 933 934 dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; 935 } 936 937 intel_crt_reset(connector); 938} 939