1/* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29#include <linux/i2c.h> 30#include <linux/i2c-algo-bit.h> 31#include <linux/export.h> 32#include <drm/drmP.h> 33#include "intel_drv.h" 34#include <drm/i915_drm.h> 35#include "i915_drv.h" 36 37struct gmbus_port { 38 const char *name; 39 int reg; 40}; 41 42static const struct gmbus_port gmbus_ports[] = { 43 { "ssc", GPIOB }, 44 { "vga", GPIOA }, 45 { "panel", GPIOC }, 46 { "dpc", GPIOD }, 47 { "dpb", GPIOE }, 48 { "dpd", GPIOF }, 49}; 50 51/* Intel GPIO access functions */ 52 53#define I2C_RISEFALL_TIME 10 54 55static inline struct intel_gmbus * 56to_intel_gmbus(struct i2c_adapter *i2c) 57{ 58 return container_of(i2c, struct intel_gmbus, adapter); 59} 60 61void 62intel_i2c_reset(struct drm_device *dev) 63{ 64 struct drm_i915_private *dev_priv = dev->dev_private; 65 66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); 67 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); 68} 69 70static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) 71{ 72 u32 val; 73 74 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 75 if (!IS_PINEVIEW(dev_priv->dev)) 76 return; 77 78 val = I915_READ(DSPCLK_GATE_D); 79 if (enable) 80 val |= DPCUNIT_CLOCK_GATE_DISABLE; 81 else 82 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 83 I915_WRITE(DSPCLK_GATE_D, val); 84} 85 86static u32 get_reserved(struct intel_gmbus *bus) 87{ 88 struct drm_i915_private *dev_priv = bus->dev_priv; 89 struct drm_device *dev = dev_priv->dev; 90 u32 reserved = 0; 91 92 /* On most chips, these bits must be preserved in software. */ 93 if (!IS_I830(dev) && !IS_845G(dev)) 94 reserved = I915_READ_NOTRACE(bus->gpio_reg) & 95 (GPIO_DATA_PULLUP_DISABLE | 96 GPIO_CLOCK_PULLUP_DISABLE); 97 98 return reserved; 99} 100 101static int get_clock(void *data) 102{ 103 struct intel_gmbus *bus = data; 104 struct drm_i915_private *dev_priv = bus->dev_priv; 105 u32 reserved = get_reserved(bus); 106 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 107 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 108 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 109} 110 111static int get_data(void *data) 112{ 113 struct intel_gmbus *bus = data; 114 struct drm_i915_private *dev_priv = bus->dev_priv; 115 u32 reserved = get_reserved(bus); 116 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 117 I915_WRITE_NOTRACE(bus->gpio_reg, reserved); 118 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 119} 120 121static void set_clock(void *data, int state_high) 122{ 123 struct intel_gmbus *bus = data; 124 struct drm_i915_private *dev_priv = bus->dev_priv; 125 u32 reserved = get_reserved(bus); 126 u32 clock_bits; 127 128 if (state_high) 129 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 130 else 131 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 132 GPIO_CLOCK_VAL_MASK; 133 134 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); 135 POSTING_READ(bus->gpio_reg); 136} 137 138static void set_data(void *data, int state_high) 139{ 140 struct intel_gmbus *bus = data; 141 struct drm_i915_private *dev_priv = bus->dev_priv; 142 u32 reserved = get_reserved(bus); 143 u32 data_bits; 144 145 if (state_high) 146 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 147 else 148 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 149 GPIO_DATA_VAL_MASK; 150 151 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); 152 POSTING_READ(bus->gpio_reg); 153} 154 155static int 156intel_gpio_pre_xfer(struct i2c_adapter *adapter) 157{ 158 struct intel_gmbus *bus = container_of(adapter, 159 struct intel_gmbus, 160 adapter); 161 struct drm_i915_private *dev_priv = bus->dev_priv; 162 163 intel_i2c_reset(dev_priv->dev); 164 intel_i2c_quirk_set(dev_priv, true); 165 set_data(bus, 1); 166 set_clock(bus, 1); 167 udelay(I2C_RISEFALL_TIME); 168 return 0; 169} 170 171static void 172intel_gpio_post_xfer(struct i2c_adapter *adapter) 173{ 174 struct intel_gmbus *bus = container_of(adapter, 175 struct intel_gmbus, 176 adapter); 177 struct drm_i915_private *dev_priv = bus->dev_priv; 178 179 set_data(bus, 1); 180 set_clock(bus, 1); 181 intel_i2c_quirk_set(dev_priv, false); 182} 183 184static void 185intel_gpio_setup(struct intel_gmbus *bus, u32 pin) 186{ 187 struct drm_i915_private *dev_priv = bus->dev_priv; 188 struct i2c_algo_bit_data *algo; 189 190 algo = &bus->bit_algo; 191 192 /* -1 to map pin pair to gmbus index */ 193 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; 194 195 bus->adapter.algo_data = algo; 196 algo->setsda = set_data; 197 algo->setscl = set_clock; 198 algo->getsda = get_data; 199 algo->getscl = get_clock; 200 algo->pre_xfer = intel_gpio_pre_xfer; 201 algo->post_xfer = intel_gpio_post_xfer; 202 algo->udelay = I2C_RISEFALL_TIME; 203 algo->timeout = usecs_to_jiffies(2200); 204 algo->data = bus; 205} 206 207static int 208gmbus_wait_hw_status(struct drm_i915_private *dev_priv, 209 u32 gmbus2_status, 210 u32 gmbus4_irq_en) 211{ 212 int i; 213 int reg_offset = dev_priv->gpio_mmio_base; 214 u32 gmbus2 = 0; 215 DEFINE_WAIT(wait); 216 217 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 218 gmbus4_irq_en = 0; 219 220 /* Important: The hw handles only the first bit, so set only one! Since 221 * we also need to check for NAKs besides the hw ready/idle signal, we 222 * need to wake up periodically and check that ourselves. */ 223 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); 224 225 for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { 226 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, 227 TASK_UNINTERRUPTIBLE); 228 229 gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset); 230 if (gmbus2 & (GMBUS_SATOER | gmbus2_status)) 231 break; 232 233 schedule_timeout(1); 234 } 235 finish_wait(&dev_priv->gmbus_wait_queue, &wait); 236 237 I915_WRITE(GMBUS4 + reg_offset, 0); 238 239 if (gmbus2 & GMBUS_SATOER) 240 return -ENXIO; 241 if (gmbus2 & gmbus2_status) 242 return 0; 243 return -ETIMEDOUT; 244} 245 246static int 247gmbus_wait_idle(struct drm_i915_private *dev_priv) 248{ 249 int ret; 250 int reg_offset = dev_priv->gpio_mmio_base; 251 252#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0) 253 254 if (!HAS_GMBUS_IRQ(dev_priv->dev)) 255 return wait_for(C, 10); 256 257 /* Important: The hw handles only the first bit, so set only one! */ 258 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); 259 260 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 261 msecs_to_jiffies_timeout(10)); 262 263 I915_WRITE(GMBUS4 + reg_offset, 0); 264 265 if (ret) 266 return 0; 267 else 268 return -ETIMEDOUT; 269#undef C 270} 271 272static int 273gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 274 unsigned short addr, u8 *buf, unsigned int len, 275 u32 gmbus1_index) 276{ 277 int reg_offset = dev_priv->gpio_mmio_base; 278 279 I915_WRITE(GMBUS1 + reg_offset, 280 gmbus1_index | 281 GMBUS_CYCLE_WAIT | 282 (len << GMBUS_BYTE_COUNT_SHIFT) | 283 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 284 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 285 while (len) { 286 int ret; 287 u32 val, loop = 0; 288 289 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 290 GMBUS_HW_RDY_EN); 291 if (ret) 292 return ret; 293 294 val = I915_READ(GMBUS3 + reg_offset); 295 do { 296 *buf++ = val & 0xff; 297 val >>= 8; 298 } while (--len && ++loop < 4); 299 } 300 301 return 0; 302} 303 304static int 305gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 306 u32 gmbus1_index) 307{ 308 u8 *buf = msg->buf; 309 unsigned int rx_size = msg->len; 310 unsigned int len; 311 int ret; 312 313 do { 314 len = min(rx_size, GMBUS_BYTE_COUNT_MAX); 315 316 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, 317 buf, len, gmbus1_index); 318 if (ret) 319 return ret; 320 321 rx_size -= len; 322 buf += len; 323 } while (rx_size != 0); 324 325 return 0; 326} 327 328static int 329gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 330 unsigned short addr, u8 *buf, unsigned int len) 331{ 332 int reg_offset = dev_priv->gpio_mmio_base; 333 unsigned int chunk_size = len; 334 u32 val, loop; 335 336 val = loop = 0; 337 while (len && loop < 4) { 338 val |= *buf++ << (8 * loop++); 339 len -= 1; 340 } 341 342 I915_WRITE(GMBUS3 + reg_offset, val); 343 I915_WRITE(GMBUS1 + reg_offset, 344 GMBUS_CYCLE_WAIT | 345 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | 346 (addr << GMBUS_SLAVE_ADDR_SHIFT) | 347 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 348 while (len) { 349 int ret; 350 351 val = loop = 0; 352 do { 353 val |= *buf++ << (8 * loop); 354 } while (--len && ++loop < 4); 355 356 I915_WRITE(GMBUS3 + reg_offset, val); 357 358 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY, 359 GMBUS_HW_RDY_EN); 360 if (ret) 361 return ret; 362 } 363 364 return 0; 365} 366 367static int 368gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) 369{ 370 u8 *buf = msg->buf; 371 unsigned int tx_size = msg->len; 372 unsigned int len; 373 int ret; 374 375 do { 376 len = min(tx_size, GMBUS_BYTE_COUNT_MAX); 377 378 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); 379 if (ret) 380 return ret; 381 382 buf += len; 383 tx_size -= len; 384 } while (tx_size != 0); 385 386 return 0; 387} 388 389/* 390 * The gmbus controller can combine a 1 or 2 byte write with a read that 391 * immediately follows it by using an "INDEX" cycle. 392 */ 393static bool 394gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) 395{ 396 return (i + 1 < num && 397 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && 398 (msgs[i + 1].flags & I2C_M_RD)); 399} 400 401static int 402gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) 403{ 404 int reg_offset = dev_priv->gpio_mmio_base; 405 u32 gmbus1_index = 0; 406 u32 gmbus5 = 0; 407 int ret; 408 409 if (msgs[0].len == 2) 410 gmbus5 = GMBUS_2BYTE_INDEX_EN | 411 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 412 if (msgs[0].len == 1) 413 gmbus1_index = GMBUS_CYCLE_INDEX | 414 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 415 416 /* GMBUS5 holds 16-bit index */ 417 if (gmbus5) 418 I915_WRITE(GMBUS5 + reg_offset, gmbus5); 419 420 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); 421 422 /* Clear GMBUS5 after each index transfer */ 423 if (gmbus5) 424 I915_WRITE(GMBUS5 + reg_offset, 0); 425 426 return ret; 427} 428 429static int 430gmbus_xfer(struct i2c_adapter *adapter, 431 struct i2c_msg *msgs, 432 int num) 433{ 434 struct intel_gmbus *bus = container_of(adapter, 435 struct intel_gmbus, 436 adapter); 437 struct drm_i915_private *dev_priv = bus->dev_priv; 438 int i = 0, inc, try = 0, reg_offset; 439 int ret = 0; 440 441 intel_aux_display_runtime_get(dev_priv); 442 mutex_lock(&dev_priv->gmbus_mutex); 443 444 if (bus->force_bit) { 445 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 446 goto out; 447 } 448 449 reg_offset = dev_priv->gpio_mmio_base; 450 451retry: 452 I915_WRITE(GMBUS0 + reg_offset, bus->reg0); 453 454 for (; i < num; i += inc) { 455 inc = 1; 456 if (gmbus_is_index_read(msgs, i, num)) { 457 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); 458 inc = 2; /* an index read is two msgs */ 459 } else if (msgs[i].flags & I2C_M_RD) { 460 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); 461 } else { 462 ret = gmbus_xfer_write(dev_priv, &msgs[i]); 463 } 464 465 if (ret == -ETIMEDOUT) 466 goto timeout; 467 if (ret == -ENXIO) 468 goto clear_err; 469 470 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE, 471 GMBUS_HW_WAIT_EN); 472 if (ret == -ENXIO) 473 goto clear_err; 474 if (ret) 475 goto timeout; 476 } 477 478 /* Generate a STOP condition on the bus. Note that gmbus can't generata 479 * a STOP on the very first cycle. To simplify the code we 480 * unconditionally generate the STOP condition with an additional gmbus 481 * cycle. */ 482 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 483 484 /* Mark the GMBUS interface as disabled after waiting for idle. 485 * We will re-enable it at the start of the next xfer, 486 * till then let it sleep. 487 */ 488 if (gmbus_wait_idle(dev_priv)) { 489 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", 490 adapter->name); 491 ret = -ETIMEDOUT; 492 } 493 I915_WRITE(GMBUS0 + reg_offset, 0); 494 ret = ret ?: i; 495 goto out; 496 497clear_err: 498 /* 499 * Wait for bus to IDLE before clearing NAK. 500 * If we clear the NAK while bus is still active, then it will stay 501 * active and the next transaction may fail. 502 * 503 * If no ACK is received during the address phase of a transaction, the 504 * adapter must report -ENXIO. It is not clear what to return if no ACK 505 * is received at other times. But we have to be careful to not return 506 * spurious -ENXIO because that will prevent i2c and drm edid functions 507 * from retrying. So return -ENXIO only when gmbus properly quiescents - 508 * timing out seems to happen when there _is_ a ddc chip present, but 509 * it's slow responding and only answers on the 2nd retry. 510 */ 511 ret = -ENXIO; 512 if (gmbus_wait_idle(dev_priv)) { 513 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", 514 adapter->name); 515 ret = -ETIMEDOUT; 516 } 517 518 /* Toggle the Software Clear Interrupt bit. This has the effect 519 * of resetting the GMBUS controller and so clearing the 520 * BUS_ERROR raised by the slave's NAK. 521 */ 522 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 523 I915_WRITE(GMBUS1 + reg_offset, 0); 524 I915_WRITE(GMBUS0 + reg_offset, 0); 525 526 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", 527 adapter->name, msgs[i].addr, 528 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 529 530 /* 531 * Passive adapters sometimes NAK the first probe. Retry the first 532 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 533 * has retries internally. See also the retry loop in 534 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 535 */ 536 if (ret == -ENXIO && i == 0 && try++ == 0) { 537 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", 538 adapter->name); 539 goto retry; 540 } 541 542 goto out; 543 544timeout: 545 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 546 bus->adapter.name, bus->reg0 & 0xff); 547 I915_WRITE(GMBUS0 + reg_offset, 0); 548 549 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ 550 bus->force_bit = 1; 551 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 552 553out: 554 mutex_unlock(&dev_priv->gmbus_mutex); 555 intel_aux_display_runtime_put(dev_priv); 556 return ret; 557} 558 559static u32 gmbus_func(struct i2c_adapter *adapter) 560{ 561 return i2c_bit_algo.functionality(adapter) & 562 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 563 /* I2C_FUNC_10BIT_ADDR | */ 564 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 565 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 566} 567 568static const struct i2c_algorithm gmbus_algorithm = { 569 .master_xfer = gmbus_xfer, 570 .functionality = gmbus_func 571}; 572 573/** 574 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 575 * @dev: DRM device 576 */ 577int intel_setup_gmbus(struct drm_device *dev) 578{ 579 struct drm_i915_private *dev_priv = dev->dev_private; 580 int ret, i; 581 582 if (HAS_PCH_NOP(dev)) 583 return 0; 584 else if (HAS_PCH_SPLIT(dev)) 585 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; 586 else if (IS_VALLEYVIEW(dev)) 587 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 588 else 589 dev_priv->gpio_mmio_base = 0; 590 591 mutex_init(&dev_priv->gmbus_mutex); 592 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 593 594 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 595 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 596 u32 port = i + 1; /* +1 to map gmbus index to pin pair */ 597 598 bus->adapter.owner = THIS_MODULE; 599 bus->adapter.class = I2C_CLASS_DDC; 600 snprintf(bus->adapter.name, 601 sizeof(bus->adapter.name), 602 "i915 gmbus %s", 603 gmbus_ports[i].name); 604 605 bus->adapter.dev.parent = &dev->pdev->dev; 606 bus->dev_priv = dev_priv; 607 608 bus->adapter.algo = &gmbus_algorithm; 609 610 /* By default use a conservative clock rate */ 611 bus->reg0 = port | GMBUS_RATE_100KHZ; 612 613 /* gmbus seems to be broken on i830 */ 614 if (IS_I830(dev)) 615 bus->force_bit = 1; 616 617 intel_gpio_setup(bus, port); 618 619 ret = i2c_add_adapter(&bus->adapter); 620 if (ret) 621 goto err; 622 } 623 624 intel_i2c_reset(dev_priv->dev); 625 626 return 0; 627 628err: 629 while (--i) { 630 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 631 i2c_del_adapter(&bus->adapter); 632 } 633 return ret; 634} 635 636struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 637 unsigned port) 638{ 639 WARN_ON(!intel_gmbus_is_port_valid(port)); 640 /* -1 to map pin pair to gmbus index */ 641 return (intel_gmbus_is_port_valid(port)) ? 642 &dev_priv->gmbus[port - 1].adapter : NULL; 643} 644 645void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 646{ 647 struct intel_gmbus *bus = to_intel_gmbus(adapter); 648 649 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 650} 651 652void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 653{ 654 struct intel_gmbus *bus = to_intel_gmbus(adapter); 655 656 bus->force_bit += force_bit ? 1 : -1; 657 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", 658 force_bit ? "en" : "dis", adapter->name, 659 bus->force_bit); 660} 661 662void intel_teardown_gmbus(struct drm_device *dev) 663{ 664 struct drm_i915_private *dev_priv = dev->dev_private; 665 int i; 666 667 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 668 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 669 i2c_del_adapter(&bus->adapter); 670 } 671} 672