1#ifndef A3XX_XML 2#define A3XX_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 15085 bytes, from 2014-12-20 21:49:41) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 64344 bytes, from 2014-12-12 20:22:26) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 51069 bytes, from 2014-12-21 15:51:54) 18 19Copyright (C) 2013-2014 by the following authors: 20- Rob Clark <robdclark@gmail.com> (robclark) 21 22Permission is hereby granted, free of charge, to any person obtaining 23a copy of this software and associated documentation files (the 24"Software"), to deal in the Software without restriction, including 25without limitation the rights to use, copy, modify, merge, publish, 26distribute, sublicense, and/or sell copies of the Software, and to 27permit persons to whom the Software is furnished to do so, subject to 28the following conditions: 29 30The above copyright notice and this permission notice (including the 31next paragraph) shall be included in all copies or substantial 32portions of the Software. 33 34THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 37IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 38LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 39OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 40WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 41*/ 42 43 44enum a3xx_tile_mode { 45 LINEAR = 0, 46 TILE_32X32 = 2, 47}; 48 49enum a3xx_state_block_id { 50 HLSQ_BLOCK_ID_TP_TEX = 2, 51 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 52 HLSQ_BLOCK_ID_SP_VS = 4, 53 HLSQ_BLOCK_ID_SP_FS = 6, 54}; 55 56enum a3xx_cache_opcode { 57 INVALIDATE = 1, 58}; 59 60enum a3xx_vtx_fmt { 61 VFMT_32_FLOAT = 0, 62 VFMT_32_32_FLOAT = 1, 63 VFMT_32_32_32_FLOAT = 2, 64 VFMT_32_32_32_32_FLOAT = 3, 65 VFMT_16_FLOAT = 4, 66 VFMT_16_16_FLOAT = 5, 67 VFMT_16_16_16_FLOAT = 6, 68 VFMT_16_16_16_16_FLOAT = 7, 69 VFMT_32_FIXED = 8, 70 VFMT_32_32_FIXED = 9, 71 VFMT_32_32_32_FIXED = 10, 72 VFMT_32_32_32_32_FIXED = 11, 73 VFMT_16_SINT = 16, 74 VFMT_16_16_SINT = 17, 75 VFMT_16_16_16_SINT = 18, 76 VFMT_16_16_16_16_SINT = 19, 77 VFMT_16_UINT = 20, 78 VFMT_16_16_UINT = 21, 79 VFMT_16_16_16_UINT = 22, 80 VFMT_16_16_16_16_UINT = 23, 81 VFMT_16_SNORM = 24, 82 VFMT_16_16_SNORM = 25, 83 VFMT_16_16_16_SNORM = 26, 84 VFMT_16_16_16_16_SNORM = 27, 85 VFMT_16_UNORM = 28, 86 VFMT_16_16_UNORM = 29, 87 VFMT_16_16_16_UNORM = 30, 88 VFMT_16_16_16_16_UNORM = 31, 89 VFMT_32_UINT = 32, 90 VFMT_32_32_UINT = 33, 91 VFMT_32_32_32_UINT = 34, 92 VFMT_32_32_32_32_UINT = 35, 93 VFMT_32_SINT = 36, 94 VFMT_32_32_SINT = 37, 95 VFMT_32_32_32_SINT = 38, 96 VFMT_32_32_32_32_SINT = 39, 97 VFMT_8_UINT = 40, 98 VFMT_8_8_UINT = 41, 99 VFMT_8_8_8_UINT = 42, 100 VFMT_8_8_8_8_UINT = 43, 101 VFMT_8_UNORM = 44, 102 VFMT_8_8_UNORM = 45, 103 VFMT_8_8_8_UNORM = 46, 104 VFMT_8_8_8_8_UNORM = 47, 105 VFMT_8_SINT = 48, 106 VFMT_8_8_SINT = 49, 107 VFMT_8_8_8_SINT = 50, 108 VFMT_8_8_8_8_SINT = 51, 109 VFMT_8_SNORM = 52, 110 VFMT_8_8_SNORM = 53, 111 VFMT_8_8_8_SNORM = 54, 112 VFMT_8_8_8_8_SNORM = 55, 113 VFMT_10_10_10_2_UINT = 60, 114 VFMT_10_10_10_2_UNORM = 61, 115 VFMT_10_10_10_2_SINT = 62, 116 VFMT_10_10_10_2_SNORM = 63, 117}; 118 119enum a3xx_tex_fmt { 120 TFMT_5_6_5_UNORM = 4, 121 TFMT_5_5_5_1_UNORM = 5, 122 TFMT_4_4_4_4_UNORM = 7, 123 TFMT_Z16_UNORM = 9, 124 TFMT_X8Z24_UNORM = 10, 125 TFMT_Z32_FLOAT = 11, 126 TFMT_NV12_UV_TILED = 17, 127 TFMT_NV12_Y_TILED = 19, 128 TFMT_NV12_UV = 21, 129 TFMT_NV12_Y = 23, 130 TFMT_I420_Y = 24, 131 TFMT_I420_U = 26, 132 TFMT_I420_V = 27, 133 TFMT_DXT1 = 36, 134 TFMT_DXT3 = 37, 135 TFMT_DXT5 = 38, 136 TFMT_10_10_10_2_UNORM = 41, 137 TFMT_9_9_9_E5_FLOAT = 42, 138 TFMT_11_11_10_FLOAT = 43, 139 TFMT_A8_UNORM = 44, 140 TFMT_L8_A8_UNORM = 47, 141 TFMT_8_UNORM = 48, 142 TFMT_8_8_UNORM = 49, 143 TFMT_8_8_8_UNORM = 50, 144 TFMT_8_8_8_8_UNORM = 51, 145 TFMT_8_SNORM = 52, 146 TFMT_8_8_SNORM = 53, 147 TFMT_8_8_8_SNORM = 54, 148 TFMT_8_8_8_8_SNORM = 55, 149 TFMT_8_UINT = 56, 150 TFMT_8_8_UINT = 57, 151 TFMT_8_8_8_UINT = 58, 152 TFMT_8_8_8_8_UINT = 59, 153 TFMT_8_SINT = 60, 154 TFMT_8_8_SINT = 61, 155 TFMT_8_8_8_SINT = 62, 156 TFMT_8_8_8_8_SINT = 63, 157 TFMT_16_FLOAT = 64, 158 TFMT_16_16_FLOAT = 65, 159 TFMT_16_16_16_16_FLOAT = 67, 160 TFMT_16_UINT = 68, 161 TFMT_16_16_UINT = 69, 162 TFMT_16_16_16_16_UINT = 71, 163 TFMT_16_SINT = 72, 164 TFMT_16_16_SINT = 73, 165 TFMT_16_16_16_16_SINT = 75, 166 TFMT_16_UNORM = 76, 167 TFMT_16_16_UNORM = 77, 168 TFMT_16_16_16_16_UNORM = 79, 169 TFMT_16_SNORM = 80, 170 TFMT_16_16_SNORM = 81, 171 TFMT_16_16_16_16_SNORM = 83, 172 TFMT_32_FLOAT = 84, 173 TFMT_32_32_FLOAT = 85, 174 TFMT_32_32_32_32_FLOAT = 87, 175 TFMT_32_UINT = 88, 176 TFMT_32_32_UINT = 89, 177 TFMT_32_32_32_32_UINT = 91, 178 TFMT_32_SINT = 92, 179 TFMT_32_32_SINT = 93, 180 TFMT_32_32_32_32_SINT = 95, 181 TFMT_RGTC2_SNORM = 112, 182 TFMT_RGTC2_UNORM = 113, 183 TFMT_RGTC1_SNORM = 114, 184 TFMT_RGTC1_UNORM = 115, 185}; 186 187enum a3xx_tex_fetchsize { 188 TFETCH_DISABLE = 0, 189 TFETCH_1_BYTE = 1, 190 TFETCH_2_BYTE = 2, 191 TFETCH_4_BYTE = 3, 192 TFETCH_8_BYTE = 4, 193 TFETCH_16_BYTE = 5, 194}; 195 196enum a3xx_color_fmt { 197 RB_R5G6B5_UNORM = 0, 198 RB_R5G5B5A1_UNORM = 1, 199 RB_R4G4B4A4_UNORM = 3, 200 RB_R8G8B8_UNORM = 4, 201 RB_R8G8B8A8_UNORM = 8, 202 RB_R8G8B8A8_SNORM = 9, 203 RB_R8G8B8A8_UINT = 10, 204 RB_R8G8B8A8_SINT = 11, 205 RB_R8G8_UNORM = 12, 206 RB_R8G8_SNORM = 13, 207 RB_R8_UINT = 14, 208 RB_R8_SINT = 15, 209 RB_R10G10B10A2_UNORM = 16, 210 RB_A8_UNORM = 20, 211 RB_R8_UNORM = 21, 212 RB_R16G16B16A16_FLOAT = 27, 213 RB_R11G11B10_FLOAT = 28, 214 RB_R16_SINT = 40, 215 RB_R16G16_SINT = 41, 216 RB_R16G16B16A16_SINT = 43, 217 RB_R16_UINT = 44, 218 RB_R16G16_UINT = 45, 219 RB_R16G16B16A16_UINT = 47, 220 RB_R32G32B32A32_FLOAT = 51, 221 RB_R32_SINT = 52, 222 RB_R32G32_SINT = 53, 223 RB_R32G32B32A32_SINT = 55, 224 RB_R32_UINT = 56, 225 RB_R32G32_UINT = 57, 226 RB_R32G32B32A32_UINT = 59, 227}; 228 229enum a3xx_sp_perfcounter_select { 230 SP_FS_CFLOW_INSTRUCTIONS = 12, 231 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 232 SP0_ICL1_MISSES = 26, 233 SP_ALU_ACTIVE_CYCLES = 29, 234}; 235 236enum a3xx_rop_code { 237 ROP_CLEAR = 0, 238 ROP_NOR = 1, 239 ROP_AND_INVERTED = 2, 240 ROP_COPY_INVERTED = 3, 241 ROP_AND_REVERSE = 4, 242 ROP_INVERT = 5, 243 ROP_XOR = 6, 244 ROP_NAND = 7, 245 ROP_AND = 8, 246 ROP_EQUIV = 9, 247 ROP_NOOP = 10, 248 ROP_OR_INVERTED = 11, 249 ROP_COPY = 12, 250 ROP_OR_REVERSE = 13, 251 ROP_OR = 14, 252 ROP_SET = 15, 253}; 254 255enum a3xx_rb_blend_opcode { 256 BLEND_DST_PLUS_SRC = 0, 257 BLEND_SRC_MINUS_DST = 1, 258 BLEND_DST_MINUS_SRC = 2, 259 BLEND_MIN_DST_SRC = 3, 260 BLEND_MAX_DST_SRC = 4, 261}; 262 263enum a3xx_intp_mode { 264 SMOOTH = 0, 265 FLAT = 1, 266}; 267 268enum a3xx_tex_filter { 269 A3XX_TEX_NEAREST = 0, 270 A3XX_TEX_LINEAR = 1, 271 A3XX_TEX_ANISO = 2, 272}; 273 274enum a3xx_tex_clamp { 275 A3XX_TEX_REPEAT = 0, 276 A3XX_TEX_CLAMP_TO_EDGE = 1, 277 A3XX_TEX_MIRROR_REPEAT = 2, 278 A3XX_TEX_CLAMP_TO_BORDER = 3, 279 A3XX_TEX_MIRROR_CLAMP = 4, 280}; 281 282enum a3xx_tex_aniso { 283 A3XX_TEX_ANISO_1 = 0, 284 A3XX_TEX_ANISO_2 = 1, 285 A3XX_TEX_ANISO_4 = 2, 286 A3XX_TEX_ANISO_8 = 3, 287 A3XX_TEX_ANISO_16 = 4, 288}; 289 290enum a3xx_tex_swiz { 291 A3XX_TEX_X = 0, 292 A3XX_TEX_Y = 1, 293 A3XX_TEX_Z = 2, 294 A3XX_TEX_W = 3, 295 A3XX_TEX_ZERO = 4, 296 A3XX_TEX_ONE = 5, 297}; 298 299enum a3xx_tex_type { 300 A3XX_TEX_1D = 0, 301 A3XX_TEX_2D = 1, 302 A3XX_TEX_CUBE = 2, 303 A3XX_TEX_3D = 3, 304}; 305 306#define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 307#define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 308#define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 309#define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 310#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 311#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 312#define A3XX_INT0_VFD_ERROR 0x00000040 313#define A3XX_INT0_CP_SW_INT 0x00000080 314#define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 315#define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 316#define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 317#define A3XX_INT0_CP_HW_FAULT 0x00000800 318#define A3XX_INT0_CP_DMA 0x00001000 319#define A3XX_INT0_CP_IB2_INT 0x00002000 320#define A3XX_INT0_CP_IB1_INT 0x00004000 321#define A3XX_INT0_CP_RB_INT 0x00008000 322#define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 323#define A3XX_INT0_CP_RB_DONE_TS 0x00020000 324#define A3XX_INT0_CP_VS_DONE_TS 0x00040000 325#define A3XX_INT0_CP_PS_DONE_TS 0x00080000 326#define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 327#define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 328#define A3XX_INT0_MISC_HANG_DETECT 0x01000000 329#define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 330#define REG_A3XX_RBBM_HW_VERSION 0x00000000 331 332#define REG_A3XX_RBBM_HW_RELEASE 0x00000001 333 334#define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 335 336#define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 337 338#define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 339 340#define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 341 342#define REG_A3XX_RBBM_AHB_CTL0 0x00000020 343 344#define REG_A3XX_RBBM_AHB_CTL1 0x00000021 345 346#define REG_A3XX_RBBM_AHB_CMD 0x00000022 347 348#define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 349 350#define REG_A3XX_RBBM_GPR0_CTL 0x0000002e 351 352#define REG_A3XX_RBBM_STATUS 0x00000030 353#define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 354#define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 355#define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 356#define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 357#define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 358#define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 359#define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 360#define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 361#define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 362#define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 363#define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 364#define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 365#define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 366#define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 367#define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 368#define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 369#define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 370#define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 371#define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 372#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 373#define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 374 375#define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 376 377#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 378 379#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 380 381#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 382 383#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 384 385#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 386 387#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 388 389#define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 390 391#define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 392 393#define REG_A3XX_RBBM_INT_0_MASK 0x00000063 394 395#define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 396 397#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 398#define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 399 400#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 401 402#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 403 404#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 405 406#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 407 408#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 409 410#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 411 412#define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 413 414#define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 415 416#define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 417 418#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 419 420#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 421 422#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 423 424#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 425 426#define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 427 428#define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 429 430#define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 431 432#define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 433 434#define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a 435 436#define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b 437 438#define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c 439 440#define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d 441 442#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e 443 444#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f 445 446#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 447 448#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 449 450#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 451 452#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 453 454#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 455 456#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 457 458#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 459 460#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 461 462#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 463 464#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 465 466#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa 467 468#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab 469 470#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac 471 472#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad 473 474#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae 475 476#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af 477 478#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 479 480#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 481 482#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 483 484#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 485 486#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 487 488#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 489 490#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 491 492#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 493 494#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 495 496#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 497 498#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba 499 500#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb 501 502#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc 503 504#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd 505 506#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be 507 508#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf 509 510#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 511 512#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 513 514#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 515 516#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 517 518#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 519 520#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 521 522#define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 523 524#define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 525 526#define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 527 528#define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 529 530#define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca 531 532#define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb 533 534#define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc 535 536#define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd 537 538#define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce 539 540#define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf 541 542#define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 543 544#define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 545 546#define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 547 548#define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 549 550#define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 551 552#define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 553 554#define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 555 556#define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 557 558#define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 559 560#define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 561 562#define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da 563 564#define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db 565 566#define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc 567 568#define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd 569 570#define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de 571 572#define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df 573 574#define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 575 576#define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 577 578#define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 579 580#define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 581 582#define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 583 584#define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 585 586#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea 587 588#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb 589 590#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec 591 592#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed 593 594#define REG_A3XX_RBBM_RBBM_CTL 0x00000100 595 596#define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 597 598#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 599 600#define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 601 602#define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca 603 604#define REG_A3XX_CP_ROQ_ADDR 0x000001cc 605 606#define REG_A3XX_CP_ROQ_DATA 0x000001cd 607 608#define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 609 610#define REG_A3XX_CP_MERCIU_DATA 0x000001d2 611 612#define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 613 614#define REG_A3XX_CP_MEQ_ADDR 0x000001da 615 616#define REG_A3XX_CP_MEQ_DATA 0x000001db 617 618#define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 619 620#define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d 621 622#define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 623 624#define REG_A3XX_CP_HW_FAULT 0x0000045c 625 626#define REG_A3XX_CP_PROTECT_CTRL 0x0000045e 627 628#define REG_A3XX_CP_PROTECT_STATUS 0x0000045f 629 630static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } 631 632static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } 633 634#define REG_A3XX_CP_AHB_FAULT 0x0000054d 635 636#define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 637 638#define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 639 640#define REG_A3XX_TP0_CHICKEN 0x00000e1e 641 642#define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 643 644#define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 645 646#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 647#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 648#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 649#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 650#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 651#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 652#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 653#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 654#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 655#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 656 657#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 658#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 659#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 660static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) 661{ 662 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; 663} 664#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 665#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 666static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) 667{ 668 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; 669} 670 671#define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 672#define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff 673#define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 674static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) 675{ 676 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; 677} 678 679#define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 680#define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff 681#define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 682static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) 683{ 684 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; 685} 686 687#define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a 688#define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff 689#define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 690static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) 691{ 692 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; 693} 694 695#define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b 696#define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff 697#define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 698static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) 699{ 700 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; 701} 702 703#define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c 704#define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff 705#define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 706static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) 707{ 708 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; 709} 710 711#define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d 712#define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff 713#define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 714static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) 715{ 716 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; 717} 718 719#define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 720#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 721#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 722static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) 723{ 724 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; 725} 726#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 727#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 728static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) 729{ 730 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; 731} 732 733#define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 734#define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff 735#define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 736static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) 737{ 738 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; 739} 740 741#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 742#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 743#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 744static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) 745{ 746 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; 747} 748 749#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d 750#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff 751#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 752static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) 753{ 754 return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; 755} 756 757#define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 758#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 759#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 760#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 761#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 762#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 763static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) 764{ 765 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; 766} 767#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 768 769#define REG_A3XX_GRAS_SC_CONTROL 0x00002072 770#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 771#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 772static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 773{ 774 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; 775} 776#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 777#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 778static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) 779{ 780 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; 781} 782#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 783#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 784static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) 785{ 786 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; 787} 788 789#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 790#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 791#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 792#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 793static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 794{ 795 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; 796} 797#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 798#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 799static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 800{ 801 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; 802} 803 804#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 805#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 806#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 807#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 808static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 809{ 810 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; 811} 812#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 813#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 814static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 815{ 816 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; 817} 818 819#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 820#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 821#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 822#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 823static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 824{ 825 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; 826} 827#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 828#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 829static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 830{ 831 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; 832} 833 834#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a 835#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 836#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 837#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 838static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 839{ 840 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; 841} 842#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 843#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 844static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 845{ 846 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; 847} 848 849#define REG_A3XX_RB_MODE_CONTROL 0x000020c0 850#define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 851#define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 852#define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 853static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) 854{ 855 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; 856} 857#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 858#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 859 860#define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 861#define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 862#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 863#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 864static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 865{ 866 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; 867} 868#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 869#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 870#define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000 871#define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 872#define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 873#define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 874#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 875#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 876#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 877static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) 878{ 879 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; 880} 881 882#define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 883#define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 884#define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 885#define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 886static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) 887{ 888 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; 889} 890#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 891#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 892static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) 893{ 894 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; 895} 896 897#define REG_A3XX_RB_ALPHA_REF 0x000020c3 898#define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 899#define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 900static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) 901{ 902 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; 903} 904#define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 905#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 906static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) 907{ 908 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; 909} 910 911static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 912 913static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } 914#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 915#define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 916#define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 917#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 918#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 919static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) 920{ 921 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 922} 923#define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 924#define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 925static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 926{ 927 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; 928} 929#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 930#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 931static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) 932{ 933 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; 934} 935 936static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } 937#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f 938#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 939static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) 940{ 941 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; 942} 943#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 944#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 945static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) 946{ 947 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; 948} 949#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 950#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 951static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) 952{ 953 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; 954} 955#define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 956#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 957#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 958static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) 959{ 960 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; 961} 962 963static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } 964#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 965#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 966static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) 967{ 968 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; 969} 970 971static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } 972#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f 973#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 974static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) 975{ 976 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; 977} 978#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 979#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 980static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 981{ 982 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 983} 984#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 985#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 986static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) 987{ 988 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; 989} 990#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 991#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 992static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) 993{ 994 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; 995} 996#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 997#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 998static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) 999{ 1000 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 1001} 1002#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 1003#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 1004static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) 1005{ 1006 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; 1007} 1008#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 1009 1010#define REG_A3XX_RB_BLEND_RED 0x000020e4 1011#define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff 1012#define A3XX_RB_BLEND_RED_UINT__SHIFT 0 1013static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) 1014{ 1015 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; 1016} 1017#define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 1018#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 1019static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) 1020{ 1021 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; 1022} 1023 1024#define REG_A3XX_RB_BLEND_GREEN 0x000020e5 1025#define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff 1026#define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 1027static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) 1028{ 1029 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; 1030} 1031#define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 1032#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 1033static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) 1034{ 1035 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; 1036} 1037 1038#define REG_A3XX_RB_BLEND_BLUE 0x000020e6 1039#define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff 1040#define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 1041static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) 1042{ 1043 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; 1044} 1045#define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 1046#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 1047static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) 1048{ 1049 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; 1050} 1051 1052#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 1053#define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff 1054#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 1055static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) 1056{ 1057 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; 1058} 1059#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 1060#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 1061static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) 1062{ 1063 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 1064} 1065 1066#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 1067 1068#define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 1069 1070#define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea 1071 1072#define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb 1073 1074#define REG_A3XX_RB_COPY_CONTROL 0x000020ec 1075#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 1076#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 1077static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) 1078{ 1079 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 1080} 1081#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 1082#define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 1083#define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 1084static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 1085{ 1086 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 1087} 1088#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 1089#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 1090static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) 1091{ 1092 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; 1093} 1094#define A3XX_RB_COPY_CONTROL_UNK12 0x00001000 1095#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 1096#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 1097static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1098{ 1099 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1100} 1101 1102#define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1103#define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 1104#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 1105static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) 1106{ 1107 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; 1108} 1109 1110#define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee 1111#define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff 1112#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 1113static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) 1114{ 1115 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; 1116} 1117 1118#define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef 1119#define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 1120#define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 1121static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) 1122{ 1123 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; 1124} 1125#define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc 1126#define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 1127static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) 1128{ 1129 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; 1130} 1131#define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 1132#define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 1133static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) 1134{ 1135 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1136} 1137#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 1138#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 1139static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 1140{ 1141 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 1142} 1143#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1144#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1145static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1146{ 1147 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; 1148} 1149#define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 1150#define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 1151static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) 1152{ 1153 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; 1154} 1155 1156#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1157#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 1158#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1159#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1160#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1161#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 1162#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 1163static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) 1164{ 1165 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; 1166} 1167#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1168#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1169 1170#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 1171 1172#define REG_A3XX_RB_DEPTH_INFO 0x00002102 1173#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 1174#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1175static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1176{ 1177 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1178} 1179#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 1180#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1181static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1182{ 1183 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1184} 1185 1186#define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1187#define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff 1188#define A3XX_RB_DEPTH_PITCH__SHIFT 0 1189static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) 1190{ 1191 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; 1192} 1193 1194#define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 1195#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 1196#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 1197#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 1198#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 1199#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 1200static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) 1201{ 1202 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; 1203} 1204#define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 1205#define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 1206static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) 1207{ 1208 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; 1209} 1210#define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 1211#define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 1212static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) 1213{ 1214 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; 1215} 1216#define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 1217#define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 1218static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) 1219{ 1220 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; 1221} 1222#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 1223#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 1224static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) 1225{ 1226 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; 1227} 1228#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 1229#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 1230static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) 1231{ 1232 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; 1233} 1234#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 1235#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 1236static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) 1237{ 1238 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; 1239} 1240#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 1241#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 1242static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) 1243{ 1244 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1245} 1246 1247#define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 1248 1249#define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106 1250 1251#define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107 1252 1253#define REG_A3XX_RB_STENCILREFMASK 0x00002108 1254#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1255#define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1256static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1257{ 1258 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; 1259} 1260#define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1261#define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1262static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1263{ 1264 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1265} 1266#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1267#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1268static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1269{ 1270 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1271} 1272 1273#define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 1274#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1275#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1276static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1277{ 1278 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1279} 1280#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1281#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1282static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1283{ 1284 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1285} 1286#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1287#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1288static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1289{ 1290 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1291} 1292 1293#define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c 1294#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 1295 1296#define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e 1297#define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff 1298#define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 1299static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) 1300{ 1301 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; 1302} 1303#define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 1304#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 1305static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) 1306{ 1307 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; 1308} 1309 1310#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1311#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 1312#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 1313 1314#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1315 1316#define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 1317 1318#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1319 1320#define REG_A3XX_VGT_BIN_BASE 0x000021e1 1321 1322#define REG_A3XX_VGT_BIN_SIZE 0x000021e2 1323 1324#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1325#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 1326#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 1327static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) 1328{ 1329 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; 1330} 1331#define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 1332#define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 1333static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) 1334{ 1335 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; 1336} 1337 1338#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1339 1340#define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec 1341#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f 1342#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 1343static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) 1344{ 1345 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; 1346} 1347#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 1348#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 1349static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 1350{ 1351 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; 1352} 1353#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 1354#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 1355static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 1356{ 1357 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1358} 1359#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 1360#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1361#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 1362 1363#define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1364 1365#define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 1366#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010 1367#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 1368static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) 1369{ 1370 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; 1371} 1372#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 1373#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 1374#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 1375#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 1376#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 1377#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 1378static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) 1379{ 1380 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; 1381} 1382#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 1383#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 1384#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 1385#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 1386 1387#define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 1388#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040 1389#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 1390static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) 1391{ 1392 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; 1393} 1394#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1395#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1396#define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000 1397 1398#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1399#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1400#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 1401static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) 1402{ 1403 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; 1404} 1405 1406#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1407#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff 1408#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0 1409static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val) 1410{ 1411 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK; 1412} 1413 1414#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1415#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1416#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1417static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1418{ 1419 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; 1420} 1421#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1422#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1423static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1424{ 1425 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1426} 1427#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1428#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1429static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1430{ 1431 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; 1432} 1433 1434#define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 1435#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1436#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 1437static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) 1438{ 1439 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; 1440} 1441#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x00fff000 1442#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 1443static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) 1444{ 1445 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; 1446} 1447#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 1448#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 1449static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) 1450{ 1451 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; 1452} 1453 1454#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 1455#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1456#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1457static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1458{ 1459 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; 1460} 1461#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1462#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1463static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1464{ 1465 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; 1466} 1467 1468#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 1469#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x0000ffff 1470#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 1471static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) 1472{ 1473 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; 1474} 1475#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0xffff0000 1476#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 1477static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) 1478{ 1479 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; 1480} 1481 1482#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1483#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 1484#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 1485static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) 1486{ 1487 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; 1488} 1489#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc 1490#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 1491static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) 1492{ 1493 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; 1494} 1495#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 1496#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 1497static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) 1498{ 1499 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; 1500} 1501#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 1502#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 1503static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) 1504{ 1505 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; 1506} 1507 1508static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1509 1510static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } 1511 1512static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } 1513 1514#define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1515 1516#define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 1517 1518#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1519 1520static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1521 1522static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } 1523 1524#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1525 1526#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1527 1528#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1529 1530#define REG_A3XX_VFD_CONTROL_0 0x00002240 1531#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff 1532#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 1533static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) 1534{ 1535 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; 1536} 1537#define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 1538#define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 1539static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) 1540{ 1541 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; 1542} 1543#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 1544#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 1545static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) 1546{ 1547 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; 1548} 1549#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 1550#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 1551static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) 1552{ 1553 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; 1554} 1555 1556#define REG_A3XX_VFD_CONTROL_1 0x00002241 1557#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff 1558#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 1559static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) 1560{ 1561 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; 1562} 1563#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 1564#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 1565static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) 1566{ 1567 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; 1568} 1569#define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 1570#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 1571static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) 1572{ 1573 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; 1574} 1575 1576#define REG_A3XX_VFD_INDEX_MIN 0x00002242 1577 1578#define REG_A3XX_VFD_INDEX_MAX 0x00002243 1579 1580#define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 1581 1582#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1583 1584#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 1585 1586static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1587 1588static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } 1589#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f 1590#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 1591static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) 1592{ 1593 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; 1594} 1595#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80 1596#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 1597static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) 1598{ 1599 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; 1600} 1601#define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000 1602#define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 1603#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 1604#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 1605static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) 1606{ 1607 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; 1608} 1609#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 1610#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 1611static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) 1612{ 1613 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; 1614} 1615 1616static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } 1617 1618static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1619 1620static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } 1621#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f 1622#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 1623static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) 1624{ 1625 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; 1626} 1627#define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 1628#define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 1629#define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 1630static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) 1631{ 1632 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; 1633} 1634#define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 1635#define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 1636static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) 1637{ 1638 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1639} 1640#define A3XX_VFD_DECODE_INSTR_INT 0x00100000 1641#define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 1642#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 1643static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) 1644{ 1645 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; 1646} 1647#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1648#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1649static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1650{ 1651 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; 1652} 1653#define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 1654#define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 1655 1656#define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e 1657#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f 1658#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 1659static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) 1660{ 1661 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; 1662} 1663#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 1664#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 1665static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) 1666{ 1667 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; 1668} 1669 1670#define REG_A3XX_VPC_ATTR 0x00002280 1671#define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff 1672#define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1673static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1674{ 1675 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1676} 1677#define A3XX_VPC_ATTR_PSIZE 0x00000200 1678#define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1679#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1680static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1681{ 1682 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; 1683} 1684#define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 1685#define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 1686static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) 1687{ 1688 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; 1689} 1690 1691#define REG_A3XX_VPC_PACK 0x00002281 1692#define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 1693#define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 1694static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) 1695{ 1696 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; 1697} 1698#define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 1699#define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 1700static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) 1701{ 1702 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; 1703} 1704 1705static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1706 1707static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } 1708#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 1709#define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 1710static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) 1711{ 1712 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; 1713} 1714#define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c 1715#define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 1716static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) 1717{ 1718 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; 1719} 1720#define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 1721#define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 1722static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) 1723{ 1724 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; 1725} 1726#define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 1727#define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 1728static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) 1729{ 1730 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; 1731} 1732#define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 1733#define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 1734static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) 1735{ 1736 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; 1737} 1738#define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 1739#define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 1740static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) 1741{ 1742 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; 1743} 1744#define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 1745#define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 1746static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) 1747{ 1748 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; 1749} 1750#define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 1751#define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 1752static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) 1753{ 1754 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; 1755} 1756#define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 1757#define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 1758static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) 1759{ 1760 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; 1761} 1762#define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 1763#define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 1764static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) 1765{ 1766 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; 1767} 1768#define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 1769#define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 1770static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) 1771{ 1772 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; 1773} 1774#define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 1775#define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 1776static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) 1777{ 1778 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; 1779} 1780#define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 1781#define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 1782static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) 1783{ 1784 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; 1785} 1786#define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 1787#define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 1788static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) 1789{ 1790 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; 1791} 1792#define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 1793#define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 1794static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) 1795{ 1796 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; 1797} 1798#define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 1799#define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 1800static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) 1801{ 1802 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; 1803} 1804 1805static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1806 1807static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } 1808 1809#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a 1810 1811#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b 1812 1813#define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1814#define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1815#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 1816#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1817static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1818{ 1819 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1820} 1821#define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 1822#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1823#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1824static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1825{ 1826 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1827} 1828#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 1829#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 1830static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) 1831{ 1832 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; 1833} 1834 1835#define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1836#define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 1837#define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 1838static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 1839{ 1840 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; 1841} 1842#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 1843#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 1844static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 1845{ 1846 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; 1847} 1848#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 1849#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 1850#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 1851static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 1852{ 1853 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 1854} 1855#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 1856#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 1857static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 1858{ 1859 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 1860} 1861#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 1862#define A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 1863static inline uint32_t A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 1864{ 1865 return ((val) << A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK; 1866} 1867#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 1868#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 1869static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 1870{ 1871 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; 1872} 1873#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1874#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1875#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000 1876#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 1877#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 1878static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 1879{ 1880 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; 1881} 1882 1883#define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 1884#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 1885#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 1886static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) 1887{ 1888 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; 1889} 1890#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 1891#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 1892static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 1893{ 1894 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; 1895} 1896#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 1897#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 1898static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 1899{ 1900 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; 1901} 1902 1903#define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 1904#define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff 1905#define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 1906static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) 1907{ 1908 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; 1909} 1910#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 1911#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 1912static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) 1913{ 1914 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; 1915} 1916#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000 1917#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 1918static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) 1919{ 1920 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; 1921} 1922 1923static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1924 1925static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } 1926#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff 1927#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 1928static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) 1929{ 1930 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; 1931} 1932#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 1933#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 1934static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) 1935{ 1936 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; 1937} 1938#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000 1939#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 1940static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) 1941{ 1942 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; 1943} 1944#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 1945#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 1946static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) 1947{ 1948 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; 1949} 1950 1951static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1952 1953static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } 1954#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff 1955#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 1956static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) 1957{ 1958 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; 1959} 1960#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 1961#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 1962static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) 1963{ 1964 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; 1965} 1966#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 1967#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 1968static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) 1969{ 1970 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; 1971} 1972#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 1973#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 1974static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) 1975{ 1976 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; 1977} 1978 1979#define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 1980#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 1981#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 1982static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 1983{ 1984 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 1985} 1986#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 1987#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 1988static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 1989{ 1990 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 1991} 1992 1993#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 1994 1995#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 1996 1997#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 1998 1999#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 2000 2001#define REG_A3XX_SP_VS_LENGTH_REG 0x000022df 2002#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2003#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2004static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2005{ 2006 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; 2007} 2008 2009#define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 2010#define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 2011#define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 2012static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) 2013{ 2014 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; 2015} 2016#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 2017#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 2018static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) 2019{ 2020 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; 2021} 2022#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 2023#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0 2024#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4 2025static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val) 2026{ 2027 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; 2028} 2029#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00 2030#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10 2031static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val) 2032{ 2033 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; 2034} 2035#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000 2036#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18 2037static inline uint32_t A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val) 2038{ 2039 return ((val) << A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK; 2040} 2041#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 2042#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 2043static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) 2044{ 2045 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; 2046} 2047#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 2048#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 2049#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 2050#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 2051#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 2052static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 2053{ 2054 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; 2055} 2056 2057#define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 2058#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff 2059#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 2060static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) 2061{ 2062 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; 2063} 2064#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00 2065#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10 2066static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val) 2067{ 2068 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; 2069} 2070#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 2071#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 2072static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) 2073{ 2074 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; 2075} 2076#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x3f000000 2077#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 2078static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) 2079{ 2080 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; 2081} 2082 2083#define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 2084#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 2085#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 2086static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) 2087{ 2088 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; 2089} 2090#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 2091#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 2092static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) 2093{ 2094 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; 2095} 2096 2097#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 2098 2099#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 2100 2101#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 2102 2103#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 2104 2105#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 2106 2107#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 2108 2109#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 2110#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 2111#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 2112#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 2113static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) 2114{ 2115 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; 2116} 2117 2118static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2119 2120static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 2121#define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff 2122#define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 2123static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) 2124{ 2125 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; 2126} 2127#define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 2128#define A3XX_SP_FS_MRT_REG_SINT 0x00000400 2129#define A3XX_SP_FS_MRT_REG_UINT 0x00000800 2130 2131static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2132 2133static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } 2134#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f 2135#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 2136static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) 2137{ 2138 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; 2139} 2140 2141#define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff 2142#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff 2143#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 2144static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) 2145{ 2146 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; 2147} 2148 2149#define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 2150 2151#define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 2152#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2153#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2154static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2155{ 2156 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2157} 2158#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2159#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2160static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2161{ 2162 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2163} 2164#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2165#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2166static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2167{ 2168 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; 2169} 2170 2171#define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 2172 2173#define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 2174#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff 2175#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 2176static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) 2177{ 2178 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; 2179} 2180#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 2181#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 2182static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) 2183{ 2184 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; 2185} 2186#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 2187#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 2188static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) 2189{ 2190 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; 2191} 2192 2193#define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 2194 2195#define REG_A3XX_VBIF_CLKON 0x00003001 2196 2197#define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c 2198 2199#define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d 2200 2201#define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e 2202 2203#define REG_A3XX_VBIF_ABIT_SORT 0x0000301c 2204 2205#define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d 2206 2207#define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a 2208 2209#define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c 2210 2211#define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d 2212 2213#define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 2214 2215#define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 2216 2217#define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 2218 2219#define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 2220 2221#define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 2222 2223#define REG_A3XX_VBIF_ARB_CTL 0x0000303c 2224 2225#define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 2226 2227#define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 2228 2229#define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e 2230 2231#define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2232 2233#define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 2234#define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 2235#define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 2236#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 2237#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 2238#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 2239 2240#define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 2241#define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 2242#define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 2243#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 2244#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 2245#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 2246 2247#define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 2248 2249#define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 2250 2251#define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 2252 2253#define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 2254 2255#define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 2256 2257#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 2258 2259#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 2260 2261#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 2262 2263#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a 2264 2265#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b 2266 2267#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c 2268 2269#define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2270#define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2271#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2272static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) 2273{ 2274 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; 2275} 2276#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 2277#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 2278static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) 2279{ 2280 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; 2281} 2282 2283#define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 2284 2285static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2286 2287static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 2288#define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff 2289#define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 2290static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) 2291{ 2292 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; 2293} 2294#define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 2295#define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 2296static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) 2297{ 2298 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; 2299} 2300#define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 2301#define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 2302static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) 2303{ 2304 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; 2305} 2306#define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 2307#define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 2308static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) 2309{ 2310 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; 2311} 2312 2313static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 2314 2315static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 2316 2317#define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c 2318#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 2319 2320#define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 2321 2322#define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 2323 2324#define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 2325 2326#define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a 2327 2328#define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 2329 2330#define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 2331 2332#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 2333 2334#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 2335 2336#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a 2337 2338#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b 2339 2340static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2341 2342static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } 2343 2344static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } 2345 2346static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } 2347 2348static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } 2349 2350#define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 2351 2352#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 2353 2354#define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2355 2356#define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2357 2358#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 2359#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff 2360#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 2361static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) 2362{ 2363 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; 2364} 2365#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 2366#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 2367static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) 2368{ 2369 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; 2370} 2371 2372#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2373 2374#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 2375 2376#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 2377 2378#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 2379 2380#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 2381 2382#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 2383 2384#define REG_A3XX_UNKNOWN_0E43 0x00000e43 2385 2386#define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 2387 2388#define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 2389 2390#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 2391 2392#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 2393 2394#define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 2395 2396#define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 2397 2398#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 2399 2400#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 2401 2402#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 2403 2404#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 2405 2406#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 2407 2408#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 2409 2410#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 2411 2412#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 2413#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff 2414#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 2415static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) 2416{ 2417 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; 2418} 2419 2420#define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 2421#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff 2422#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 2423static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) 2424{ 2425 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; 2426} 2427#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 2428#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 2429static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) 2430{ 2431 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; 2432} 2433#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2434 2435#define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 2436 2437#define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2438 2439#define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2440 2441#define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 2442 2443#define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 2444 2445#define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 2446 2447#define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 2448 2449#define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca 2450 2451#define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb 2452 2453#define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 2454 2455#define REG_A3XX_UNKNOWN_0F03 0x00000f03 2456 2457#define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 2458 2459#define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 2460 2461#define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 2462 2463#define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 2464 2465#define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 2466 2467#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2468 2469#define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 2470 2471#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 2472 2473#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 2474#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 2475#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 2476static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 2477{ 2478 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 2479} 2480#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 2481#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 2482static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 2483{ 2484 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 2485} 2486#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 2487#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 2488static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 2489{ 2490 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 2491} 2492#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 2493#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 2494static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 2495{ 2496 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 2497} 2498#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 2499#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 2500#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2501#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 2502#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 2503static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 2504{ 2505 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 2506} 2507 2508#define REG_A3XX_VGT_IMMED_DATA 0x000021fd 2509 2510#define REG_A3XX_TEX_SAMP_0 0x00000000 2511#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2512#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2513#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 2514static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) 2515{ 2516 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; 2517} 2518#define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 2519#define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 2520static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) 2521{ 2522 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; 2523} 2524#define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 2525#define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 2526static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) 2527{ 2528 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; 2529} 2530#define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 2531#define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 2532static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) 2533{ 2534 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; 2535} 2536#define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 2537#define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 2538static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) 2539{ 2540 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2541} 2542#define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000 2543#define A3XX_TEX_SAMP_0_ANISO__SHIFT 15 2544static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) 2545{ 2546 return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; 2547} 2548#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 2549#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 2550static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) 2551{ 2552 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; 2553} 2554#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2555 2556#define REG_A3XX_TEX_SAMP_1 0x00000001 2557#define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff 2558#define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 2559static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) 2560{ 2561 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; 2562} 2563#define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 2564#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 2565static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) 2566{ 2567 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; 2568} 2569#define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 2570#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 2571static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) 2572{ 2573 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; 2574} 2575 2576#define REG_A3XX_TEX_CONST_0 0x00000000 2577#define A3XX_TEX_CONST_0_TILED 0x00000001 2578#define A3XX_TEX_CONST_0_SRGB 0x00000004 2579#define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2580#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2581static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2582{ 2583 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; 2584} 2585#define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 2586#define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 2587static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) 2588{ 2589 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; 2590} 2591#define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 2592#define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 2593static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) 2594{ 2595 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; 2596} 2597#define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 2598#define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 2599static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) 2600{ 2601 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; 2602} 2603#define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 2604#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 2605static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) 2606{ 2607 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; 2608} 2609#define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 2610#define A3XX_TEX_CONST_0_FMT__SHIFT 22 2611static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) 2612{ 2613 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2614} 2615#define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 2616#define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2617#define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2618static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2619{ 2620 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; 2621} 2622 2623#define REG_A3XX_TEX_CONST_1 0x00000001 2624#define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff 2625#define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 2626static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) 2627{ 2628 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; 2629} 2630#define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 2631#define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 2632static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) 2633{ 2634 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; 2635} 2636#define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000 2637#define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28 2638static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val) 2639{ 2640 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK; 2641} 2642 2643#define REG_A3XX_TEX_CONST_2 0x00000002 2644#define A3XX_TEX_CONST_2_INDX__MASK 0x000000ff 2645#define A3XX_TEX_CONST_2_INDX__SHIFT 0 2646static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) 2647{ 2648 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; 2649} 2650#define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 2651#define A3XX_TEX_CONST_2_PITCH__SHIFT 12 2652static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) 2653{ 2654 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; 2655} 2656#define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 2657#define A3XX_TEX_CONST_2_SWAP__SHIFT 30 2658static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) 2659{ 2660 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; 2661} 2662 2663#define REG_A3XX_TEX_CONST_3 0x00000003 2664#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0000000f 2665#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 2666static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) 2667{ 2668 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; 2669} 2670#define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 2671#define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 2672static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) 2673{ 2674 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; 2675} 2676#define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 2677#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 2678static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) 2679{ 2680 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; 2681} 2682 2683 2684#endif /* A3XX_XML */ 2685