1/* 2 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 20#include "msm_drv.h" 21#include "msm_mmu.h" 22#include "mdp5_kms.h" 23 24static const char *iommu_ports[] = { 25 "mdp_0", 26}; 27 28static int mdp5_hw_init(struct msm_kms *kms) 29{ 30 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 31 struct drm_device *dev = mdp5_kms->dev; 32 unsigned long flags; 33 34 pm_runtime_get_sync(dev->dev); 35 36 /* Magic unknown register writes: 37 * 38 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 39 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 40 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 41 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 42 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 43 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 44 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 45 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 46 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 47 * 48 * Downstream fbdev driver gets these register offsets/values 49 * from DT.. not really sure what these registers are or if 50 * different values for different boards/SoC's, etc. I guess 51 * they are the golden registers. 52 * 53 * Not setting these does not seem to cause any problem. But 54 * we may be getting lucky with the bootloader initializing 55 * them for us. OTOH, if we can always count on the bootloader 56 * setting the golden registers, then perhaps we don't need to 57 * care. 58 */ 59 60 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 61 mdp5_write(mdp5_kms, REG_MDP5_MDP_DISP_INTF_SEL(0), 0); 62 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 63 64 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 65 66 pm_runtime_put_sync(dev->dev); 67 68 return 0; 69} 70 71static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 72{ 73 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 74 mdp5_enable(mdp5_kms); 75} 76 77static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state) 78{ 79 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 80 mdp5_disable(mdp5_kms); 81} 82 83static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, 84 struct drm_encoder *encoder) 85{ 86 return rate; 87} 88 89static int mdp5_set_split_display(struct msm_kms *kms, 90 struct drm_encoder *encoder, 91 struct drm_encoder *slave_encoder, 92 bool is_cmd_mode) 93{ 94 if (is_cmd_mode) 95 return mdp5_cmd_encoder_set_split_display(encoder, 96 slave_encoder); 97 else 98 return mdp5_encoder_set_split_display(encoder, slave_encoder); 99} 100 101static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file) 102{ 103 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 104 struct msm_drm_private *priv = mdp5_kms->dev->dev_private; 105 unsigned i; 106 107 for (i = 0; i < priv->num_crtcs; i++) 108 mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file); 109} 110 111static void mdp5_destroy(struct msm_kms *kms) 112{ 113 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 114 struct msm_mmu *mmu = mdp5_kms->mmu; 115 116 mdp5_irq_domain_fini(mdp5_kms); 117 118 if (mmu) { 119 mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports)); 120 mmu->funcs->destroy(mmu); 121 } 122 123 if (mdp5_kms->ctlm) 124 mdp5_ctlm_destroy(mdp5_kms->ctlm); 125 if (mdp5_kms->smp) 126 mdp5_smp_destroy(mdp5_kms->smp); 127 if (mdp5_kms->cfg) 128 mdp5_cfg_destroy(mdp5_kms->cfg); 129 130 kfree(mdp5_kms); 131} 132 133static const struct mdp_kms_funcs kms_funcs = { 134 .base = { 135 .hw_init = mdp5_hw_init, 136 .irq_preinstall = mdp5_irq_preinstall, 137 .irq_postinstall = mdp5_irq_postinstall, 138 .irq_uninstall = mdp5_irq_uninstall, 139 .irq = mdp5_irq, 140 .enable_vblank = mdp5_enable_vblank, 141 .disable_vblank = mdp5_disable_vblank, 142 .prepare_commit = mdp5_prepare_commit, 143 .complete_commit = mdp5_complete_commit, 144 .get_format = mdp_get_format, 145 .round_pixclk = mdp5_round_pixclk, 146 .set_split_display = mdp5_set_split_display, 147 .preclose = mdp5_preclose, 148 .destroy = mdp5_destroy, 149 }, 150 .set_irqmask = mdp5_set_irqmask, 151}; 152 153int mdp5_disable(struct mdp5_kms *mdp5_kms) 154{ 155 DBG(""); 156 157 clk_disable_unprepare(mdp5_kms->ahb_clk); 158 clk_disable_unprepare(mdp5_kms->axi_clk); 159 clk_disable_unprepare(mdp5_kms->core_clk); 160 clk_disable_unprepare(mdp5_kms->lut_clk); 161 162 return 0; 163} 164 165int mdp5_enable(struct mdp5_kms *mdp5_kms) 166{ 167 DBG(""); 168 169 clk_prepare_enable(mdp5_kms->ahb_clk); 170 clk_prepare_enable(mdp5_kms->axi_clk); 171 clk_prepare_enable(mdp5_kms->core_clk); 172 clk_prepare_enable(mdp5_kms->lut_clk); 173 174 return 0; 175} 176 177static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 178 enum mdp5_intf_type intf_type, int intf_num, 179 enum mdp5_intf_mode intf_mode) 180{ 181 struct drm_device *dev = mdp5_kms->dev; 182 struct msm_drm_private *priv = dev->dev_private; 183 struct drm_encoder *encoder; 184 struct mdp5_interface intf = { 185 .num = intf_num, 186 .type = intf_type, 187 .mode = intf_mode, 188 }; 189 190 if ((intf_type == INTF_DSI) && 191 (intf_mode == MDP5_INTF_DSI_MODE_COMMAND)) 192 encoder = mdp5_cmd_encoder_init(dev, &intf); 193 else 194 encoder = mdp5_encoder_init(dev, &intf); 195 196 if (IS_ERR(encoder)) { 197 dev_err(dev->dev, "failed to construct encoder\n"); 198 return encoder; 199 } 200 201 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 202 priv->encoders[priv->num_encoders++] = encoder; 203 204 return encoder; 205} 206 207static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 208{ 209 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 210 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 211 int id = 0, i; 212 213 for (i = 0; i < intf_cnt; i++) { 214 if (intfs[i] == INTF_DSI) { 215 if (intf_num == i) 216 return id; 217 218 id++; 219 } 220 } 221 222 return -EINVAL; 223} 224 225static int modeset_init_intf(struct mdp5_kms *mdp5_kms, int intf_num) 226{ 227 struct drm_device *dev = mdp5_kms->dev; 228 struct msm_drm_private *priv = dev->dev_private; 229 const struct mdp5_cfg_hw *hw_cfg = 230 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 231 enum mdp5_intf_type intf_type = hw_cfg->intf.connect[intf_num]; 232 struct drm_encoder *encoder; 233 int ret = 0; 234 235 switch (intf_type) { 236 case INTF_DISABLED: 237 break; 238 case INTF_eDP: 239 if (!priv->edp) 240 break; 241 242 encoder = construct_encoder(mdp5_kms, INTF_eDP, intf_num, 243 MDP5_INTF_MODE_NONE); 244 if (IS_ERR(encoder)) { 245 ret = PTR_ERR(encoder); 246 break; 247 } 248 249 ret = msm_edp_modeset_init(priv->edp, dev, encoder); 250 break; 251 case INTF_HDMI: 252 if (!priv->hdmi) 253 break; 254 255 encoder = construct_encoder(mdp5_kms, INTF_HDMI, intf_num, 256 MDP5_INTF_MODE_NONE); 257 if (IS_ERR(encoder)) { 258 ret = PTR_ERR(encoder); 259 break; 260 } 261 262 ret = hdmi_modeset_init(priv->hdmi, dev, encoder); 263 break; 264 case INTF_DSI: 265 { 266 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf_num); 267 struct drm_encoder *dsi_encs[MSM_DSI_ENCODER_NUM]; 268 enum mdp5_intf_mode mode; 269 int i; 270 271 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { 272 dev_err(dev->dev, "failed to find dsi from intf %d\n", 273 intf_num); 274 ret = -EINVAL; 275 break; 276 } 277 278 if (!priv->dsi[dsi_id]) 279 break; 280 281 for (i = 0; i < MSM_DSI_ENCODER_NUM; i++) { 282 mode = (i == MSM_DSI_CMD_ENCODER_ID) ? 283 MDP5_INTF_DSI_MODE_COMMAND : 284 MDP5_INTF_DSI_MODE_VIDEO; 285 dsi_encs[i] = construct_encoder(mdp5_kms, INTF_DSI, 286 intf_num, mode); 287 if (IS_ERR(dsi_encs)) { 288 ret = PTR_ERR(dsi_encs); 289 break; 290 } 291 } 292 293 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, dsi_encs); 294 break; 295 } 296 default: 297 dev_err(dev->dev, "unknown intf: %d\n", intf_type); 298 ret = -EINVAL; 299 break; 300 } 301 302 return ret; 303} 304 305static int modeset_init(struct mdp5_kms *mdp5_kms) 306{ 307 static const enum mdp5_pipe crtcs[] = { 308 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 309 }; 310 static const enum mdp5_pipe pub_planes[] = { 311 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 312 }; 313 struct drm_device *dev = mdp5_kms->dev; 314 struct msm_drm_private *priv = dev->dev_private; 315 const struct mdp5_cfg_hw *hw_cfg; 316 int i, ret; 317 318 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 319 320 /* register our interrupt-controller for hdmi/eDP/dsi/etc 321 * to use for irqs routed through mdp: 322 */ 323 ret = mdp5_irq_domain_init(mdp5_kms); 324 if (ret) 325 goto fail; 326 327 /* construct CRTCs and their private planes: */ 328 for (i = 0; i < hw_cfg->pipe_rgb.count; i++) { 329 struct drm_plane *plane; 330 struct drm_crtc *crtc; 331 332 plane = mdp5_plane_init(dev, crtcs[i], true, 333 hw_cfg->pipe_rgb.base[i]); 334 if (IS_ERR(plane)) { 335 ret = PTR_ERR(plane); 336 dev_err(dev->dev, "failed to construct plane for %s (%d)\n", 337 pipe2name(crtcs[i]), ret); 338 goto fail; 339 } 340 341 crtc = mdp5_crtc_init(dev, plane, i); 342 if (IS_ERR(crtc)) { 343 ret = PTR_ERR(crtc); 344 dev_err(dev->dev, "failed to construct crtc for %s (%d)\n", 345 pipe2name(crtcs[i]), ret); 346 goto fail; 347 } 348 priv->crtcs[priv->num_crtcs++] = crtc; 349 } 350 351 /* Construct public planes: */ 352 for (i = 0; i < hw_cfg->pipe_vig.count; i++) { 353 struct drm_plane *plane; 354 355 plane = mdp5_plane_init(dev, pub_planes[i], false, 356 hw_cfg->pipe_vig.base[i]); 357 if (IS_ERR(plane)) { 358 ret = PTR_ERR(plane); 359 dev_err(dev->dev, "failed to construct %s plane: %d\n", 360 pipe2name(pub_planes[i]), ret); 361 goto fail; 362 } 363 } 364 365 /* Construct encoders and modeset initialize connector devices 366 * for each external display interface. 367 */ 368 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 369 ret = modeset_init_intf(mdp5_kms, i); 370 if (ret) 371 goto fail; 372 } 373 374 return 0; 375 376fail: 377 return ret; 378} 379 380static void read_hw_revision(struct mdp5_kms *mdp5_kms, 381 uint32_t *major, uint32_t *minor) 382{ 383 uint32_t version; 384 385 mdp5_enable(mdp5_kms); 386 version = mdp5_read(mdp5_kms, REG_MDSS_HW_VERSION); 387 mdp5_disable(mdp5_kms); 388 389 *major = FIELD(version, MDSS_HW_VERSION_MAJOR); 390 *minor = FIELD(version, MDSS_HW_VERSION_MINOR); 391 392 DBG("MDP5 version v%d.%d", *major, *minor); 393} 394 395static int get_clk(struct platform_device *pdev, struct clk **clkp, 396 const char *name) 397{ 398 struct device *dev = &pdev->dev; 399 struct clk *clk = devm_clk_get(dev, name); 400 if (IS_ERR(clk)) { 401 dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 402 return PTR_ERR(clk); 403 } 404 *clkp = clk; 405 return 0; 406} 407 408struct msm_kms *mdp5_kms_init(struct drm_device *dev) 409{ 410 struct platform_device *pdev = dev->platformdev; 411 struct mdp5_cfg *config; 412 struct mdp5_kms *mdp5_kms; 413 struct msm_kms *kms = NULL; 414 struct msm_mmu *mmu; 415 uint32_t major, minor; 416 int i, ret; 417 418 mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL); 419 if (!mdp5_kms) { 420 dev_err(dev->dev, "failed to allocate kms\n"); 421 ret = -ENOMEM; 422 goto fail; 423 } 424 425 spin_lock_init(&mdp5_kms->resource_lock); 426 427 mdp_kms_init(&mdp5_kms->base, &kms_funcs); 428 429 kms = &mdp5_kms->base.base; 430 431 mdp5_kms->dev = dev; 432 433 /* mdp5_kms->mmio actually represents the MDSS base address */ 434 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); 435 if (IS_ERR(mdp5_kms->mmio)) { 436 ret = PTR_ERR(mdp5_kms->mmio); 437 goto fail; 438 } 439 440 mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF"); 441 if (IS_ERR(mdp5_kms->vbif)) { 442 ret = PTR_ERR(mdp5_kms->vbif); 443 goto fail; 444 } 445 446 mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd"); 447 if (IS_ERR(mdp5_kms->vdd)) { 448 ret = PTR_ERR(mdp5_kms->vdd); 449 goto fail; 450 } 451 452 ret = regulator_enable(mdp5_kms->vdd); 453 if (ret) { 454 dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); 455 goto fail; 456 } 457 458 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk"); 459 if (ret) 460 goto fail; 461 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk"); 462 if (ret) 463 goto fail; 464 ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src"); 465 if (ret) 466 goto fail; 467 ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk"); 468 if (ret) 469 goto fail; 470 ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk"); 471 if (ret) 472 goto fail; 473 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk"); 474 if (ret) 475 goto fail; 476 477 /* we need to set a default rate before enabling. Set a safe 478 * rate first, then figure out hw revision, and then set a 479 * more optimal rate: 480 */ 481 clk_set_rate(mdp5_kms->src_clk, 200000000); 482 483 read_hw_revision(mdp5_kms, &major, &minor); 484 485 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 486 if (IS_ERR(mdp5_kms->cfg)) { 487 ret = PTR_ERR(mdp5_kms->cfg); 488 mdp5_kms->cfg = NULL; 489 goto fail; 490 } 491 492 config = mdp5_cfg_get_config(mdp5_kms->cfg); 493 494 /* TODO: compute core clock rate at runtime */ 495 clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk); 496 497 mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); 498 if (IS_ERR(mdp5_kms->smp)) { 499 ret = PTR_ERR(mdp5_kms->smp); 500 mdp5_kms->smp = NULL; 501 goto fail; 502 } 503 504 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw); 505 if (IS_ERR(mdp5_kms->ctlm)) { 506 ret = PTR_ERR(mdp5_kms->ctlm); 507 mdp5_kms->ctlm = NULL; 508 goto fail; 509 } 510 511 /* make sure things are off before attaching iommu (bootloader could 512 * have left things on, in which case we'll start getting faults if 513 * we don't disable): 514 */ 515 mdp5_enable(mdp5_kms); 516 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 517 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 518 !config->hw->intf.base[i]) 519 continue; 520 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 521 } 522 mdp5_disable(mdp5_kms); 523 mdelay(16); 524 525 if (config->platform.iommu) { 526 mmu = msm_iommu_new(&pdev->dev, config->platform.iommu); 527 if (IS_ERR(mmu)) { 528 ret = PTR_ERR(mmu); 529 dev_err(dev->dev, "failed to init iommu: %d\n", ret); 530 goto fail; 531 } 532 533 ret = mmu->funcs->attach(mmu, iommu_ports, 534 ARRAY_SIZE(iommu_ports)); 535 if (ret) { 536 dev_err(dev->dev, "failed to attach iommu: %d\n", ret); 537 mmu->funcs->destroy(mmu); 538 goto fail; 539 } 540 } else { 541 dev_info(dev->dev, "no iommu, fallback to phys " 542 "contig buffers for scanout\n"); 543 mmu = NULL; 544 } 545 mdp5_kms->mmu = mmu; 546 547 mdp5_kms->id = msm_register_mmu(dev, mmu); 548 if (mdp5_kms->id < 0) { 549 ret = mdp5_kms->id; 550 dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret); 551 goto fail; 552 } 553 554 ret = modeset_init(mdp5_kms); 555 if (ret) { 556 dev_err(dev->dev, "modeset_init failed: %d\n", ret); 557 goto fail; 558 } 559 560 return kms; 561 562fail: 563 if (kms) 564 mdp5_destroy(kms); 565 return ERR_PTR(ret); 566} 567