1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv50.h"
25
26#include <nvif/class.h>
27
28/*******************************************************************************
29 * Base display object
30 ******************************************************************************/
31
32static struct nvkm_oclass
33gt215_disp_sclass[] = {
34	{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
35	{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
36	{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
37	{ GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
38	{ GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
39	{}
40};
41
42static struct nvkm_oclass
43gt215_disp_main_oclass[] = {
44	{ GT214_DISP, &nv50_disp_main_ofuncs },
45	{}
46};
47
48/*******************************************************************************
49 * Display engine implementation
50 ******************************************************************************/
51
52static int
53gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
54		struct nvkm_oclass *oclass, void *data, u32 size,
55		struct nvkm_object **pobject)
56{
57	struct nv50_disp_priv *priv;
58	int ret;
59
60	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
61			       "display", &priv);
62	*pobject = nv_object(priv);
63	if (ret)
64		return ret;
65
66	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
67	if (ret)
68		return ret;
69
70	nv_engine(priv)->sclass = gt215_disp_main_oclass;
71	nv_engine(priv)->cclass = &nv50_disp_cclass;
72	nv_subdev(priv)->intr = nv50_disp_intr;
73	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
74	priv->sclass = gt215_disp_sclass;
75	priv->head.nr = 2;
76	priv->dac.nr = 3;
77	priv->sor.nr = 4;
78	priv->pior.nr = 3;
79	priv->dac.power = nv50_dac_power;
80	priv->dac.sense = nv50_dac_sense;
81	priv->sor.power = nv50_sor_power;
82	priv->sor.hda_eld = gt215_hda_eld;
83	priv->sor.hdmi = gt215_hdmi_ctrl;
84	priv->pior.power = nv50_pior_power;
85	return 0;
86}
87
88struct nvkm_oclass *
89gt215_disp_oclass = &(struct nv50_disp_impl) {
90	.base.base.handle = NV_ENGINE(DISP, 0x85),
91	.base.base.ofuncs = &(struct nvkm_ofuncs) {
92		.ctor = gt215_disp_ctor,
93		.dtor = _nvkm_disp_dtor,
94		.init = _nvkm_disp_init,
95		.fini = _nvkm_disp_fini,
96	},
97	.base.vblank = &nv50_disp_vblank_func,
98	.base.outp =  g94_disp_outp_sclass,
99	.mthd.core = &g94_disp_core_mthd_chan,
100	.mthd.base = &g84_disp_base_mthd_chan,
101	.mthd.ovly = &g84_disp_ovly_mthd_chan,
102	.mthd.prev = 0x000004,
103	.head.scanoutpos = nv50_disp_main_scanoutpos,
104}.base.base;
105