1/* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include <subdev/bios.h> 25#include <subdev/bios/bit.h> 26#include <subdev/bios/rammap.h> 27 28u32 29nvbios_rammapTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, 30 u8 *cnt, u8 *len, u8 *snr, u8 *ssz) 31{ 32 struct bit_entry bit_P; 33 u16 rammap = 0x0000; 34 35 if (!bit_entry(bios, 'P', &bit_P)) { 36 if (bit_P.version == 2) 37 rammap = nv_ro16(bios, bit_P.offset + 4); 38 39 if (rammap) { 40 *ver = nv_ro08(bios, rammap + 0); 41 switch (*ver) { 42 case 0x10: 43 case 0x11: 44 *hdr = nv_ro08(bios, rammap + 1); 45 *cnt = nv_ro08(bios, rammap + 5); 46 *len = nv_ro08(bios, rammap + 2); 47 *snr = nv_ro08(bios, rammap + 4); 48 *ssz = nv_ro08(bios, rammap + 3); 49 return rammap; 50 default: 51 break; 52 } 53 } 54 } 55 56 return 0x0000; 57} 58 59u32 60nvbios_rammapEe(struct nvkm_bios *bios, int idx, 61 u8 *ver, u8 *hdr, u8 *cnt, u8 *len) 62{ 63 u8 snr, ssz; 64 u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz); 65 if (rammap && idx < *cnt) { 66 rammap = rammap + *hdr + (idx * (*len + (snr * ssz))); 67 *hdr = *len; 68 *cnt = snr; 69 *len = ssz; 70 return rammap; 71 } 72 return 0x0000; 73} 74 75u32 76nvbios_rammapEp(struct nvkm_bios *bios, int idx, 77 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p) 78{ 79 u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp; 80 memset(p, 0x00, sizeof(*p)); 81 p->rammap_ver = *ver; 82 p->rammap_hdr = *hdr; 83 switch (!!data * *ver) { 84 case 0x10: 85 p->rammap_min = nv_ro16(bios, data + 0x00); 86 p->rammap_max = nv_ro16(bios, data + 0x02); 87 p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1; 88 p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3; 89 break; 90 case 0x11: 91 p->rammap_min = nv_ro16(bios, data + 0x00); 92 p->rammap_max = nv_ro16(bios, data + 0x02); 93 p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; 94 p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; 95 p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; 96 temp = nv_ro32(bios, data + 0x09); 97 p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0; 98 p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9; 99 p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18; 100 p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19; 101 p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20; 102 p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25; 103 p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26; 104 p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27; 105 p->rammap_11_0d = nv_ro08(bios, data + 0x0d); 106 p->rammap_11_0e = nv_ro08(bios, data + 0x0e); 107 p->rammap_11_0f = nv_ro08(bios, data + 0x0f); 108 p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2; 109 break; 110 default: 111 data = 0; 112 break; 113 } 114 return data; 115} 116 117u32 118nvbios_rammapEm(struct nvkm_bios *bios, u16 mhz, 119 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *info) 120{ 121 int idx = 0; 122 u32 data; 123 while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) { 124 if (mhz >= info->rammap_min && mhz <= info->rammap_max) 125 break; 126 } 127 return data; 128} 129 130u32 131nvbios_rammapSe(struct nvkm_bios *bios, u32 data, 132 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, u8 *ver, u8 *hdr) 133{ 134 if (idx < ecnt) { 135 data = data + ehdr + (idx * elen); 136 *ver = ever; 137 *hdr = elen; 138 return data; 139 } 140 return 0; 141} 142 143u32 144nvbios_rammapSp(struct nvkm_bios *bios, u32 data, 145 u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, 146 u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) 147{ 148 data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); 149 p->ramcfg_ver = *ver; 150 p->ramcfg_hdr = *hdr; 151 switch (!!data * *ver) { 152 case 0x10: 153 p->ramcfg_timing = nv_ro08(bios, data + 0x01); 154 p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0; 155 p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1; 156 p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; 157 p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; 158 p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; 159 p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5; 160 p->ramcfg_10_DLLoff = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; 161 p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; 162 p->ramcfg_10_04_01 = (nv_ro08(bios, data + 0x04) & 0x01) >> 0; 163 p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0; 164 p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; 165 p->ramcfg_10_07 = (nv_ro08(bios, data + 0x07) & 0xff) >> 0; 166 p->ramcfg_10_08 = (nv_ro08(bios, data + 0x08) & 0xff) >> 0; 167 p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0; 168 p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4; 169 break; 170 case 0x11: 171 p->ramcfg_timing = nv_ro08(bios, data + 0x00); 172 p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; 173 p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; 174 p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; 175 p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3; 176 p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4; 177 p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5; 178 p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6; 179 p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7; 180 p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0; 181 p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; 182 p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; 183 p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; 184 p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; 185 p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7; 186 p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; 187 p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4; 188 p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6; 189 p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4; 190 p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0; 191 p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; 192 p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1; 193 p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2; 194 p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3; 195 p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4; 196 p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6; 197 p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7; 198 p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; 199 p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1; 200 p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2; 201 p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3; 202 p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; 203 p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5; 204 p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0; 205 break; 206 default: 207 data = 0; 208 break; 209 } 210 return data; 211} 212