1/* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "nv50.h" 25#include "pll.h" 26#include "seq.h" 27 28#include <core/device.h> 29#include <subdev/bios.h> 30#include <subdev/bios/pll.h> 31 32static u32 33read_div(struct nv50_clk_priv *priv) 34{ 35 switch (nv_device(priv)->chipset) { 36 case 0x50: /* it exists, but only has bit 31, not the dividers.. */ 37 case 0x84: 38 case 0x86: 39 case 0x98: 40 case 0xa0: 41 return nv_rd32(priv, 0x004700); 42 case 0x92: 43 case 0x94: 44 case 0x96: 45 return nv_rd32(priv, 0x004800); 46 default: 47 return 0x00000000; 48 } 49} 50 51static u32 52read_pll_src(struct nv50_clk_priv *priv, u32 base) 53{ 54 struct nvkm_clk *clk = &priv->base; 55 u32 coef, ref = clk->read(clk, nv_clk_src_crystal); 56 u32 rsel = nv_rd32(priv, 0x00e18c); 57 int P, N, M, id; 58 59 switch (nv_device(priv)->chipset) { 60 case 0x50: 61 case 0xa0: 62 switch (base) { 63 case 0x4020: 64 case 0x4028: id = !!(rsel & 0x00000004); break; 65 case 0x4008: id = !!(rsel & 0x00000008); break; 66 case 0x4030: id = 0; break; 67 default: 68 nv_error(priv, "ref: bad pll 0x%06x\n", base); 69 return 0; 70 } 71 72 coef = nv_rd32(priv, 0x00e81c + (id * 0x0c)); 73 ref *= (coef & 0x01000000) ? 2 : 4; 74 P = (coef & 0x00070000) >> 16; 75 N = ((coef & 0x0000ff00) >> 8) + 1; 76 M = ((coef & 0x000000ff) >> 0) + 1; 77 break; 78 case 0x84: 79 case 0x86: 80 case 0x92: 81 coef = nv_rd32(priv, 0x00e81c); 82 P = (coef & 0x00070000) >> 16; 83 N = (coef & 0x0000ff00) >> 8; 84 M = (coef & 0x000000ff) >> 0; 85 break; 86 case 0x94: 87 case 0x96: 88 case 0x98: 89 rsel = nv_rd32(priv, 0x00c050); 90 switch (base) { 91 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; 92 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; 93 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; 94 case 0x4030: rsel = 3; break; 95 default: 96 nv_error(priv, "ref: bad pll 0x%06x\n", base); 97 return 0; 98 } 99 100 switch (rsel) { 101 case 0: id = 1; break; 102 case 1: return clk->read(clk, nv_clk_src_crystal); 103 case 2: return clk->read(clk, nv_clk_src_href); 104 case 3: id = 0; break; 105 } 106 107 coef = nv_rd32(priv, 0x00e81c + (id * 0x28)); 108 P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7; 109 P += (coef & 0x00070000) >> 16; 110 N = (coef & 0x0000ff00) >> 8; 111 M = (coef & 0x000000ff) >> 0; 112 break; 113 default: 114 BUG_ON(1); 115 } 116 117 if (M) 118 return (ref * N / M) >> P; 119 120 return 0; 121} 122 123static u32 124read_pll_ref(struct nv50_clk_priv *priv, u32 base) 125{ 126 struct nvkm_clk *clk = &priv->base; 127 u32 src, mast = nv_rd32(priv, 0x00c040); 128 129 switch (base) { 130 case 0x004028: 131 src = !!(mast & 0x00200000); 132 break; 133 case 0x004020: 134 src = !!(mast & 0x00400000); 135 break; 136 case 0x004008: 137 src = !!(mast & 0x00010000); 138 break; 139 case 0x004030: 140 src = !!(mast & 0x02000000); 141 break; 142 case 0x00e810: 143 return clk->read(clk, nv_clk_src_crystal); 144 default: 145 nv_error(priv, "bad pll 0x%06x\n", base); 146 return 0; 147 } 148 149 if (src) 150 return clk->read(clk, nv_clk_src_href); 151 152 return read_pll_src(priv, base); 153} 154 155static u32 156read_pll(struct nv50_clk_priv *priv, u32 base) 157{ 158 struct nvkm_clk *clk = &priv->base; 159 u32 mast = nv_rd32(priv, 0x00c040); 160 u32 ctrl = nv_rd32(priv, base + 0); 161 u32 coef = nv_rd32(priv, base + 4); 162 u32 ref = read_pll_ref(priv, base); 163 u32 freq = 0; 164 int N1, N2, M1, M2; 165 166 if (base == 0x004028 && (mast & 0x00100000)) { 167 /* wtf, appears to only disable post-divider on gt200 */ 168 if (nv_device(priv)->chipset != 0xa0) 169 return clk->read(clk, nv_clk_src_dom6); 170 } 171 172 N2 = (coef & 0xff000000) >> 24; 173 M2 = (coef & 0x00ff0000) >> 16; 174 N1 = (coef & 0x0000ff00) >> 8; 175 M1 = (coef & 0x000000ff); 176 if ((ctrl & 0x80000000) && M1) { 177 freq = ref * N1 / M1; 178 if ((ctrl & 0x40000100) == 0x40000000) { 179 if (M2) 180 freq = freq * N2 / M2; 181 else 182 freq = 0; 183 } 184 } 185 186 return freq; 187} 188 189static int 190nv50_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) 191{ 192 struct nv50_clk_priv *priv = (void *)clk; 193 u32 mast = nv_rd32(priv, 0x00c040); 194 u32 P = 0; 195 196 switch (src) { 197 case nv_clk_src_crystal: 198 return nv_device(priv)->crystal; 199 case nv_clk_src_href: 200 return 100000; /* PCIE reference clock */ 201 case nv_clk_src_hclk: 202 return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000); 203 case nv_clk_src_hclkm3: 204 return clk->read(clk, nv_clk_src_hclk) * 3; 205 case nv_clk_src_hclkm3d2: 206 return clk->read(clk, nv_clk_src_hclk) * 3 / 2; 207 case nv_clk_src_host: 208 switch (mast & 0x30000000) { 209 case 0x00000000: return clk->read(clk, nv_clk_src_href); 210 case 0x10000000: break; 211 case 0x20000000: /* !0x50 */ 212 case 0x30000000: return clk->read(clk, nv_clk_src_hclk); 213 } 214 break; 215 case nv_clk_src_core: 216 if (!(mast & 0x00100000)) 217 P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16; 218 switch (mast & 0x00000003) { 219 case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; 220 case 0x00000001: return clk->read(clk, nv_clk_src_dom6); 221 case 0x00000002: return read_pll(priv, 0x004020) >> P; 222 case 0x00000003: return read_pll(priv, 0x004028) >> P; 223 } 224 break; 225 case nv_clk_src_shader: 226 P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16; 227 switch (mast & 0x00000030) { 228 case 0x00000000: 229 if (mast & 0x00000080) 230 return clk->read(clk, nv_clk_src_host) >> P; 231 return clk->read(clk, nv_clk_src_crystal) >> P; 232 case 0x00000010: break; 233 case 0x00000020: return read_pll(priv, 0x004028) >> P; 234 case 0x00000030: return read_pll(priv, 0x004020) >> P; 235 } 236 break; 237 case nv_clk_src_mem: 238 P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16; 239 if (nv_rd32(priv, 0x004008) & 0x00000200) { 240 switch (mast & 0x0000c000) { 241 case 0x00000000: 242 return clk->read(clk, nv_clk_src_crystal) >> P; 243 case 0x00008000: 244 case 0x0000c000: 245 return clk->read(clk, nv_clk_src_href) >> P; 246 } 247 } else { 248 return read_pll(priv, 0x004008) >> P; 249 } 250 break; 251 case nv_clk_src_vdec: 252 P = (read_div(priv) & 0x00000700) >> 8; 253 switch (nv_device(priv)->chipset) { 254 case 0x84: 255 case 0x86: 256 case 0x92: 257 case 0x94: 258 case 0x96: 259 case 0xa0: 260 switch (mast & 0x00000c00) { 261 case 0x00000000: 262 if (nv_device(priv)->chipset == 0xa0) /* wtf?? */ 263 return clk->read(clk, nv_clk_src_core) >> P; 264 return clk->read(clk, nv_clk_src_crystal) >> P; 265 case 0x00000400: 266 return 0; 267 case 0x00000800: 268 if (mast & 0x01000000) 269 return read_pll(priv, 0x004028) >> P; 270 return read_pll(priv, 0x004030) >> P; 271 case 0x00000c00: 272 return clk->read(clk, nv_clk_src_core) >> P; 273 } 274 break; 275 case 0x98: 276 switch (mast & 0x00000c00) { 277 case 0x00000000: 278 return clk->read(clk, nv_clk_src_core) >> P; 279 case 0x00000400: 280 return 0; 281 case 0x00000800: 282 return clk->read(clk, nv_clk_src_hclkm3d2) >> P; 283 case 0x00000c00: 284 return clk->read(clk, nv_clk_src_mem) >> P; 285 } 286 break; 287 } 288 break; 289 case nv_clk_src_dom6: 290 switch (nv_device(priv)->chipset) { 291 case 0x50: 292 case 0xa0: 293 return read_pll(priv, 0x00e810) >> 2; 294 case 0x84: 295 case 0x86: 296 case 0x92: 297 case 0x94: 298 case 0x96: 299 case 0x98: 300 P = (read_div(priv) & 0x00000007) >> 0; 301 switch (mast & 0x0c000000) { 302 case 0x00000000: return clk->read(clk, nv_clk_src_href); 303 case 0x04000000: break; 304 case 0x08000000: return clk->read(clk, nv_clk_src_hclk); 305 case 0x0c000000: 306 return clk->read(clk, nv_clk_src_hclkm3) >> P; 307 } 308 break; 309 default: 310 break; 311 } 312 default: 313 break; 314 } 315 316 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); 317 return -EINVAL; 318} 319 320static u32 321calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) 322{ 323 struct nvkm_bios *bios = nvkm_bios(priv); 324 struct nvbios_pll pll; 325 int ret; 326 327 ret = nvbios_pll_parse(bios, reg, &pll); 328 if (ret) 329 return 0; 330 331 pll.vco2.max_freq = 0; 332 pll.refclk = read_pll_ref(priv, reg); 333 if (!pll.refclk) 334 return 0; 335 336 return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); 337} 338 339static inline u32 340calc_div(u32 src, u32 target, int *div) 341{ 342 u32 clk0 = src, clk1 = src; 343 for (*div = 0; *div <= 7; (*div)++) { 344 if (clk0 <= target) { 345 clk1 = clk0 << (*div ? 1 : 0); 346 break; 347 } 348 clk0 >>= 1; 349 } 350 351 if (target - clk0 <= clk1 - target) 352 return clk0; 353 (*div)--; 354 return clk1; 355} 356 357static inline u32 358clk_same(u32 a, u32 b) 359{ 360 return ((a / 1000) == (b / 1000)); 361} 362 363static int 364nv50_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate) 365{ 366 struct nv50_clk_priv *priv = (void *)clk; 367 struct nv50_clk_hwsq *hwsq = &priv->hwsq; 368 const int shader = cstate->domain[nv_clk_src_shader]; 369 const int core = cstate->domain[nv_clk_src_core]; 370 const int vdec = cstate->domain[nv_clk_src_vdec]; 371 const int dom6 = cstate->domain[nv_clk_src_dom6]; 372 u32 mastm = 0, mastv = 0; 373 u32 divsm = 0, divsv = 0; 374 int N, M, P1, P2; 375 int freq, out; 376 377 /* prepare a hwsq script from which we'll perform the reclock */ 378 out = clk_init(hwsq, nv_subdev(clk)); 379 if (out) 380 return out; 381 382 clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ 383 clk_nsec(hwsq, 8000); 384 clk_setf(hwsq, 0x10, 0x00); /* disable fb */ 385 clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ 386 387 /* vdec: avoid modifying xpll until we know exactly how the other 388 * clock domains work, i suspect at least some of them can also be 389 * tied to xpll... 390 */ 391 if (vdec) { 392 /* see how close we can get using nvclk as a source */ 393 freq = calc_div(core, vdec, &P1); 394 395 /* see how close we can get using xpll/hclk as a source */ 396 if (nv_device(priv)->chipset != 0x98) 397 out = read_pll(priv, 0x004030); 398 else 399 out = clk->read(clk, nv_clk_src_hclkm3d2); 400 out = calc_div(out, vdec, &P2); 401 402 /* select whichever gets us closest */ 403 if (abs(vdec - freq) <= abs(vdec - out)) { 404 if (nv_device(priv)->chipset != 0x98) 405 mastv |= 0x00000c00; 406 divsv |= P1 << 8; 407 } else { 408 mastv |= 0x00000800; 409 divsv |= P2 << 8; 410 } 411 412 mastm |= 0x00000c00; 413 divsm |= 0x00000700; 414 } 415 416 /* dom6: nfi what this is, but we're limited to various combinations 417 * of the host clock frequency 418 */ 419 if (dom6) { 420 if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) { 421 mastv |= 0x00000000; 422 } else 423 if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) { 424 mastv |= 0x08000000; 425 } else { 426 freq = clk->read(clk, nv_clk_src_hclk) * 3; 427 freq = calc_div(freq, dom6, &P1); 428 429 mastv |= 0x0c000000; 430 divsv |= P1; 431 } 432 433 mastm |= 0x0c000000; 434 divsm |= 0x00000007; 435 } 436 437 /* vdec/dom6: switch to "safe" clocks temporarily, update dividers 438 * and then switch to target clocks 439 */ 440 clk_mask(hwsq, mast, mastm, 0x00000000); 441 clk_mask(hwsq, divs, divsm, divsv); 442 clk_mask(hwsq, mast, mastm, mastv); 443 444 /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, 445 * sclk to hclk) before reprogramming 446 */ 447 if (nv_device(priv)->chipset < 0x92) 448 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); 449 else 450 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); 451 452 /* core: for the moment at least, always use nvpll */ 453 freq = calc_pll(priv, 0x4028, core, &N, &M, &P1); 454 if (freq == 0) 455 return -ERANGE; 456 457 clk_mask(hwsq, nvpll[0], 0xc03f0100, 458 0x80000000 | (P1 << 19) | (P1 << 16)); 459 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); 460 461 /* shader: tie to nvclk if possible, otherwise use spll. have to be 462 * very careful that the shader clock is at least twice the core, or 463 * some chipsets will be very unhappy. i expect most or all of these 464 * cases will be handled by tying to nvclk, but it's possible there's 465 * corners 466 */ 467 if (P1-- && shader == (core << 1)) { 468 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); 469 clk_mask(hwsq, mast, 0x00100033, 0x00000023); 470 } else { 471 freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1); 472 if (freq == 0) 473 return -ERANGE; 474 475 clk_mask(hwsq, spll[0], 0xc03f0100, 476 0x80000000 | (P1 << 19) | (P1 << 16)); 477 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); 478 clk_mask(hwsq, mast, 0x00100033, 0x00000033); 479 } 480 481 /* restore normal operation */ 482 clk_setf(hwsq, 0x10, 0x01); /* enable fb */ 483 clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ 484 clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ 485 return 0; 486} 487 488static int 489nv50_clk_prog(struct nvkm_clk *clk) 490{ 491 struct nv50_clk_priv *priv = (void *)clk; 492 return clk_exec(&priv->hwsq, true); 493} 494 495static void 496nv50_clk_tidy(struct nvkm_clk *clk) 497{ 498 struct nv50_clk_priv *priv = (void *)clk; 499 clk_exec(&priv->hwsq, false); 500} 501 502int 503nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 504 struct nvkm_oclass *oclass, void *data, u32 size, 505 struct nvkm_object **pobject) 506{ 507 struct nv50_clk_oclass *pclass = (void *)oclass; 508 struct nv50_clk_priv *priv; 509 int ret; 510 511 ret = nvkm_clk_create(parent, engine, oclass, pclass->domains, 512 NULL, 0, false, &priv); 513 *pobject = nv_object(priv); 514 if (ret) 515 return ret; 516 517 priv->hwsq.r_fifo = hwsq_reg(0x002504); 518 priv->hwsq.r_spll[0] = hwsq_reg(0x004020); 519 priv->hwsq.r_spll[1] = hwsq_reg(0x004024); 520 priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028); 521 priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); 522 switch (nv_device(priv)->chipset) { 523 case 0x92: 524 case 0x94: 525 case 0x96: 526 priv->hwsq.r_divs = hwsq_reg(0x004800); 527 break; 528 default: 529 priv->hwsq.r_divs = hwsq_reg(0x004700); 530 break; 531 } 532 priv->hwsq.r_mast = hwsq_reg(0x00c040); 533 534 priv->base.read = nv50_clk_read; 535 priv->base.calc = nv50_clk_calc; 536 priv->base.prog = nv50_clk_prog; 537 priv->base.tidy = nv50_clk_tidy; 538 return 0; 539} 540 541static struct nvkm_domain 542nv50_domains[] = { 543 { nv_clk_src_crystal, 0xff }, 544 { nv_clk_src_href , 0xff }, 545 { nv_clk_src_core , 0xff, 0, "core", 1000 }, 546 { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, 547 { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, 548 { nv_clk_src_max } 549}; 550 551struct nvkm_oclass * 552nv50_clk_oclass = &(struct nv50_clk_oclass) { 553 .base.handle = NV_SUBDEV(CLK, 0x50), 554 .base.ofuncs = &(struct nvkm_ofuncs) { 555 .ctor = nv50_clk_ctor, 556 .dtor = _nvkm_clk_dtor, 557 .init = _nvkm_clk_init, 558 .fini = _nvkm_clk_fini, 559 }, 560 .domains = nv50_domains, 561}.base; 562