1/*
2 * Copyright 2014 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <subdev/fb.h>
27#include <subdev/timer.h>
28
29static void
30gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
31{
32	nv_wr32(priv, 0x17e270, start);
33	nv_wr32(priv, 0x17e274, limit);
34	nv_wr32(priv, 0x17e26c, 0x00000004);
35}
36
37static void
38gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
39{
40	int c, s;
41	for (c = 0; c < priv->ltc_nr; c++) {
42		for (s = 0; s < priv->lts_nr; s++)
43			nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0);
44	}
45}
46
47static void
48gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4])
49{
50	nv_mask(priv, 0x17e338, 0x0000000f, i);
51	nv_wr32(priv, 0x17e33c, color[0]);
52	nv_wr32(priv, 0x17e340, color[1]);
53	nv_wr32(priv, 0x17e344, color[2]);
54	nv_wr32(priv, 0x17e348, color[3]);
55}
56
57static void
58gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth)
59{
60	nv_mask(priv, 0x17e338, 0x0000000f, i);
61	nv_wr32(priv, 0x17e34c, depth);
62}
63
64static void
65gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
66{
67	u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400);
68	u32 stat = nv_rd32(priv, base + 0x00c);
69
70	if (stat) {
71		nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat);
72		nv_wr32(priv, base + 0x00c, stat);
73	}
74}
75
76static void
77gm107_ltc_intr(struct nvkm_subdev *subdev)
78{
79	struct nvkm_ltc_priv *priv = (void *)subdev;
80	u32 mask;
81
82	mask = nv_rd32(priv, 0x00017c);
83	while (mask) {
84		u32 lts, ltc = __ffs(mask);
85		for (lts = 0; lts < priv->lts_nr; lts++)
86			gm107_ltc_lts_isr(priv, ltc, lts);
87		mask &= ~(1 << ltc);
88	}
89}
90
91static int
92gm107_ltc_init(struct nvkm_object *object)
93{
94	struct nvkm_ltc_priv *priv = (void *)object;
95	u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001);
96	int ret;
97
98	ret = nvkm_ltc_init(priv);
99	if (ret)
100		return ret;
101
102	nv_wr32(priv, 0x17e27c, priv->ltc_nr);
103	nv_wr32(priv, 0x17e278, priv->tag_base);
104	nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000);
105	return 0;
106}
107
108static int
109gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
110	       struct nvkm_oclass *oclass, void *data, u32 size,
111	       struct nvkm_object **pobject)
112{
113	struct nvkm_fb *pfb = nvkm_fb(parent);
114	struct nvkm_ltc_priv *priv;
115	u32 parts, mask;
116	int ret, i;
117
118	ret = nvkm_ltc_create(parent, engine, oclass, &priv);
119	*pobject = nv_object(priv);
120	if (ret)
121		return ret;
122
123	parts = nv_rd32(priv, 0x022438);
124	mask = nv_rd32(priv, 0x021c14);
125	for (i = 0; i < parts; i++) {
126		if (!(mask & (1 << i)))
127			priv->ltc_nr++;
128	}
129	priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28;
130
131	ret = gf100_ltc_init_tag_ram(pfb, priv);
132	if (ret)
133		return ret;
134
135	return 0;
136}
137
138struct nvkm_oclass *
139gm107_ltc_oclass = &(struct nvkm_ltc_impl) {
140	.base.handle = NV_SUBDEV(LTC, 0xff),
141	.base.ofuncs = &(struct nvkm_ofuncs) {
142		.ctor = gm107_ltc_ctor,
143		.dtor = gf100_ltc_dtor,
144		.init = gm107_ltc_init,
145		.fini = _nvkm_ltc_fini,
146	},
147	.intr = gm107_ltc_intr,
148	.cbc_clear = gm107_ltc_cbc_clear,
149	.cbc_wait = gm107_ltc_cbc_wait,
150	.zbc = 16,
151	.zbc_clear_color = gm107_ltc_zbc_clear_color,
152	.zbc_clear_depth = gm107_ltc_zbc_clear_depth,
153}.base;
154