1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28#ifndef __RADEON_H__ 29#define __RADEON_H__ 30 31/* TODO: Here are things that needs to be done : 32 * - surface allocator & initializer : (bit like scratch reg) should 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 34 * related to surface 35 * - WB : write back stuff (do it bit like scratch reg things) 36 * - Vblank : look at Jesse's rework and what we should do 37 * - r600/r700: gart & cp 38 * - cs : clean cs ioctl use bitmap & things like that. 39 * - power management stuff 40 * - Barrier in gart code 41 * - Unmappabled vram ? 42 * - TESTING, TESTING, TESTING 43 */ 44 45/* Initialization path: 46 * We expect that acceleration initialization might fail for various 47 * reasons even thought we work hard to make it works on most 48 * configurations. In order to still have a working userspace in such 49 * situation the init path must succeed up to the memory controller 50 * initialization point. Failure before this point are considered as 51 * fatal error. Here is the init callchain : 52 * radeon_device_init perform common structure, mutex initialization 53 * asic_init setup the GPU memory layout and perform all 54 * one time initialization (failure in this 55 * function are considered fatal) 56 * asic_startup setup the GPU acceleration, in order to 57 * follow guideline the first thing this 58 * function should do is setting the GPU 59 * memory controller (only MC setup failure 60 * are considered as fatal) 61 */ 62 63#include <linux/atomic.h> 64#include <linux/wait.h> 65#include <linux/list.h> 66#include <linux/kref.h> 67#include <linux/interval_tree.h> 68#include <linux/hashtable.h> 69#include <linux/fence.h> 70 71#include <ttm/ttm_bo_api.h> 72#include <ttm/ttm_bo_driver.h> 73#include <ttm/ttm_placement.h> 74#include <ttm/ttm_module.h> 75#include <ttm/ttm_execbuf_util.h> 76 77#include <drm/drm_gem.h> 78 79#include "radeon_family.h" 80#include "radeon_mode.h" 81#include "radeon_reg.h" 82 83/* 84 * Modules parameters. 85 */ 86extern int radeon_no_wb; 87extern int radeon_modeset; 88extern int radeon_dynclks; 89extern int radeon_r4xx_atom; 90extern int radeon_agpmode; 91extern int radeon_vram_limit; 92extern int radeon_gart_size; 93extern int radeon_benchmarking; 94extern int radeon_testing; 95extern int radeon_connector_table; 96extern int radeon_tv; 97extern int radeon_audio; 98extern int radeon_disp_priority; 99extern int radeon_hw_i2c; 100extern int radeon_pcie_gen2; 101extern int radeon_msi; 102extern int radeon_lockup_timeout; 103extern int radeon_fastfb; 104extern int radeon_dpm; 105extern int radeon_aspm; 106extern int radeon_runtime_pm; 107extern int radeon_hard_reset; 108extern int radeon_vm_size; 109extern int radeon_vm_block_size; 110extern int radeon_deep_color; 111extern int radeon_use_pflipirq; 112extern int radeon_bapm; 113extern int radeon_backlight; 114extern int radeon_auxch; 115extern int radeon_mst; 116 117/* 118 * Copy from radeon_drv.h so we don't have to include both and have conflicting 119 * symbol; 120 */ 121#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 122#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 123/* RADEON_IB_POOL_SIZE must be a power of 2 */ 124#define RADEON_IB_POOL_SIZE 16 125#define RADEON_DEBUGFS_MAX_COMPONENTS 32 126#define RADEONFB_CONN_LIMIT 4 127#define RADEON_BIOS_NUM_SCRATCH 8 128 129/* internal ring indices */ 130/* r1xx+ has gfx CP ring */ 131#define RADEON_RING_TYPE_GFX_INDEX 0 132 133/* cayman has 2 compute CP rings */ 134#define CAYMAN_RING_TYPE_CP1_INDEX 1 135#define CAYMAN_RING_TYPE_CP2_INDEX 2 136 137/* R600+ has an async dma ring */ 138#define R600_RING_TYPE_DMA_INDEX 3 139/* cayman add a second async dma ring */ 140#define CAYMAN_RING_TYPE_DMA1_INDEX 4 141 142/* R600+ */ 143#define R600_RING_TYPE_UVD_INDEX 5 144 145/* TN+ */ 146#define TN_RING_TYPE_VCE1_INDEX 6 147#define TN_RING_TYPE_VCE2_INDEX 7 148 149/* max number of rings */ 150#define RADEON_NUM_RINGS 8 151 152/* number of hw syncs before falling back on blocking */ 153#define RADEON_NUM_SYNCS 4 154 155/* hardcode those limit for now */ 156#define RADEON_VA_IB_OFFSET (1 << 20) 157#define RADEON_VA_RESERVED_SIZE (8 << 20) 158#define RADEON_IB_VM_MAX_SIZE (64 << 10) 159 160/* hard reset data */ 161#define RADEON_ASIC_RESET_DATA 0x39d5e86b 162 163/* reset flags */ 164#define RADEON_RESET_GFX (1 << 0) 165#define RADEON_RESET_COMPUTE (1 << 1) 166#define RADEON_RESET_DMA (1 << 2) 167#define RADEON_RESET_CP (1 << 3) 168#define RADEON_RESET_GRBM (1 << 4) 169#define RADEON_RESET_DMA1 (1 << 5) 170#define RADEON_RESET_RLC (1 << 6) 171#define RADEON_RESET_SEM (1 << 7) 172#define RADEON_RESET_IH (1 << 8) 173#define RADEON_RESET_VMC (1 << 9) 174#define RADEON_RESET_MC (1 << 10) 175#define RADEON_RESET_DISPLAY (1 << 11) 176 177/* CG block flags */ 178#define RADEON_CG_BLOCK_GFX (1 << 0) 179#define RADEON_CG_BLOCK_MC (1 << 1) 180#define RADEON_CG_BLOCK_SDMA (1 << 2) 181#define RADEON_CG_BLOCK_UVD (1 << 3) 182#define RADEON_CG_BLOCK_VCE (1 << 4) 183#define RADEON_CG_BLOCK_HDP (1 << 5) 184#define RADEON_CG_BLOCK_BIF (1 << 6) 185 186/* CG flags */ 187#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0) 188#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1) 189#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2) 190#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3) 191#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4) 192#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 193#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6) 194#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7) 195#define RADEON_CG_SUPPORT_MC_LS (1 << 8) 196#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9) 197#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10) 198#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11) 199#define RADEON_CG_SUPPORT_BIF_LS (1 << 12) 200#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13) 201#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14) 202#define RADEON_CG_SUPPORT_HDP_LS (1 << 15) 203#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16) 204 205/* PG flags */ 206#define RADEON_PG_SUPPORT_GFX_PG (1 << 0) 207#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1) 208#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2) 209#define RADEON_PG_SUPPORT_UVD (1 << 3) 210#define RADEON_PG_SUPPORT_VCE (1 << 4) 211#define RADEON_PG_SUPPORT_CP (1 << 5) 212#define RADEON_PG_SUPPORT_GDS (1 << 6) 213#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7) 214#define RADEON_PG_SUPPORT_SDMA (1 << 8) 215#define RADEON_PG_SUPPORT_ACP (1 << 9) 216#define RADEON_PG_SUPPORT_SAMU (1 << 10) 217 218/* max cursor sizes (in pixels) */ 219#define CURSOR_WIDTH 64 220#define CURSOR_HEIGHT 64 221 222#define CIK_CURSOR_WIDTH 128 223#define CIK_CURSOR_HEIGHT 128 224 225/* 226 * Errata workarounds. 227 */ 228enum radeon_pll_errata { 229 CHIP_ERRATA_R300_CG = 0x00000001, 230 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 231 CHIP_ERRATA_PLL_DELAY = 0x00000004 232}; 233 234 235struct radeon_device; 236 237 238/* 239 * BIOS. 240 */ 241bool radeon_get_bios(struct radeon_device *rdev); 242 243/* 244 * Dummy page 245 */ 246struct radeon_dummy_page { 247 uint64_t entry; 248 struct page *page; 249 dma_addr_t addr; 250}; 251int radeon_dummy_page_init(struct radeon_device *rdev); 252void radeon_dummy_page_fini(struct radeon_device *rdev); 253 254 255/* 256 * Clocks 257 */ 258struct radeon_clock { 259 struct radeon_pll p1pll; 260 struct radeon_pll p2pll; 261 struct radeon_pll dcpll; 262 struct radeon_pll spll; 263 struct radeon_pll mpll; 264 /* 10 Khz units */ 265 uint32_t default_mclk; 266 uint32_t default_sclk; 267 uint32_t default_dispclk; 268 uint32_t current_dispclk; 269 uint32_t dp_extclk; 270 uint32_t max_pixel_clock; 271 uint32_t vco_freq; 272}; 273 274/* 275 * Power management 276 */ 277int radeon_pm_init(struct radeon_device *rdev); 278int radeon_pm_late_init(struct radeon_device *rdev); 279void radeon_pm_fini(struct radeon_device *rdev); 280void radeon_pm_compute_clocks(struct radeon_device *rdev); 281void radeon_pm_suspend(struct radeon_device *rdev); 282void radeon_pm_resume(struct radeon_device *rdev); 283void radeon_combios_get_power_modes(struct radeon_device *rdev); 284void radeon_atombios_get_power_modes(struct radeon_device *rdev); 285int radeon_atom_get_clock_dividers(struct radeon_device *rdev, 286 u8 clock_type, 287 u32 clock, 288 bool strobe_mode, 289 struct atom_clock_dividers *dividers); 290int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev, 291 u32 clock, 292 bool strobe_mode, 293 struct atom_mpll_param *mpll_param); 294void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 295int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev, 296 u16 voltage_level, u8 voltage_type, 297 u32 *gpio_value, u32 *gpio_mask); 298void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev, 299 u32 eng_clock, u32 mem_clock); 300int radeon_atom_get_voltage_step(struct radeon_device *rdev, 301 u8 voltage_type, u16 *voltage_step); 302int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 303 u16 voltage_id, u16 *voltage); 304int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev, 305 u16 *voltage, 306 u16 leakage_idx); 307int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev, 308 u16 *leakage_id); 309int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev, 310 u16 *vddc, u16 *vddci, 311 u16 virtual_voltage_id, 312 u16 vbios_voltage_id); 313int radeon_atom_get_voltage_evv(struct radeon_device *rdev, 314 u16 virtual_voltage_id, 315 u16 *voltage); 316int radeon_atom_round_to_true_voltage(struct radeon_device *rdev, 317 u8 voltage_type, 318 u16 nominal_voltage, 319 u16 *true_voltage); 320int radeon_atom_get_min_voltage(struct radeon_device *rdev, 321 u8 voltage_type, u16 *min_voltage); 322int radeon_atom_get_max_voltage(struct radeon_device *rdev, 323 u8 voltage_type, u16 *max_voltage); 324int radeon_atom_get_voltage_table(struct radeon_device *rdev, 325 u8 voltage_type, u8 voltage_mode, 326 struct atom_voltage_table *voltage_table); 327bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev, 328 u8 voltage_type, u8 voltage_mode); 329int radeon_atom_get_svi2_info(struct radeon_device *rdev, 330 u8 voltage_type, 331 u8 *svd_gpio_id, u8 *svc_gpio_id); 332void radeon_atom_update_memory_dll(struct radeon_device *rdev, 333 u32 mem_clock); 334void radeon_atom_set_ac_timing(struct radeon_device *rdev, 335 u32 mem_clock); 336int radeon_atom_init_mc_reg_table(struct radeon_device *rdev, 337 u8 module_index, 338 struct atom_mc_reg_table *reg_table); 339int radeon_atom_get_memory_info(struct radeon_device *rdev, 340 u8 module_index, struct atom_memory_info *mem_info); 341int radeon_atom_get_mclk_range_table(struct radeon_device *rdev, 342 bool gddr5, u8 module_index, 343 struct atom_memory_clock_range_table *mclk_range_table); 344int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type, 345 u16 voltage_id, u16 *voltage); 346void rs690_pm_info(struct radeon_device *rdev); 347extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 348 unsigned *bankh, unsigned *mtaspect, 349 unsigned *tile_split); 350 351/* 352 * Fences. 353 */ 354struct radeon_fence_driver { 355 struct radeon_device *rdev; 356 uint32_t scratch_reg; 357 uint64_t gpu_addr; 358 volatile uint32_t *cpu_addr; 359 /* sync_seq is protected by ring emission lock */ 360 uint64_t sync_seq[RADEON_NUM_RINGS]; 361 atomic64_t last_seq; 362 bool initialized, delayed_irq; 363 struct delayed_work lockup_work; 364}; 365 366struct radeon_fence { 367 struct fence base; 368 369 struct radeon_device *rdev; 370 uint64_t seq; 371 /* RB, DMA, etc. */ 372 unsigned ring; 373 bool is_vm_update; 374 375 wait_queue_t fence_wake; 376}; 377 378int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 379int radeon_fence_driver_init(struct radeon_device *rdev); 380void radeon_fence_driver_fini(struct radeon_device *rdev); 381void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring); 382int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 383void radeon_fence_process(struct radeon_device *rdev, int ring); 384bool radeon_fence_signaled(struct radeon_fence *fence); 385int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 386int radeon_fence_wait_next(struct radeon_device *rdev, int ring); 387int radeon_fence_wait_empty(struct radeon_device *rdev, int ring); 388int radeon_fence_wait_any(struct radeon_device *rdev, 389 struct radeon_fence **fences, 390 bool intr); 391struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 392void radeon_fence_unref(struct radeon_fence **fence); 393unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 394bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 395void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 396static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 397 struct radeon_fence *b) 398{ 399 if (!a) { 400 return b; 401 } 402 403 if (!b) { 404 return a; 405 } 406 407 BUG_ON(a->ring != b->ring); 408 409 if (a->seq > b->seq) { 410 return a; 411 } else { 412 return b; 413 } 414} 415 416static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 417 struct radeon_fence *b) 418{ 419 if (!a) { 420 return false; 421 } 422 423 if (!b) { 424 return true; 425 } 426 427 BUG_ON(a->ring != b->ring); 428 429 return a->seq < b->seq; 430} 431 432/* 433 * Tiling registers 434 */ 435struct radeon_surface_reg { 436 struct radeon_bo *bo; 437}; 438 439#define RADEON_GEM_MAX_SURFACES 8 440 441/* 442 * TTM. 443 */ 444struct radeon_mman { 445 struct ttm_bo_global_ref bo_global_ref; 446 struct drm_global_reference mem_global_ref; 447 struct ttm_bo_device bdev; 448 bool mem_global_referenced; 449 bool initialized; 450 451#if defined(CONFIG_DEBUG_FS) 452 struct dentry *vram; 453 struct dentry *gtt; 454#endif 455}; 456 457struct radeon_bo_list { 458 struct radeon_bo *robj; 459 struct ttm_validate_buffer tv; 460 uint64_t gpu_offset; 461 unsigned prefered_domains; 462 unsigned allowed_domains; 463 uint32_t tiling_flags; 464}; 465 466/* bo virtual address in a specific vm */ 467struct radeon_bo_va { 468 /* protected by bo being reserved */ 469 struct list_head bo_list; 470 uint32_t flags; 471 uint64_t addr; 472 struct radeon_fence *last_pt_update; 473 unsigned ref_count; 474 475 /* protected by vm mutex */ 476 struct interval_tree_node it; 477 struct list_head vm_status; 478 479 /* constant after initialization */ 480 struct radeon_vm *vm; 481 struct radeon_bo *bo; 482}; 483 484struct radeon_bo { 485 /* Protected by gem.mutex */ 486 struct list_head list; 487 /* Protected by tbo.reserved */ 488 u32 initial_domain; 489 struct ttm_place placements[4]; 490 struct ttm_placement placement; 491 struct ttm_buffer_object tbo; 492 struct ttm_bo_kmap_obj kmap; 493 u32 flags; 494 unsigned pin_count; 495 void *kptr; 496 u32 tiling_flags; 497 u32 pitch; 498 int surface_reg; 499 /* list of all virtual address to which this bo 500 * is associated to 501 */ 502 struct list_head va; 503 /* Constant after initialization */ 504 struct radeon_device *rdev; 505 struct drm_gem_object gem_base; 506 507 struct ttm_bo_kmap_obj dma_buf_vmap; 508 pid_t pid; 509 510 struct radeon_mn *mn; 511 struct list_head mn_list; 512}; 513#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 514 515int radeon_gem_debugfs_init(struct radeon_device *rdev); 516 517/* sub-allocation manager, it has to be protected by another lock. 518 * By conception this is an helper for other part of the driver 519 * like the indirect buffer or semaphore, which both have their 520 * locking. 521 * 522 * Principe is simple, we keep a list of sub allocation in offset 523 * order (first entry has offset == 0, last entry has the highest 524 * offset). 525 * 526 * When allocating new object we first check if there is room at 527 * the end total_size - (last_object_offset + last_object_size) >= 528 * alloc_size. If so we allocate new object there. 529 * 530 * When there is not enough room at the end, we start waiting for 531 * each sub object until we reach object_offset+object_size >= 532 * alloc_size, this object then become the sub object we return. 533 * 534 * Alignment can't be bigger than page size. 535 * 536 * Hole are not considered for allocation to keep things simple. 537 * Assumption is that there won't be hole (all object on same 538 * alignment). 539 */ 540struct radeon_sa_manager { 541 wait_queue_head_t wq; 542 struct radeon_bo *bo; 543 struct list_head *hole; 544 struct list_head flist[RADEON_NUM_RINGS]; 545 struct list_head olist; 546 unsigned size; 547 uint64_t gpu_addr; 548 void *cpu_ptr; 549 uint32_t domain; 550 uint32_t align; 551}; 552 553struct radeon_sa_bo; 554 555/* sub-allocation buffer */ 556struct radeon_sa_bo { 557 struct list_head olist; 558 struct list_head flist; 559 struct radeon_sa_manager *manager; 560 unsigned soffset; 561 unsigned eoffset; 562 struct radeon_fence *fence; 563}; 564 565/* 566 * GEM objects. 567 */ 568struct radeon_gem { 569 struct mutex mutex; 570 struct list_head objects; 571}; 572 573int radeon_gem_init(struct radeon_device *rdev); 574void radeon_gem_fini(struct radeon_device *rdev); 575int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 576 int alignment, int initial_domain, 577 u32 flags, bool kernel, 578 struct drm_gem_object **obj); 579 580int radeon_mode_dumb_create(struct drm_file *file_priv, 581 struct drm_device *dev, 582 struct drm_mode_create_dumb *args); 583int radeon_mode_dumb_mmap(struct drm_file *filp, 584 struct drm_device *dev, 585 uint32_t handle, uint64_t *offset_p); 586 587/* 588 * Semaphores. 589 */ 590struct radeon_semaphore { 591 struct radeon_sa_bo *sa_bo; 592 signed waiters; 593 uint64_t gpu_addr; 594}; 595 596int radeon_semaphore_create(struct radeon_device *rdev, 597 struct radeon_semaphore **semaphore); 598bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 599 struct radeon_semaphore *semaphore); 600bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 601 struct radeon_semaphore *semaphore); 602void radeon_semaphore_free(struct radeon_device *rdev, 603 struct radeon_semaphore **semaphore, 604 struct radeon_fence *fence); 605 606/* 607 * Synchronization 608 */ 609struct radeon_sync { 610 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS]; 611 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 612 struct radeon_fence *last_vm_update; 613}; 614 615void radeon_sync_create(struct radeon_sync *sync); 616void radeon_sync_fence(struct radeon_sync *sync, 617 struct radeon_fence *fence); 618int radeon_sync_resv(struct radeon_device *rdev, 619 struct radeon_sync *sync, 620 struct reservation_object *resv, 621 bool shared); 622int radeon_sync_rings(struct radeon_device *rdev, 623 struct radeon_sync *sync, 624 int waiting_ring); 625void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync, 626 struct radeon_fence *fence); 627 628/* 629 * GART structures, functions & helpers 630 */ 631struct radeon_mc; 632 633#define RADEON_GPU_PAGE_SIZE 4096 634#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 635#define RADEON_GPU_PAGE_SHIFT 12 636#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 637 638#define RADEON_GART_PAGE_DUMMY 0 639#define RADEON_GART_PAGE_VALID (1 << 0) 640#define RADEON_GART_PAGE_READ (1 << 1) 641#define RADEON_GART_PAGE_WRITE (1 << 2) 642#define RADEON_GART_PAGE_SNOOP (1 << 3) 643 644struct radeon_gart { 645 dma_addr_t table_addr; 646 struct radeon_bo *robj; 647 void *ptr; 648 unsigned num_gpu_pages; 649 unsigned num_cpu_pages; 650 unsigned table_size; 651 struct page **pages; 652 uint64_t *pages_entry; 653 bool ready; 654}; 655 656int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 657void radeon_gart_table_ram_free(struct radeon_device *rdev); 658int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 659void radeon_gart_table_vram_free(struct radeon_device *rdev); 660int radeon_gart_table_vram_pin(struct radeon_device *rdev); 661void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 662int radeon_gart_init(struct radeon_device *rdev); 663void radeon_gart_fini(struct radeon_device *rdev); 664void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 665 int pages); 666int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 667 int pages, struct page **pagelist, 668 dma_addr_t *dma_addr, uint32_t flags); 669 670 671/* 672 * GPU MC structures, functions & helpers 673 */ 674struct radeon_mc { 675 resource_size_t aper_size; 676 resource_size_t aper_base; 677 resource_size_t agp_base; 678 /* for some chips with <= 32MB we need to lie 679 * about vram size near mc fb location */ 680 u64 mc_vram_size; 681 u64 visible_vram_size; 682 u64 gtt_size; 683 u64 gtt_start; 684 u64 gtt_end; 685 u64 vram_start; 686 u64 vram_end; 687 unsigned vram_width; 688 u64 real_vram_size; 689 int vram_mtrr; 690 bool vram_is_ddr; 691 bool igp_sideport_enabled; 692 u64 gtt_base_align; 693 u64 mc_mask; 694}; 695 696bool radeon_combios_sideport_present(struct radeon_device *rdev); 697bool radeon_atombios_sideport_present(struct radeon_device *rdev); 698 699/* 700 * GPU scratch registers structures, functions & helpers 701 */ 702struct radeon_scratch { 703 unsigned num_reg; 704 uint32_t reg_base; 705 bool free[32]; 706 uint32_t reg[32]; 707}; 708 709int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 710void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 711 712/* 713 * GPU doorbell structures, functions & helpers 714 */ 715#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */ 716 717struct radeon_doorbell { 718 /* doorbell mmio */ 719 resource_size_t base; 720 resource_size_t size; 721 u32 __iomem *ptr; 722 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */ 723 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)]; 724}; 725 726int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 727void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 728void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 729 phys_addr_t *aperture_base, 730 size_t *aperture_size, 731 size_t *start_offset); 732 733/* 734 * IRQS. 735 */ 736 737struct radeon_flip_work { 738 struct work_struct flip_work; 739 struct work_struct unpin_work; 740 struct radeon_device *rdev; 741 int crtc_id; 742 uint64_t base; 743 struct drm_pending_vblank_event *event; 744 struct radeon_bo *old_rbo; 745 struct fence *fence; 746}; 747 748struct r500_irq_stat_regs { 749 u32 disp_int; 750 u32 hdmi0_status; 751}; 752 753struct r600_irq_stat_regs { 754 u32 disp_int; 755 u32 disp_int_cont; 756 u32 disp_int_cont2; 757 u32 d1grph_int; 758 u32 d2grph_int; 759 u32 hdmi0_status; 760 u32 hdmi1_status; 761}; 762 763struct evergreen_irq_stat_regs { 764 u32 disp_int; 765 u32 disp_int_cont; 766 u32 disp_int_cont2; 767 u32 disp_int_cont3; 768 u32 disp_int_cont4; 769 u32 disp_int_cont5; 770 u32 d1grph_int; 771 u32 d2grph_int; 772 u32 d3grph_int; 773 u32 d4grph_int; 774 u32 d5grph_int; 775 u32 d6grph_int; 776 u32 afmt_status1; 777 u32 afmt_status2; 778 u32 afmt_status3; 779 u32 afmt_status4; 780 u32 afmt_status5; 781 u32 afmt_status6; 782}; 783 784struct cik_irq_stat_regs { 785 u32 disp_int; 786 u32 disp_int_cont; 787 u32 disp_int_cont2; 788 u32 disp_int_cont3; 789 u32 disp_int_cont4; 790 u32 disp_int_cont5; 791 u32 disp_int_cont6; 792 u32 d1grph_int; 793 u32 d2grph_int; 794 u32 d3grph_int; 795 u32 d4grph_int; 796 u32 d5grph_int; 797 u32 d6grph_int; 798}; 799 800union radeon_irq_stat_regs { 801 struct r500_irq_stat_regs r500; 802 struct r600_irq_stat_regs r600; 803 struct evergreen_irq_stat_regs evergreen; 804 struct cik_irq_stat_regs cik; 805}; 806 807struct radeon_irq { 808 bool installed; 809 spinlock_t lock; 810 atomic_t ring_int[RADEON_NUM_RINGS]; 811 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 812 atomic_t pflip[RADEON_MAX_CRTCS]; 813 wait_queue_head_t vblank_queue; 814 bool hpd[RADEON_MAX_HPD_PINS]; 815 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 816 union radeon_irq_stat_regs stat_regs; 817 bool dpm_thermal; 818}; 819 820int radeon_irq_kms_init(struct radeon_device *rdev); 821void radeon_irq_kms_fini(struct radeon_device *rdev); 822void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 823bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring); 824void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 825void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 826void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 827void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 828void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 829void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 830void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 831 832/* 833 * CP & rings. 834 */ 835 836struct radeon_ib { 837 struct radeon_sa_bo *sa_bo; 838 uint32_t length_dw; 839 uint64_t gpu_addr; 840 uint32_t *ptr; 841 int ring; 842 struct radeon_fence *fence; 843 struct radeon_vm *vm; 844 bool is_const_ib; 845 struct radeon_sync sync; 846}; 847 848struct radeon_ring { 849 struct radeon_bo *ring_obj; 850 volatile uint32_t *ring; 851 unsigned rptr_offs; 852 unsigned rptr_save_reg; 853 u64 next_rptr_gpu_addr; 854 volatile u32 *next_rptr_cpu_addr; 855 unsigned wptr; 856 unsigned wptr_old; 857 unsigned ring_size; 858 unsigned ring_free_dw; 859 int count_dw; 860 atomic_t last_rptr; 861 atomic64_t last_activity; 862 uint64_t gpu_addr; 863 uint32_t align_mask; 864 uint32_t ptr_mask; 865 bool ready; 866 u32 nop; 867 u32 idx; 868 u64 last_semaphore_signal_addr; 869 u64 last_semaphore_wait_addr; 870 /* for CIK queues */ 871 u32 me; 872 u32 pipe; 873 u32 queue; 874 struct radeon_bo *mqd_obj; 875 u32 doorbell_index; 876 unsigned wptr_offs; 877}; 878 879struct radeon_mec { 880 struct radeon_bo *hpd_eop_obj; 881 u64 hpd_eop_gpu_addr; 882 u32 num_pipe; 883 u32 num_mec; 884 u32 num_queue; 885}; 886 887/* 888 * VM 889 */ 890 891/* maximum number of VMIDs */ 892#define RADEON_NUM_VM 16 893 894/* number of entries in page table */ 895#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size) 896 897/* PTBs (Page Table Blocks) need to be aligned to 32K */ 898#define RADEON_VM_PTB_ALIGN_SIZE 32768 899#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) 900#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) 901 902#define R600_PTE_VALID (1 << 0) 903#define R600_PTE_SYSTEM (1 << 1) 904#define R600_PTE_SNOOPED (1 << 2) 905#define R600_PTE_READABLE (1 << 5) 906#define R600_PTE_WRITEABLE (1 << 6) 907 908/* PTE (Page Table Entry) fragment field for different page sizes */ 909#define R600_PTE_FRAG_4KB (0 << 7) 910#define R600_PTE_FRAG_64KB (4 << 7) 911#define R600_PTE_FRAG_256KB (6 << 7) 912 913/* flags needed to be set so we can copy directly from the GART table */ 914#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \ 915 R600_PTE_SYSTEM | R600_PTE_VALID ) 916 917struct radeon_vm_pt { 918 struct radeon_bo *bo; 919 uint64_t addr; 920}; 921 922struct radeon_vm_id { 923 unsigned id; 924 uint64_t pd_gpu_addr; 925 /* last flushed PD/PT update */ 926 struct radeon_fence *flushed_updates; 927 /* last use of vmid */ 928 struct radeon_fence *last_id_use; 929}; 930 931struct radeon_vm { 932 struct mutex mutex; 933 934 struct rb_root va; 935 936 /* protecting invalidated and freed */ 937 spinlock_t status_lock; 938 939 /* BOs moved, but not yet updated in the PT */ 940 struct list_head invalidated; 941 942 /* BOs freed, but not yet updated in the PT */ 943 struct list_head freed; 944 945 /* contains the page directory */ 946 struct radeon_bo *page_directory; 947 unsigned max_pde_used; 948 949 /* array of page tables, one for each page directory entry */ 950 struct radeon_vm_pt *page_tables; 951 952 struct radeon_bo_va *ib_bo_va; 953 954 /* for id and flush management per ring */ 955 struct radeon_vm_id ids[RADEON_NUM_RINGS]; 956}; 957 958struct radeon_vm_manager { 959 struct radeon_fence *active[RADEON_NUM_VM]; 960 uint32_t max_pfn; 961 /* number of VMIDs */ 962 unsigned nvm; 963 /* vram base address for page table entry */ 964 u64 vram_base_offset; 965 /* is vm enabled? */ 966 bool enabled; 967 /* for hw to save the PD addr on suspend/resume */ 968 uint32_t saved_table_addr[RADEON_NUM_VM]; 969}; 970 971/* 972 * file private structure 973 */ 974struct radeon_fpriv { 975 struct radeon_vm vm; 976}; 977 978/* 979 * R6xx+ IH ring 980 */ 981struct r600_ih { 982 struct radeon_bo *ring_obj; 983 volatile uint32_t *ring; 984 unsigned rptr; 985 unsigned ring_size; 986 uint64_t gpu_addr; 987 uint32_t ptr_mask; 988 atomic_t lock; 989 bool enabled; 990}; 991 992/* 993 * RLC stuff 994 */ 995#include "clearstate_defs.h" 996 997struct radeon_rlc { 998 /* for power gating */ 999 struct radeon_bo *save_restore_obj; 1000 uint64_t save_restore_gpu_addr; 1001 volatile uint32_t *sr_ptr; 1002 const u32 *reg_list; 1003 u32 reg_list_size; 1004 /* for clear state */ 1005 struct radeon_bo *clear_state_obj; 1006 uint64_t clear_state_gpu_addr; 1007 volatile uint32_t *cs_ptr; 1008 const struct cs_section_def *cs_data; 1009 u32 clear_state_size; 1010 /* for cp tables */ 1011 struct radeon_bo *cp_table_obj; 1012 uint64_t cp_table_gpu_addr; 1013 volatile uint32_t *cp_table_ptr; 1014 u32 cp_table_size; 1015}; 1016 1017int radeon_ib_get(struct radeon_device *rdev, int ring, 1018 struct radeon_ib *ib, struct radeon_vm *vm, 1019 unsigned size); 1020void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 1021int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 1022 struct radeon_ib *const_ib, bool hdp_flush); 1023int radeon_ib_pool_init(struct radeon_device *rdev); 1024void radeon_ib_pool_fini(struct radeon_device *rdev); 1025int radeon_ib_ring_tests(struct radeon_device *rdev); 1026/* Ring access between begin & end cannot sleep */ 1027bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 1028 struct radeon_ring *ring); 1029void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 1030int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1031int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 1032void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1033 bool hdp_flush); 1034void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp, 1035 bool hdp_flush); 1036void radeon_ring_undo(struct radeon_ring *ring); 1037void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 1038int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 1039void radeon_ring_lockup_update(struct radeon_device *rdev, 1040 struct radeon_ring *ring); 1041bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 1042unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 1043 uint32_t **data); 1044int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 1045 unsigned size, uint32_t *data); 1046int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 1047 unsigned rptr_offs, u32 nop); 1048void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 1049 1050 1051/* r600 async dma */ 1052void r600_dma_stop(struct radeon_device *rdev); 1053int r600_dma_resume(struct radeon_device *rdev); 1054void r600_dma_fini(struct radeon_device *rdev); 1055 1056void cayman_dma_stop(struct radeon_device *rdev); 1057int cayman_dma_resume(struct radeon_device *rdev); 1058void cayman_dma_fini(struct radeon_device *rdev); 1059 1060/* 1061 * CS. 1062 */ 1063struct radeon_cs_chunk { 1064 uint32_t length_dw; 1065 uint32_t *kdata; 1066 void __user *user_ptr; 1067}; 1068 1069struct radeon_cs_parser { 1070 struct device *dev; 1071 struct radeon_device *rdev; 1072 struct drm_file *filp; 1073 /* chunks */ 1074 unsigned nchunks; 1075 struct radeon_cs_chunk *chunks; 1076 uint64_t *chunks_array; 1077 /* IB */ 1078 unsigned idx; 1079 /* relocations */ 1080 unsigned nrelocs; 1081 struct radeon_bo_list *relocs; 1082 struct radeon_bo_list *vm_bos; 1083 struct list_head validated; 1084 unsigned dma_reloc_idx; 1085 /* indices of various chunks */ 1086 struct radeon_cs_chunk *chunk_ib; 1087 struct radeon_cs_chunk *chunk_relocs; 1088 struct radeon_cs_chunk *chunk_flags; 1089 struct radeon_cs_chunk *chunk_const_ib; 1090 struct radeon_ib ib; 1091 struct radeon_ib const_ib; 1092 void *track; 1093 unsigned family; 1094 int parser_error; 1095 u32 cs_flags; 1096 u32 ring; 1097 s32 priority; 1098 struct ww_acquire_ctx ticket; 1099}; 1100 1101static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1102{ 1103 struct radeon_cs_chunk *ibc = p->chunk_ib; 1104 1105 if (ibc->kdata) 1106 return ibc->kdata[idx]; 1107 return p->ib.ptr[idx]; 1108} 1109 1110 1111struct radeon_cs_packet { 1112 unsigned idx; 1113 unsigned type; 1114 unsigned reg; 1115 unsigned opcode; 1116 int count; 1117 unsigned one_reg_wr; 1118}; 1119 1120typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 1121 struct radeon_cs_packet *pkt, 1122 unsigned idx, unsigned reg); 1123typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 1124 struct radeon_cs_packet *pkt); 1125 1126 1127/* 1128 * AGP 1129 */ 1130int radeon_agp_init(struct radeon_device *rdev); 1131void radeon_agp_resume(struct radeon_device *rdev); 1132void radeon_agp_suspend(struct radeon_device *rdev); 1133void radeon_agp_fini(struct radeon_device *rdev); 1134 1135 1136/* 1137 * Writeback 1138 */ 1139struct radeon_wb { 1140 struct radeon_bo *wb_obj; 1141 volatile uint32_t *wb; 1142 uint64_t gpu_addr; 1143 bool enabled; 1144 bool use_event; 1145}; 1146 1147#define RADEON_WB_SCRATCH_OFFSET 0 1148#define RADEON_WB_RING0_NEXT_RPTR 256 1149#define RADEON_WB_CP_RPTR_OFFSET 1024 1150#define RADEON_WB_CP1_RPTR_OFFSET 1280 1151#define RADEON_WB_CP2_RPTR_OFFSET 1536 1152#define R600_WB_DMA_RPTR_OFFSET 1792 1153#define R600_WB_IH_WPTR_OFFSET 2048 1154#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 1155#define R600_WB_EVENT_OFFSET 3072 1156#define CIK_WB_CP1_WPTR_OFFSET 3328 1157#define CIK_WB_CP2_WPTR_OFFSET 3584 1158#define R600_WB_DMA_RING_TEST_OFFSET 3588 1159#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592 1160 1161/** 1162 * struct radeon_pm - power management datas 1163 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 1164 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 1165 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 1166 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 1167 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 1168 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 1169 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 1170 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 1171 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 1172 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 1173 * @needed_bandwidth: current bandwidth needs 1174 * 1175 * It keeps track of various data needed to take powermanagement decision. 1176 * Bandwidth need is used to determine minimun clock of the GPU and memory. 1177 * Equation between gpu/memory clock and available bandwidth is hw dependent 1178 * (type of memory, bus size, efficiency, ...) 1179 */ 1180 1181enum radeon_pm_method { 1182 PM_METHOD_PROFILE, 1183 PM_METHOD_DYNPM, 1184 PM_METHOD_DPM, 1185}; 1186 1187enum radeon_dynpm_state { 1188 DYNPM_STATE_DISABLED, 1189 DYNPM_STATE_MINIMUM, 1190 DYNPM_STATE_PAUSED, 1191 DYNPM_STATE_ACTIVE, 1192 DYNPM_STATE_SUSPENDED, 1193}; 1194enum radeon_dynpm_action { 1195 DYNPM_ACTION_NONE, 1196 DYNPM_ACTION_MINIMUM, 1197 DYNPM_ACTION_DOWNCLOCK, 1198 DYNPM_ACTION_UPCLOCK, 1199 DYNPM_ACTION_DEFAULT 1200}; 1201 1202enum radeon_voltage_type { 1203 VOLTAGE_NONE = 0, 1204 VOLTAGE_GPIO, 1205 VOLTAGE_VDDC, 1206 VOLTAGE_SW 1207}; 1208 1209enum radeon_pm_state_type { 1210 /* not used for dpm */ 1211 POWER_STATE_TYPE_DEFAULT, 1212 POWER_STATE_TYPE_POWERSAVE, 1213 /* user selectable states */ 1214 POWER_STATE_TYPE_BATTERY, 1215 POWER_STATE_TYPE_BALANCED, 1216 POWER_STATE_TYPE_PERFORMANCE, 1217 /* internal states */ 1218 POWER_STATE_TYPE_INTERNAL_UVD, 1219 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1220 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1221 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1222 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1223 POWER_STATE_TYPE_INTERNAL_BOOT, 1224 POWER_STATE_TYPE_INTERNAL_THERMAL, 1225 POWER_STATE_TYPE_INTERNAL_ACPI, 1226 POWER_STATE_TYPE_INTERNAL_ULV, 1227 POWER_STATE_TYPE_INTERNAL_3DPERF, 1228}; 1229 1230enum radeon_pm_profile_type { 1231 PM_PROFILE_DEFAULT, 1232 PM_PROFILE_AUTO, 1233 PM_PROFILE_LOW, 1234 PM_PROFILE_MID, 1235 PM_PROFILE_HIGH, 1236}; 1237 1238#define PM_PROFILE_DEFAULT_IDX 0 1239#define PM_PROFILE_LOW_SH_IDX 1 1240#define PM_PROFILE_MID_SH_IDX 2 1241#define PM_PROFILE_HIGH_SH_IDX 3 1242#define PM_PROFILE_LOW_MH_IDX 4 1243#define PM_PROFILE_MID_MH_IDX 5 1244#define PM_PROFILE_HIGH_MH_IDX 6 1245#define PM_PROFILE_MAX 7 1246 1247struct radeon_pm_profile { 1248 int dpms_off_ps_idx; 1249 int dpms_on_ps_idx; 1250 int dpms_off_cm_idx; 1251 int dpms_on_cm_idx; 1252}; 1253 1254enum radeon_int_thermal_type { 1255 THERMAL_TYPE_NONE, 1256 THERMAL_TYPE_EXTERNAL, 1257 THERMAL_TYPE_EXTERNAL_GPIO, 1258 THERMAL_TYPE_RV6XX, 1259 THERMAL_TYPE_RV770, 1260 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1261 THERMAL_TYPE_EVERGREEN, 1262 THERMAL_TYPE_SUMO, 1263 THERMAL_TYPE_NI, 1264 THERMAL_TYPE_SI, 1265 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1266 THERMAL_TYPE_CI, 1267 THERMAL_TYPE_KV, 1268}; 1269 1270struct radeon_voltage { 1271 enum radeon_voltage_type type; 1272 /* gpio voltage */ 1273 struct radeon_gpio_rec gpio; 1274 u32 delay; /* delay in usec from voltage drop to sclk change */ 1275 bool active_high; /* voltage drop is active when bit is high */ 1276 /* VDDC voltage */ 1277 u8 vddc_id; /* index into vddc voltage table */ 1278 u8 vddci_id; /* index into vddci voltage table */ 1279 bool vddci_enabled; 1280 /* r6xx+ sw */ 1281 u16 voltage; 1282 /* evergreen+ vddci */ 1283 u16 vddci; 1284}; 1285 1286/* clock mode flags */ 1287#define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1288 1289struct radeon_pm_clock_info { 1290 /* memory clock */ 1291 u32 mclk; 1292 /* engine clock */ 1293 u32 sclk; 1294 /* voltage info */ 1295 struct radeon_voltage voltage; 1296 /* standardized clock flags */ 1297 u32 flags; 1298}; 1299 1300/* state flags */ 1301#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1302 1303struct radeon_power_state { 1304 enum radeon_pm_state_type type; 1305 struct radeon_pm_clock_info *clock_info; 1306 /* number of valid clock modes in this power state */ 1307 int num_clock_modes; 1308 struct radeon_pm_clock_info *default_clock_mode; 1309 /* standardized state flags */ 1310 u32 flags; 1311 u32 misc; /* vbios specific flags */ 1312 u32 misc2; /* vbios specific flags */ 1313 int pcie_lanes; /* pcie lanes */ 1314}; 1315 1316/* 1317 * Some modes are overclocked by very low value, accept them 1318 */ 1319#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1320 1321enum radeon_dpm_auto_throttle_src { 1322 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, 1323 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1324}; 1325 1326enum radeon_dpm_event_src { 1327 RADEON_DPM_EVENT_SRC_ANALOG = 0, 1328 RADEON_DPM_EVENT_SRC_EXTERNAL = 1, 1329 RADEON_DPM_EVENT_SRC_DIGITAL = 2, 1330 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1331 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1332}; 1333 1334#define RADEON_MAX_VCE_LEVELS 6 1335 1336enum radeon_vce_level { 1337 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1338 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1339 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1340 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1341 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1342 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1343}; 1344 1345struct radeon_ps { 1346 u32 caps; /* vbios flags */ 1347 u32 class; /* vbios flags */ 1348 u32 class2; /* vbios flags */ 1349 /* UVD clocks */ 1350 u32 vclk; 1351 u32 dclk; 1352 /* VCE clocks */ 1353 u32 evclk; 1354 u32 ecclk; 1355 bool vce_active; 1356 enum radeon_vce_level vce_level; 1357 /* asic priv */ 1358 void *ps_priv; 1359}; 1360 1361struct radeon_dpm_thermal { 1362 /* thermal interrupt work */ 1363 struct work_struct work; 1364 /* low temperature threshold */ 1365 int min_temp; 1366 /* high temperature threshold */ 1367 int max_temp; 1368 /* was interrupt low to high or high to low */ 1369 bool high_to_low; 1370}; 1371 1372enum radeon_clk_action 1373{ 1374 RADEON_SCLK_UP = 1, 1375 RADEON_SCLK_DOWN 1376}; 1377 1378struct radeon_blacklist_clocks 1379{ 1380 u32 sclk; 1381 u32 mclk; 1382 enum radeon_clk_action action; 1383}; 1384 1385struct radeon_clock_and_voltage_limits { 1386 u32 sclk; 1387 u32 mclk; 1388 u16 vddc; 1389 u16 vddci; 1390}; 1391 1392struct radeon_clock_array { 1393 u32 count; 1394 u32 *values; 1395}; 1396 1397struct radeon_clock_voltage_dependency_entry { 1398 u32 clk; 1399 u16 v; 1400}; 1401 1402struct radeon_clock_voltage_dependency_table { 1403 u32 count; 1404 struct radeon_clock_voltage_dependency_entry *entries; 1405}; 1406 1407union radeon_cac_leakage_entry { 1408 struct { 1409 u16 vddc; 1410 u32 leakage; 1411 }; 1412 struct { 1413 u16 vddc1; 1414 u16 vddc2; 1415 u16 vddc3; 1416 }; 1417}; 1418 1419struct radeon_cac_leakage_table { 1420 u32 count; 1421 union radeon_cac_leakage_entry *entries; 1422}; 1423 1424struct radeon_phase_shedding_limits_entry { 1425 u16 voltage; 1426 u32 sclk; 1427 u32 mclk; 1428}; 1429 1430struct radeon_phase_shedding_limits_table { 1431 u32 count; 1432 struct radeon_phase_shedding_limits_entry *entries; 1433}; 1434 1435struct radeon_uvd_clock_voltage_dependency_entry { 1436 u32 vclk; 1437 u32 dclk; 1438 u16 v; 1439}; 1440 1441struct radeon_uvd_clock_voltage_dependency_table { 1442 u8 count; 1443 struct radeon_uvd_clock_voltage_dependency_entry *entries; 1444}; 1445 1446struct radeon_vce_clock_voltage_dependency_entry { 1447 u32 ecclk; 1448 u32 evclk; 1449 u16 v; 1450}; 1451 1452struct radeon_vce_clock_voltage_dependency_table { 1453 u8 count; 1454 struct radeon_vce_clock_voltage_dependency_entry *entries; 1455}; 1456 1457struct radeon_ppm_table { 1458 u8 ppm_design; 1459 u16 cpu_core_number; 1460 u32 platform_tdp; 1461 u32 small_ac_platform_tdp; 1462 u32 platform_tdc; 1463 u32 small_ac_platform_tdc; 1464 u32 apu_tdp; 1465 u32 dgpu_tdp; 1466 u32 dgpu_ulv_power; 1467 u32 tj_max; 1468}; 1469 1470struct radeon_cac_tdp_table { 1471 u16 tdp; 1472 u16 configurable_tdp; 1473 u16 tdc; 1474 u16 battery_power_limit; 1475 u16 small_power_limit; 1476 u16 low_cac_leakage; 1477 u16 high_cac_leakage; 1478 u16 maximum_power_delivery_limit; 1479}; 1480 1481struct radeon_dpm_dynamic_state { 1482 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk; 1483 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk; 1484 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk; 1485 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1486 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1487 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1488 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1489 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1490 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1491 struct radeon_clock_array valid_sclk_values; 1492 struct radeon_clock_array valid_mclk_values; 1493 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc; 1494 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac; 1495 u32 mclk_sclk_ratio; 1496 u32 sclk_mclk_delta; 1497 u16 vddc_vddci_delta; 1498 u16 min_vddc_for_pcie_gen2; 1499 struct radeon_cac_leakage_table cac_leakage_table; 1500 struct radeon_phase_shedding_limits_table phase_shedding_limits_table; 1501 struct radeon_ppm_table *ppm_table; 1502 struct radeon_cac_tdp_table *cac_tdp_table; 1503}; 1504 1505struct radeon_dpm_fan { 1506 u16 t_min; 1507 u16 t_med; 1508 u16 t_high; 1509 u16 pwm_min; 1510 u16 pwm_med; 1511 u16 pwm_high; 1512 u8 t_hyst; 1513 u32 cycle_delay; 1514 u16 t_max; 1515 u8 control_mode; 1516 u16 default_max_fan_pwm; 1517 u16 default_fan_output_sensitivity; 1518 u16 fan_output_sensitivity; 1519 bool ucode_fan_control; 1520}; 1521 1522enum radeon_pcie_gen { 1523 RADEON_PCIE_GEN1 = 0, 1524 RADEON_PCIE_GEN2 = 1, 1525 RADEON_PCIE_GEN3 = 2, 1526 RADEON_PCIE_GEN_INVALID = 0xffff 1527}; 1528 1529enum radeon_dpm_forced_level { 1530 RADEON_DPM_FORCED_LEVEL_AUTO = 0, 1531 RADEON_DPM_FORCED_LEVEL_LOW = 1, 1532 RADEON_DPM_FORCED_LEVEL_HIGH = 2, 1533}; 1534 1535struct radeon_vce_state { 1536 /* vce clocks */ 1537 u32 evclk; 1538 u32 ecclk; 1539 /* gpu clocks */ 1540 u32 sclk; 1541 u32 mclk; 1542 u8 clk_idx; 1543 u8 pstate; 1544}; 1545 1546struct radeon_dpm { 1547 struct radeon_ps *ps; 1548 /* number of valid power states */ 1549 int num_ps; 1550 /* current power state that is active */ 1551 struct radeon_ps *current_ps; 1552 /* requested power state */ 1553 struct radeon_ps *requested_ps; 1554 /* boot up power state */ 1555 struct radeon_ps *boot_ps; 1556 /* default uvd power state */ 1557 struct radeon_ps *uvd_ps; 1558 /* vce requirements */ 1559 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS]; 1560 enum radeon_vce_level vce_level; 1561 enum radeon_pm_state_type state; 1562 enum radeon_pm_state_type user_state; 1563 u32 platform_caps; 1564 u32 voltage_response_time; 1565 u32 backbias_response_time; 1566 void *priv; 1567 u32 new_active_crtcs; 1568 int new_active_crtc_count; 1569 u32 current_active_crtcs; 1570 int current_active_crtc_count; 1571 bool single_display; 1572 struct radeon_dpm_dynamic_state dyn_state; 1573 struct radeon_dpm_fan fan; 1574 u32 tdp_limit; 1575 u32 near_tdp_limit; 1576 u32 near_tdp_limit_adjusted; 1577 u32 sq_ramping_threshold; 1578 u32 cac_leakage; 1579 u16 tdp_od_limit; 1580 u32 tdp_adjustment; 1581 u16 load_line_slope; 1582 bool power_control; 1583 bool ac_power; 1584 /* special states active */ 1585 bool thermal_active; 1586 bool uvd_active; 1587 bool vce_active; 1588 /* thermal handling */ 1589 struct radeon_dpm_thermal thermal; 1590 /* forced levels */ 1591 enum radeon_dpm_forced_level forced_level; 1592 /* track UVD streams */ 1593 unsigned sd; 1594 unsigned hd; 1595}; 1596 1597void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable); 1598void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable); 1599 1600struct radeon_pm { 1601 struct mutex mutex; 1602 /* write locked while reprogramming mclk */ 1603 struct rw_semaphore mclk_lock; 1604 u32 active_crtcs; 1605 int active_crtc_count; 1606 int req_vblank; 1607 bool vblank_sync; 1608 fixed20_12 max_bandwidth; 1609 fixed20_12 igp_sideport_mclk; 1610 fixed20_12 igp_system_mclk; 1611 fixed20_12 igp_ht_link_clk; 1612 fixed20_12 igp_ht_link_width; 1613 fixed20_12 k8_bandwidth; 1614 fixed20_12 sideport_bandwidth; 1615 fixed20_12 ht_bandwidth; 1616 fixed20_12 core_bandwidth; 1617 fixed20_12 sclk; 1618 fixed20_12 mclk; 1619 fixed20_12 needed_bandwidth; 1620 struct radeon_power_state *power_state; 1621 /* number of valid power states */ 1622 int num_power_states; 1623 int current_power_state_index; 1624 int current_clock_mode_index; 1625 int requested_power_state_index; 1626 int requested_clock_mode_index; 1627 int default_power_state_index; 1628 u32 current_sclk; 1629 u32 current_mclk; 1630 u16 current_vddc; 1631 u16 current_vddci; 1632 u32 default_sclk; 1633 u32 default_mclk; 1634 u16 default_vddc; 1635 u16 default_vddci; 1636 struct radeon_i2c_chan *i2c_bus; 1637 /* selected pm method */ 1638 enum radeon_pm_method pm_method; 1639 /* dynpm power management */ 1640 struct delayed_work dynpm_idle_work; 1641 enum radeon_dynpm_state dynpm_state; 1642 enum radeon_dynpm_action dynpm_planned_action; 1643 unsigned long dynpm_action_timeout; 1644 bool dynpm_can_upclock; 1645 bool dynpm_can_downclock; 1646 /* profile-based power management */ 1647 enum radeon_pm_profile_type profile; 1648 int profile_index; 1649 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1650 /* internal thermal controller on rv6xx+ */ 1651 enum radeon_int_thermal_type int_thermal_type; 1652 struct device *int_hwmon_dev; 1653 /* fan control parameters */ 1654 bool no_fan; 1655 u8 fan_pulses_per_revolution; 1656 u8 fan_min_rpm; 1657 u8 fan_max_rpm; 1658 /* dpm */ 1659 bool dpm_enabled; 1660 bool sysfs_initialized; 1661 struct radeon_dpm dpm; 1662}; 1663 1664int radeon_pm_get_type_index(struct radeon_device *rdev, 1665 enum radeon_pm_state_type ps_type, 1666 int instance); 1667/* 1668 * UVD 1669 */ 1670#define RADEON_MAX_UVD_HANDLES 10 1671#define RADEON_UVD_STACK_SIZE (1024*1024) 1672#define RADEON_UVD_HEAP_SIZE (1024*1024) 1673 1674struct radeon_uvd { 1675 struct radeon_bo *vcpu_bo; 1676 void *cpu_addr; 1677 uint64_t gpu_addr; 1678 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1679 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1680 unsigned img_size[RADEON_MAX_UVD_HANDLES]; 1681 struct delayed_work idle_work; 1682}; 1683 1684int radeon_uvd_init(struct radeon_device *rdev); 1685void radeon_uvd_fini(struct radeon_device *rdev); 1686int radeon_uvd_suspend(struct radeon_device *rdev); 1687int radeon_uvd_resume(struct radeon_device *rdev); 1688int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, 1689 uint32_t handle, struct radeon_fence **fence); 1690int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, 1691 uint32_t handle, struct radeon_fence **fence); 1692void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, 1693 uint32_t allowed_domains); 1694void radeon_uvd_free_handles(struct radeon_device *rdev, 1695 struct drm_file *filp); 1696int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1697void radeon_uvd_note_usage(struct radeon_device *rdev); 1698int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, 1699 unsigned vclk, unsigned dclk, 1700 unsigned vco_min, unsigned vco_max, 1701 unsigned fb_factor, unsigned fb_mask, 1702 unsigned pd_min, unsigned pd_max, 1703 unsigned pd_even, 1704 unsigned *optimal_fb_div, 1705 unsigned *optimal_vclk_div, 1706 unsigned *optimal_dclk_div); 1707int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, 1708 unsigned cg_upll_func_cntl); 1709 1710/* 1711 * VCE 1712 */ 1713#define RADEON_MAX_VCE_HANDLES 16 1714#define RADEON_VCE_STACK_SIZE (1024*1024) 1715#define RADEON_VCE_HEAP_SIZE (4*1024*1024) 1716 1717struct radeon_vce { 1718 struct radeon_bo *vcpu_bo; 1719 uint64_t gpu_addr; 1720 unsigned fw_version; 1721 unsigned fb_version; 1722 atomic_t handles[RADEON_MAX_VCE_HANDLES]; 1723 struct drm_file *filp[RADEON_MAX_VCE_HANDLES]; 1724 unsigned img_size[RADEON_MAX_VCE_HANDLES]; 1725 struct delayed_work idle_work; 1726}; 1727 1728int radeon_vce_init(struct radeon_device *rdev); 1729void radeon_vce_fini(struct radeon_device *rdev); 1730int radeon_vce_suspend(struct radeon_device *rdev); 1731int radeon_vce_resume(struct radeon_device *rdev); 1732int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring, 1733 uint32_t handle, struct radeon_fence **fence); 1734int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring, 1735 uint32_t handle, struct radeon_fence **fence); 1736void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp); 1737void radeon_vce_note_usage(struct radeon_device *rdev); 1738int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size); 1739int radeon_vce_cs_parse(struct radeon_cs_parser *p); 1740bool radeon_vce_semaphore_emit(struct radeon_device *rdev, 1741 struct radeon_ring *ring, 1742 struct radeon_semaphore *semaphore, 1743 bool emit_wait); 1744void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 1745void radeon_vce_fence_emit(struct radeon_device *rdev, 1746 struct radeon_fence *fence); 1747int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring); 1748int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 1749 1750struct r600_audio_pin { 1751 int channels; 1752 int rate; 1753 int bits_per_sample; 1754 u8 status_bits; 1755 u8 category_code; 1756 u32 offset; 1757 bool connected; 1758 u32 id; 1759}; 1760 1761struct r600_audio { 1762 bool enabled; 1763 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS]; 1764 int num_pins; 1765 struct radeon_audio_funcs *hdmi_funcs; 1766 struct radeon_audio_funcs *dp_funcs; 1767 struct radeon_audio_basic_funcs *funcs; 1768}; 1769 1770/* 1771 * Benchmarking 1772 */ 1773void radeon_benchmark(struct radeon_device *rdev, int test_number); 1774 1775 1776/* 1777 * Testing 1778 */ 1779void radeon_test_moves(struct radeon_device *rdev); 1780void radeon_test_ring_sync(struct radeon_device *rdev, 1781 struct radeon_ring *cpA, 1782 struct radeon_ring *cpB); 1783void radeon_test_syncing(struct radeon_device *rdev); 1784 1785/* 1786 * MMU Notifier 1787 */ 1788#if defined(CONFIG_MMU_NOTIFIER) 1789int radeon_mn_register(struct radeon_bo *bo, unsigned long addr); 1790void radeon_mn_unregister(struct radeon_bo *bo); 1791#else 1792static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr) 1793{ 1794 return -ENODEV; 1795} 1796static inline void radeon_mn_unregister(struct radeon_bo *bo) {} 1797#endif 1798 1799/* 1800 * Debugfs 1801 */ 1802struct radeon_debugfs { 1803 struct drm_info_list *files; 1804 unsigned num_files; 1805}; 1806 1807int radeon_debugfs_add_files(struct radeon_device *rdev, 1808 struct drm_info_list *files, 1809 unsigned nfiles); 1810int radeon_debugfs_fence_init(struct radeon_device *rdev); 1811 1812/* 1813 * ASIC ring specific functions. 1814 */ 1815struct radeon_asic_ring { 1816 /* ring read/write ptr handling */ 1817 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1818 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1819 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); 1820 1821 /* validating and patching of IBs */ 1822 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1823 int (*cs_parse)(struct radeon_cs_parser *p); 1824 1825 /* command emmit functions */ 1826 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1827 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1828 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1829 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1830 struct radeon_semaphore *semaphore, bool emit_wait); 1831 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring, 1832 unsigned vm_id, uint64_t pd_addr); 1833 1834 /* testing functions */ 1835 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1836 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1837 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1838 1839 /* deprecated */ 1840 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1841}; 1842 1843/* 1844 * ASIC specific functions. 1845 */ 1846struct radeon_asic { 1847 int (*init)(struct radeon_device *rdev); 1848 void (*fini)(struct radeon_device *rdev); 1849 int (*resume)(struct radeon_device *rdev); 1850 int (*suspend)(struct radeon_device *rdev); 1851 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1852 int (*asic_reset)(struct radeon_device *rdev); 1853 /* Flush the HDP cache via MMIO */ 1854 void (*mmio_hdp_flush)(struct radeon_device *rdev); 1855 /* check if 3D engine is idle */ 1856 bool (*gui_idle)(struct radeon_device *rdev); 1857 /* wait for mc_idle */ 1858 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1859 /* get the reference clock */ 1860 u32 (*get_xclk)(struct radeon_device *rdev); 1861 /* get the gpu clock counter */ 1862 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev); 1863 /* get register for info ioctl */ 1864 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val); 1865 /* gart */ 1866 struct { 1867 void (*tlb_flush)(struct radeon_device *rdev); 1868 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags); 1869 void (*set_page)(struct radeon_device *rdev, unsigned i, 1870 uint64_t entry); 1871 } gart; 1872 struct { 1873 int (*init)(struct radeon_device *rdev); 1874 void (*fini)(struct radeon_device *rdev); 1875 void (*copy_pages)(struct radeon_device *rdev, 1876 struct radeon_ib *ib, 1877 uint64_t pe, uint64_t src, 1878 unsigned count); 1879 void (*write_pages)(struct radeon_device *rdev, 1880 struct radeon_ib *ib, 1881 uint64_t pe, 1882 uint64_t addr, unsigned count, 1883 uint32_t incr, uint32_t flags); 1884 void (*set_pages)(struct radeon_device *rdev, 1885 struct radeon_ib *ib, 1886 uint64_t pe, 1887 uint64_t addr, unsigned count, 1888 uint32_t incr, uint32_t flags); 1889 void (*pad_ib)(struct radeon_ib *ib); 1890 } vm; 1891 /* ring specific callbacks */ 1892 struct radeon_asic_ring *ring[RADEON_NUM_RINGS]; 1893 /* irqs */ 1894 struct { 1895 int (*set)(struct radeon_device *rdev); 1896 int (*process)(struct radeon_device *rdev); 1897 } irq; 1898 /* displays */ 1899 struct { 1900 /* display watermarks */ 1901 void (*bandwidth_update)(struct radeon_device *rdev); 1902 /* get frame count */ 1903 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1904 /* wait for vblank */ 1905 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1906 /* set backlight level */ 1907 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1908 /* get backlight level */ 1909 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1910 /* audio callbacks */ 1911 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable); 1912 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode); 1913 } display; 1914 /* copy functions for bo handling */ 1915 struct { 1916 struct radeon_fence *(*blit)(struct radeon_device *rdev, 1917 uint64_t src_offset, 1918 uint64_t dst_offset, 1919 unsigned num_gpu_pages, 1920 struct reservation_object *resv); 1921 u32 blit_ring_index; 1922 struct radeon_fence *(*dma)(struct radeon_device *rdev, 1923 uint64_t src_offset, 1924 uint64_t dst_offset, 1925 unsigned num_gpu_pages, 1926 struct reservation_object *resv); 1927 u32 dma_ring_index; 1928 /* method used for bo copy */ 1929 struct radeon_fence *(*copy)(struct radeon_device *rdev, 1930 uint64_t src_offset, 1931 uint64_t dst_offset, 1932 unsigned num_gpu_pages, 1933 struct reservation_object *resv); 1934 /* ring used for bo copies */ 1935 u32 copy_ring_index; 1936 } copy; 1937 /* surfaces */ 1938 struct { 1939 int (*set_reg)(struct radeon_device *rdev, int reg, 1940 uint32_t tiling_flags, uint32_t pitch, 1941 uint32_t offset, uint32_t obj_size); 1942 void (*clear_reg)(struct radeon_device *rdev, int reg); 1943 } surface; 1944 /* hotplug detect */ 1945 struct { 1946 void (*init)(struct radeon_device *rdev); 1947 void (*fini)(struct radeon_device *rdev); 1948 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1949 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1950 } hpd; 1951 /* static power management */ 1952 struct { 1953 void (*misc)(struct radeon_device *rdev); 1954 void (*prepare)(struct radeon_device *rdev); 1955 void (*finish)(struct radeon_device *rdev); 1956 void (*init_profile)(struct radeon_device *rdev); 1957 void (*get_dynpm_state)(struct radeon_device *rdev); 1958 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1959 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1960 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1961 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1962 int (*get_pcie_lanes)(struct radeon_device *rdev); 1963 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1964 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1965 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk); 1966 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk); 1967 int (*get_temperature)(struct radeon_device *rdev); 1968 } pm; 1969 /* dynamic power management */ 1970 struct { 1971 int (*init)(struct radeon_device *rdev); 1972 void (*setup_asic)(struct radeon_device *rdev); 1973 int (*enable)(struct radeon_device *rdev); 1974 int (*late_enable)(struct radeon_device *rdev); 1975 void (*disable)(struct radeon_device *rdev); 1976 int (*pre_set_power_state)(struct radeon_device *rdev); 1977 int (*set_power_state)(struct radeon_device *rdev); 1978 void (*post_set_power_state)(struct radeon_device *rdev); 1979 void (*display_configuration_changed)(struct radeon_device *rdev); 1980 void (*fini)(struct radeon_device *rdev); 1981 u32 (*get_sclk)(struct radeon_device *rdev, bool low); 1982 u32 (*get_mclk)(struct radeon_device *rdev, bool low); 1983 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps); 1984 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m); 1985 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level); 1986 bool (*vblank_too_short)(struct radeon_device *rdev); 1987 void (*powergate_uvd)(struct radeon_device *rdev, bool gate); 1988 void (*enable_bapm)(struct radeon_device *rdev, bool enable); 1989 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode); 1990 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev); 1991 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed); 1992 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed); 1993 u32 (*get_current_sclk)(struct radeon_device *rdev); 1994 u32 (*get_current_mclk)(struct radeon_device *rdev); 1995 } dpm; 1996 /* pageflipping */ 1997 struct { 1998 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1999 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc); 2000 } pflip; 2001}; 2002 2003/* 2004 * Asic structures 2005 */ 2006struct r100_asic { 2007 const unsigned *reg_safe_bm; 2008 unsigned reg_safe_bm_size; 2009 u32 hdp_cntl; 2010}; 2011 2012struct r300_asic { 2013 const unsigned *reg_safe_bm; 2014 unsigned reg_safe_bm_size; 2015 u32 resync_scratch; 2016 u32 hdp_cntl; 2017}; 2018 2019struct r600_asic { 2020 unsigned max_pipes; 2021 unsigned max_tile_pipes; 2022 unsigned max_simds; 2023 unsigned max_backends; 2024 unsigned max_gprs; 2025 unsigned max_threads; 2026 unsigned max_stack_entries; 2027 unsigned max_hw_contexts; 2028 unsigned max_gs_threads; 2029 unsigned sx_max_export_size; 2030 unsigned sx_max_export_pos_size; 2031 unsigned sx_max_export_smx_size; 2032 unsigned sq_num_cf_insts; 2033 unsigned tiling_nbanks; 2034 unsigned tiling_npipes; 2035 unsigned tiling_group_size; 2036 unsigned tile_config; 2037 unsigned backend_map; 2038 unsigned active_simds; 2039}; 2040 2041struct rv770_asic { 2042 unsigned max_pipes; 2043 unsigned max_tile_pipes; 2044 unsigned max_simds; 2045 unsigned max_backends; 2046 unsigned max_gprs; 2047 unsigned max_threads; 2048 unsigned max_stack_entries; 2049 unsigned max_hw_contexts; 2050 unsigned max_gs_threads; 2051 unsigned sx_max_export_size; 2052 unsigned sx_max_export_pos_size; 2053 unsigned sx_max_export_smx_size; 2054 unsigned sq_num_cf_insts; 2055 unsigned sx_num_of_sets; 2056 unsigned sc_prim_fifo_size; 2057 unsigned sc_hiz_tile_fifo_size; 2058 unsigned sc_earlyz_tile_fifo_fize; 2059 unsigned tiling_nbanks; 2060 unsigned tiling_npipes; 2061 unsigned tiling_group_size; 2062 unsigned tile_config; 2063 unsigned backend_map; 2064 unsigned active_simds; 2065}; 2066 2067struct evergreen_asic { 2068 unsigned num_ses; 2069 unsigned max_pipes; 2070 unsigned max_tile_pipes; 2071 unsigned max_simds; 2072 unsigned max_backends; 2073 unsigned max_gprs; 2074 unsigned max_threads; 2075 unsigned max_stack_entries; 2076 unsigned max_hw_contexts; 2077 unsigned max_gs_threads; 2078 unsigned sx_max_export_size; 2079 unsigned sx_max_export_pos_size; 2080 unsigned sx_max_export_smx_size; 2081 unsigned sq_num_cf_insts; 2082 unsigned sx_num_of_sets; 2083 unsigned sc_prim_fifo_size; 2084 unsigned sc_hiz_tile_fifo_size; 2085 unsigned sc_earlyz_tile_fifo_size; 2086 unsigned tiling_nbanks; 2087 unsigned tiling_npipes; 2088 unsigned tiling_group_size; 2089 unsigned tile_config; 2090 unsigned backend_map; 2091 unsigned active_simds; 2092}; 2093 2094struct cayman_asic { 2095 unsigned max_shader_engines; 2096 unsigned max_pipes_per_simd; 2097 unsigned max_tile_pipes; 2098 unsigned max_simds_per_se; 2099 unsigned max_backends_per_se; 2100 unsigned max_texture_channel_caches; 2101 unsigned max_gprs; 2102 unsigned max_threads; 2103 unsigned max_gs_threads; 2104 unsigned max_stack_entries; 2105 unsigned sx_num_of_sets; 2106 unsigned sx_max_export_size; 2107 unsigned sx_max_export_pos_size; 2108 unsigned sx_max_export_smx_size; 2109 unsigned max_hw_contexts; 2110 unsigned sq_num_cf_insts; 2111 unsigned sc_prim_fifo_size; 2112 unsigned sc_hiz_tile_fifo_size; 2113 unsigned sc_earlyz_tile_fifo_size; 2114 2115 unsigned num_shader_engines; 2116 unsigned num_shader_pipes_per_simd; 2117 unsigned num_tile_pipes; 2118 unsigned num_simds_per_se; 2119 unsigned num_backends_per_se; 2120 unsigned backend_disable_mask_per_asic; 2121 unsigned backend_map; 2122 unsigned num_texture_channel_caches; 2123 unsigned mem_max_burst_length_bytes; 2124 unsigned mem_row_size_in_kb; 2125 unsigned shader_engine_tile_size; 2126 unsigned num_gpus; 2127 unsigned multi_gpu_tile_size; 2128 2129 unsigned tile_config; 2130 unsigned active_simds; 2131}; 2132 2133struct si_asic { 2134 unsigned max_shader_engines; 2135 unsigned max_tile_pipes; 2136 unsigned max_cu_per_sh; 2137 unsigned max_sh_per_se; 2138 unsigned max_backends_per_se; 2139 unsigned max_texture_channel_caches; 2140 unsigned max_gprs; 2141 unsigned max_gs_threads; 2142 unsigned max_hw_contexts; 2143 unsigned sc_prim_fifo_size_frontend; 2144 unsigned sc_prim_fifo_size_backend; 2145 unsigned sc_hiz_tile_fifo_size; 2146 unsigned sc_earlyz_tile_fifo_size; 2147 2148 unsigned num_tile_pipes; 2149 unsigned backend_enable_mask; 2150 unsigned backend_disable_mask_per_asic; 2151 unsigned backend_map; 2152 unsigned num_texture_channel_caches; 2153 unsigned mem_max_burst_length_bytes; 2154 unsigned mem_row_size_in_kb; 2155 unsigned shader_engine_tile_size; 2156 unsigned num_gpus; 2157 unsigned multi_gpu_tile_size; 2158 2159 unsigned tile_config; 2160 uint32_t tile_mode_array[32]; 2161 uint32_t active_cus; 2162}; 2163 2164struct cik_asic { 2165 unsigned max_shader_engines; 2166 unsigned max_tile_pipes; 2167 unsigned max_cu_per_sh; 2168 unsigned max_sh_per_se; 2169 unsigned max_backends_per_se; 2170 unsigned max_texture_channel_caches; 2171 unsigned max_gprs; 2172 unsigned max_gs_threads; 2173 unsigned max_hw_contexts; 2174 unsigned sc_prim_fifo_size_frontend; 2175 unsigned sc_prim_fifo_size_backend; 2176 unsigned sc_hiz_tile_fifo_size; 2177 unsigned sc_earlyz_tile_fifo_size; 2178 2179 unsigned num_tile_pipes; 2180 unsigned backend_enable_mask; 2181 unsigned backend_disable_mask_per_asic; 2182 unsigned backend_map; 2183 unsigned num_texture_channel_caches; 2184 unsigned mem_max_burst_length_bytes; 2185 unsigned mem_row_size_in_kb; 2186 unsigned shader_engine_tile_size; 2187 unsigned num_gpus; 2188 unsigned multi_gpu_tile_size; 2189 2190 unsigned tile_config; 2191 uint32_t tile_mode_array[32]; 2192 uint32_t macrotile_mode_array[16]; 2193 uint32_t active_cus; 2194}; 2195 2196union radeon_asic_config { 2197 struct r300_asic r300; 2198 struct r100_asic r100; 2199 struct r600_asic r600; 2200 struct rv770_asic rv770; 2201 struct evergreen_asic evergreen; 2202 struct cayman_asic cayman; 2203 struct si_asic si; 2204 struct cik_asic cik; 2205}; 2206 2207/* 2208 * asic initizalization from radeon_asic.c 2209 */ 2210void radeon_agp_disable(struct radeon_device *rdev); 2211int radeon_asic_init(struct radeon_device *rdev); 2212 2213 2214/* 2215 * IOCTL. 2216 */ 2217int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 2218 struct drm_file *filp); 2219int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 2220 struct drm_file *filp); 2221int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 2222 struct drm_file *filp); 2223int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 2224 struct drm_file *file_priv); 2225int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 2226 struct drm_file *file_priv); 2227int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2228 struct drm_file *file_priv); 2229int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 2230 struct drm_file *file_priv); 2231int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2232 struct drm_file *filp); 2233int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 2234 struct drm_file *filp); 2235int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 2236 struct drm_file *filp); 2237int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 2238 struct drm_file *filp); 2239int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 2240 struct drm_file *filp); 2241int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 2242 struct drm_file *filp); 2243int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 2244int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 2245 struct drm_file *filp); 2246int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 2247 struct drm_file *filp); 2248 2249/* VRAM scratch page for HDP bug, default vram page */ 2250struct r600_vram_scratch { 2251 struct radeon_bo *robj; 2252 volatile uint32_t *ptr; 2253 u64 gpu_addr; 2254}; 2255 2256/* 2257 * ACPI 2258 */ 2259struct radeon_atif_notification_cfg { 2260 bool enabled; 2261 int command_code; 2262}; 2263 2264struct radeon_atif_notifications { 2265 bool display_switch; 2266 bool expansion_mode_change; 2267 bool thermal_state; 2268 bool forced_power_state; 2269 bool system_power_state; 2270 bool display_conf_change; 2271 bool px_gfx_switch; 2272 bool brightness_change; 2273 bool dgpu_display_event; 2274}; 2275 2276struct radeon_atif_functions { 2277 bool system_params; 2278 bool sbios_requests; 2279 bool select_active_disp; 2280 bool lid_state; 2281 bool get_tv_standard; 2282 bool set_tv_standard; 2283 bool get_panel_expansion_mode; 2284 bool set_panel_expansion_mode; 2285 bool temperature_change; 2286 bool graphics_device_types; 2287}; 2288 2289struct radeon_atif { 2290 struct radeon_atif_notifications notifications; 2291 struct radeon_atif_functions functions; 2292 struct radeon_atif_notification_cfg notification_cfg; 2293 struct radeon_encoder *encoder_for_bl; 2294}; 2295 2296struct radeon_atcs_functions { 2297 bool get_ext_state; 2298 bool pcie_perf_req; 2299 bool pcie_dev_rdy; 2300 bool pcie_bus_width; 2301}; 2302 2303struct radeon_atcs { 2304 struct radeon_atcs_functions functions; 2305}; 2306 2307/* 2308 * Core structure, functions and helpers. 2309 */ 2310typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 2311typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 2312 2313struct radeon_device { 2314 struct device *dev; 2315 struct drm_device *ddev; 2316 struct pci_dev *pdev; 2317 struct rw_semaphore exclusive_lock; 2318 /* ASIC */ 2319 union radeon_asic_config config; 2320 enum radeon_family family; 2321 unsigned long flags; 2322 int usec_timeout; 2323 enum radeon_pll_errata pll_errata; 2324 int num_gb_pipes; 2325 int num_z_pipes; 2326 int disp_priority; 2327 /* BIOS */ 2328 uint8_t *bios; 2329 bool is_atom_bios; 2330 uint16_t bios_header_start; 2331 struct radeon_bo *stollen_vga_memory; 2332 /* Register mmio */ 2333 resource_size_t rmmio_base; 2334 resource_size_t rmmio_size; 2335 /* protects concurrent MM_INDEX/DATA based register access */ 2336 spinlock_t mmio_idx_lock; 2337 /* protects concurrent SMC based register access */ 2338 spinlock_t smc_idx_lock; 2339 /* protects concurrent PLL register access */ 2340 spinlock_t pll_idx_lock; 2341 /* protects concurrent MC register access */ 2342 spinlock_t mc_idx_lock; 2343 /* protects concurrent PCIE register access */ 2344 spinlock_t pcie_idx_lock; 2345 /* protects concurrent PCIE_PORT register access */ 2346 spinlock_t pciep_idx_lock; 2347 /* protects concurrent PIF register access */ 2348 spinlock_t pif_idx_lock; 2349 /* protects concurrent CG register access */ 2350 spinlock_t cg_idx_lock; 2351 /* protects concurrent UVD register access */ 2352 spinlock_t uvd_idx_lock; 2353 /* protects concurrent RCU register access */ 2354 spinlock_t rcu_idx_lock; 2355 /* protects concurrent DIDT register access */ 2356 spinlock_t didt_idx_lock; 2357 /* protects concurrent ENDPOINT (audio) register access */ 2358 spinlock_t end_idx_lock; 2359 void __iomem *rmmio; 2360 radeon_rreg_t mc_rreg; 2361 radeon_wreg_t mc_wreg; 2362 radeon_rreg_t pll_rreg; 2363 radeon_wreg_t pll_wreg; 2364 uint32_t pcie_reg_mask; 2365 radeon_rreg_t pciep_rreg; 2366 radeon_wreg_t pciep_wreg; 2367 /* io port */ 2368 void __iomem *rio_mem; 2369 resource_size_t rio_mem_size; 2370 struct radeon_clock clock; 2371 struct radeon_mc mc; 2372 struct radeon_gart gart; 2373 struct radeon_mode_info mode_info; 2374 struct radeon_scratch scratch; 2375 struct radeon_doorbell doorbell; 2376 struct radeon_mman mman; 2377 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 2378 wait_queue_head_t fence_queue; 2379 unsigned fence_context; 2380 struct mutex ring_lock; 2381 struct radeon_ring ring[RADEON_NUM_RINGS]; 2382 bool ib_pool_ready; 2383 struct radeon_sa_manager ring_tmp_bo; 2384 struct radeon_irq irq; 2385 struct radeon_asic *asic; 2386 struct radeon_gem gem; 2387 struct radeon_pm pm; 2388 struct radeon_uvd uvd; 2389 struct radeon_vce vce; 2390 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 2391 struct radeon_wb wb; 2392 struct radeon_dummy_page dummy_page; 2393 bool shutdown; 2394 bool suspend; 2395 bool need_dma32; 2396 bool accel_working; 2397 bool fastfb_working; /* IGP feature*/ 2398 bool needs_reset, in_reset; 2399 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 2400 const struct firmware *me_fw; /* all family ME firmware */ 2401 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 2402 const struct firmware *rlc_fw; /* r6/700 RLC firmware */ 2403 const struct firmware *mc_fw; /* NI MC firmware */ 2404 const struct firmware *ce_fw; /* SI CE firmware */ 2405 const struct firmware *mec_fw; /* CIK MEC firmware */ 2406 const struct firmware *mec2_fw; /* KV MEC2 firmware */ 2407 const struct firmware *sdma_fw; /* CIK SDMA firmware */ 2408 const struct firmware *smc_fw; /* SMC firmware */ 2409 const struct firmware *uvd_fw; /* UVD firmware */ 2410 const struct firmware *vce_fw; /* VCE firmware */ 2411 bool new_fw; 2412 struct r600_vram_scratch vram_scratch; 2413 int msi_enabled; /* msi enabled */ 2414 struct r600_ih ih; /* r6/700 interrupt ring */ 2415 struct radeon_rlc rlc; 2416 struct radeon_mec mec; 2417 struct work_struct hotplug_work; 2418 struct work_struct dp_work; 2419 struct work_struct audio_work; 2420 int num_crtc; /* number of crtcs */ 2421 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 2422 bool has_uvd; 2423 struct r600_audio audio; /* audio stuff */ 2424 struct notifier_block acpi_nb; 2425 /* only one userspace can use Hyperz features or CMASK at a time */ 2426 struct drm_file *hyperz_filp; 2427 struct drm_file *cmask_filp; 2428 /* i2c buses */ 2429 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 2430 /* debugfs */ 2431 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 2432 unsigned debugfs_count; 2433 /* virtual memory */ 2434 struct radeon_vm_manager vm_manager; 2435 struct mutex gpu_clock_mutex; 2436 /* memory stats */ 2437 atomic64_t vram_usage; 2438 atomic64_t gtt_usage; 2439 atomic64_t num_bytes_moved; 2440 /* ACPI interface */ 2441 struct radeon_atif atif; 2442 struct radeon_atcs atcs; 2443 /* srbm instance registers */ 2444 struct mutex srbm_mutex; 2445 /* GRBM index mutex. Protects concurrents access to GRBM index */ 2446 struct mutex grbm_idx_mutex; 2447 /* clock, powergating flags */ 2448 u32 cg_flags; 2449 u32 pg_flags; 2450 2451 struct dev_pm_domain vga_pm_domain; 2452 bool have_disp_power_ref; 2453 u32 px_quirk_flags; 2454 2455 /* tracking pinned memory */ 2456 u64 vram_pin_size; 2457 u64 gart_pin_size; 2458 2459 /* amdkfd interface */ 2460 struct kfd_dev *kfd; 2461 struct radeon_sa_manager kfd_bo; 2462 2463 struct mutex mn_lock; 2464 DECLARE_HASHTABLE(mn_hash, 7); 2465}; 2466 2467bool radeon_is_px(struct drm_device *dev); 2468int radeon_device_init(struct radeon_device *rdev, 2469 struct drm_device *ddev, 2470 struct pci_dev *pdev, 2471 uint32_t flags); 2472void radeon_device_fini(struct radeon_device *rdev); 2473int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 2474 2475#define RADEON_MIN_MMIO_SIZE 0x10000 2476 2477static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 2478 bool always_indirect) 2479{ 2480 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */ 2481 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2482 return readl(((void __iomem *)rdev->rmmio) + reg); 2483 else { 2484 unsigned long flags; 2485 uint32_t ret; 2486 2487 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2488 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2489 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2490 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2491 2492 return ret; 2493 } 2494} 2495 2496static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 2497 bool always_indirect) 2498{ 2499 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect) 2500 writel(v, ((void __iomem *)rdev->rmmio) + reg); 2501 else { 2502 unsigned long flags; 2503 2504 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 2505 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 2506 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); 2507 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 2508 } 2509} 2510 2511u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 2512void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 2513 2514u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index); 2515void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v); 2516 2517/* 2518 * Cast helper 2519 */ 2520extern const struct fence_ops radeon_fence_ops; 2521 2522static inline struct radeon_fence *to_radeon_fence(struct fence *f) 2523{ 2524 struct radeon_fence *__f = container_of(f, struct radeon_fence, base); 2525 2526 if (__f->base.ops == &radeon_fence_ops) 2527 return __f; 2528 2529 return NULL; 2530} 2531 2532/* 2533 * Registers read & write functions. 2534 */ 2535#define RREG8(reg) readb((rdev->rmmio) + (reg)) 2536#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) 2537#define RREG16(reg) readw((rdev->rmmio) + (reg)) 2538#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) 2539#define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 2540#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 2541#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 2542#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 2543#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 2544#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2545#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2546#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 2547#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 2548#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 2549#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 2550#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 2551#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 2552#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg)) 2553#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 2554#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) 2555#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) 2556#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg)) 2557#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v)) 2558#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg)) 2559#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v)) 2560#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg)) 2561#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v)) 2562#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg)) 2563#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v)) 2564#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) 2565#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) 2566#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg)) 2567#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v)) 2568#define WREG32_P(reg, val, mask) \ 2569 do { \ 2570 uint32_t tmp_ = RREG32(reg); \ 2571 tmp_ &= (mask); \ 2572 tmp_ |= ((val) & ~(mask)); \ 2573 WREG32(reg, tmp_); \ 2574 } while (0) 2575#define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2576#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2577#define WREG32_PLL_P(reg, val, mask) \ 2578 do { \ 2579 uint32_t tmp_ = RREG32_PLL(reg); \ 2580 tmp_ &= (mask); \ 2581 tmp_ |= ((val) & ~(mask)); \ 2582 WREG32_PLL(reg, tmp_); \ 2583 } while (0) 2584#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 2585#define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 2586#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 2587 2588#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index)) 2589#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v)) 2590 2591/* 2592 * Indirect registers accessor 2593 */ 2594static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 2595{ 2596 unsigned long flags; 2597 uint32_t r; 2598 2599 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2600 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2601 r = RREG32(RADEON_PCIE_DATA); 2602 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2603 return r; 2604} 2605 2606static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2607{ 2608 unsigned long flags; 2609 2610 spin_lock_irqsave(&rdev->pcie_idx_lock, flags); 2611 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 2612 WREG32(RADEON_PCIE_DATA, (v)); 2613 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags); 2614} 2615 2616static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) 2617{ 2618 unsigned long flags; 2619 u32 r; 2620 2621 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2622 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2623 r = RREG32(TN_SMC_IND_DATA_0); 2624 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2625 return r; 2626} 2627 2628static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2629{ 2630 unsigned long flags; 2631 2632 spin_lock_irqsave(&rdev->smc_idx_lock, flags); 2633 WREG32(TN_SMC_IND_INDEX_0, (reg)); 2634 WREG32(TN_SMC_IND_DATA_0, (v)); 2635 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); 2636} 2637 2638static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg) 2639{ 2640 unsigned long flags; 2641 u32 r; 2642 2643 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2644 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2645 r = RREG32(R600_RCU_DATA); 2646 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2647 return r; 2648} 2649 2650static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2651{ 2652 unsigned long flags; 2653 2654 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); 2655 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff)); 2656 WREG32(R600_RCU_DATA, (v)); 2657 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); 2658} 2659 2660static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) 2661{ 2662 unsigned long flags; 2663 u32 r; 2664 2665 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2666 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2667 r = RREG32(EVERGREEN_CG_IND_DATA); 2668 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2669 return r; 2670} 2671 2672static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2673{ 2674 unsigned long flags; 2675 2676 spin_lock_irqsave(&rdev->cg_idx_lock, flags); 2677 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); 2678 WREG32(EVERGREEN_CG_IND_DATA, (v)); 2679 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); 2680} 2681 2682static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) 2683{ 2684 unsigned long flags; 2685 u32 r; 2686 2687 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2688 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2689 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2690 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2691 return r; 2692} 2693 2694static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2695{ 2696 unsigned long flags; 2697 2698 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2699 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2700 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2701 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2702} 2703 2704static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) 2705{ 2706 unsigned long flags; 2707 u32 r; 2708 2709 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2710 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2711 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2712 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2713 return r; 2714} 2715 2716static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2717{ 2718 unsigned long flags; 2719 2720 spin_lock_irqsave(&rdev->pif_idx_lock, flags); 2721 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2722 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2723 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); 2724} 2725 2726static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg) 2727{ 2728 unsigned long flags; 2729 u32 r; 2730 2731 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2732 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2733 r = RREG32(R600_UVD_CTX_DATA); 2734 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2735 return r; 2736} 2737 2738static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2739{ 2740 unsigned long flags; 2741 2742 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); 2743 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff)); 2744 WREG32(R600_UVD_CTX_DATA, (v)); 2745 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); 2746} 2747 2748 2749static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg) 2750{ 2751 unsigned long flags; 2752 u32 r; 2753 2754 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2755 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2756 r = RREG32(CIK_DIDT_IND_DATA); 2757 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2758 return r; 2759} 2760 2761static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v) 2762{ 2763 unsigned long flags; 2764 2765 spin_lock_irqsave(&rdev->didt_idx_lock, flags); 2766 WREG32(CIK_DIDT_IND_INDEX, (reg)); 2767 WREG32(CIK_DIDT_IND_DATA, (v)); 2768 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags); 2769} 2770 2771void r100_pll_errata_after_index(struct radeon_device *rdev); 2772 2773 2774/* 2775 * ASICs helpers. 2776 */ 2777#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 2778 (rdev->pdev->device == 0x5969)) 2779#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 2780 (rdev->family == CHIP_RV200) || \ 2781 (rdev->family == CHIP_RS100) || \ 2782 (rdev->family == CHIP_RS200) || \ 2783 (rdev->family == CHIP_RV250) || \ 2784 (rdev->family == CHIP_RV280) || \ 2785 (rdev->family == CHIP_RS300)) 2786#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 2787 (rdev->family == CHIP_RV350) || \ 2788 (rdev->family == CHIP_R350) || \ 2789 (rdev->family == CHIP_RV380) || \ 2790 (rdev->family == CHIP_R420) || \ 2791 (rdev->family == CHIP_R423) || \ 2792 (rdev->family == CHIP_RV410) || \ 2793 (rdev->family == CHIP_RS400) || \ 2794 (rdev->family == CHIP_RS480)) 2795#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 2796 (rdev->ddev->pdev->device == 0x9443) || \ 2797 (rdev->ddev->pdev->device == 0x944B) || \ 2798 (rdev->ddev->pdev->device == 0x9506) || \ 2799 (rdev->ddev->pdev->device == 0x9509) || \ 2800 (rdev->ddev->pdev->device == 0x950F) || \ 2801 (rdev->ddev->pdev->device == 0x689C) || \ 2802 (rdev->ddev->pdev->device == 0x689D)) 2803#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 2804#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 2805 (rdev->family == CHIP_RS690) || \ 2806 (rdev->family == CHIP_RS740) || \ 2807 (rdev->family >= CHIP_R600)) 2808#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 2809#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 2810#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 2811#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 2812 (rdev->flags & RADEON_IS_IGP)) 2813#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 2814#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 2815#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 2816 (rdev->flags & RADEON_IS_IGP)) 2817#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND)) 2818#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN)) 2819#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE)) 2820#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI)) 2821#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE)) 2822#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \ 2823 (rdev->family == CHIP_MULLINS)) 2824 2825#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \ 2826 (rdev->ddev->pdev->device == 0x6850) || \ 2827 (rdev->ddev->pdev->device == 0x6858) || \ 2828 (rdev->ddev->pdev->device == 0x6859) || \ 2829 (rdev->ddev->pdev->device == 0x6840) || \ 2830 (rdev->ddev->pdev->device == 0x6841) || \ 2831 (rdev->ddev->pdev->device == 0x6842) || \ 2832 (rdev->ddev->pdev->device == 0x6843)) 2833 2834/* 2835 * BIOS helpers. 2836 */ 2837#define RBIOS8(i) (rdev->bios[i]) 2838#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2839#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2840 2841int radeon_combios_init(struct radeon_device *rdev); 2842void radeon_combios_fini(struct radeon_device *rdev); 2843int radeon_atombios_init(struct radeon_device *rdev); 2844void radeon_atombios_fini(struct radeon_device *rdev); 2845 2846 2847/* 2848 * RING helpers. 2849 */ 2850 2851/** 2852 * radeon_ring_write - write a value to the ring 2853 * 2854 * @ring: radeon_ring structure holding ring information 2855 * @v: dword (dw) value to write 2856 * 2857 * Write a value to the requested ring buffer (all asics). 2858 */ 2859static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 2860{ 2861 if (ring->count_dw <= 0) 2862 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n"); 2863 2864 ring->ring[ring->wptr++] = v; 2865 ring->wptr &= ring->ptr_mask; 2866 ring->count_dw--; 2867 ring->ring_free_dw--; 2868} 2869 2870/* 2871 * ASICs macro. 2872 */ 2873#define radeon_init(rdev) (rdev)->asic->init((rdev)) 2874#define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 2875#define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 2876#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 2877#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p)) 2878#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 2879#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 2880#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 2881#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f)) 2882#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e)) 2883#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 2884#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 2885#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count))) 2886#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2887#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags))) 2888#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib))) 2889#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp)) 2890#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp)) 2891#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp)) 2892#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2893#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2894#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2895#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr)) 2896#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2897#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2898#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2899#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 2900#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 2901#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 2902#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 2903#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 2904#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b)) 2905#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m)) 2906#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence)) 2907#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 2908#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv)) 2909#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv)) 2910#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv)) 2911#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 2912#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 2913#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 2914#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 2915#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 2916#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 2917#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 2918#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 2919#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 2920#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 2921#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d)) 2922#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec)) 2923#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev)) 2924#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 2925#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 2926#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 2927#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 2928#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 2929#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 2930#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 2931#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 2932#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 2933#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 2934#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 2935#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 2936#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 2937#define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 2938#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc)) 2939#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 2940#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 2941#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev)) 2942#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev)) 2943#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v)) 2944#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev)) 2945#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev)) 2946#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev)) 2947#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev)) 2948#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev)) 2949#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev)) 2950#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev)) 2951#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev)) 2952#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev)) 2953#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev)) 2954#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l)) 2955#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l)) 2956#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps)) 2957#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m)) 2958#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l)) 2959#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev)) 2960#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g)) 2961#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e)) 2962#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev)) 2963#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev)) 2964 2965/* Common functions */ 2966/* AGP */ 2967extern int radeon_gpu_reset(struct radeon_device *rdev); 2968extern void radeon_pci_config_reset(struct radeon_device *rdev); 2969extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung); 2970extern void radeon_agp_disable(struct radeon_device *rdev); 2971extern int radeon_modeset_init(struct radeon_device *rdev); 2972extern void radeon_modeset_fini(struct radeon_device *rdev); 2973extern bool radeon_card_posted(struct radeon_device *rdev); 2974extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 2975extern void radeon_update_display_priority(struct radeon_device *rdev); 2976extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 2977extern void radeon_scratch_init(struct radeon_device *rdev); 2978extern void radeon_wb_fini(struct radeon_device *rdev); 2979extern int radeon_wb_init(struct radeon_device *rdev); 2980extern void radeon_wb_disable(struct radeon_device *rdev); 2981extern void radeon_surface_init(struct radeon_device *rdev); 2982extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 2983extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 2984extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 2985extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 2986extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 2987extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2988 uint32_t flags); 2989extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm); 2990extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm); 2991extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 2992extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 2993extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2994extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2995extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 2996extern void radeon_program_register_sequence(struct radeon_device *rdev, 2997 const u32 *registers, 2998 const u32 array_size); 2999 3000/* 3001 * vm 3002 */ 3003int radeon_vm_manager_init(struct radeon_device *rdev); 3004void radeon_vm_manager_fini(struct radeon_device *rdev); 3005int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 3006void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 3007struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev, 3008 struct radeon_vm *vm, 3009 struct list_head *head); 3010struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 3011 struct radeon_vm *vm, int ring); 3012void radeon_vm_flush(struct radeon_device *rdev, 3013 struct radeon_vm *vm, 3014 int ring, struct radeon_fence *fence); 3015void radeon_vm_fence(struct radeon_device *rdev, 3016 struct radeon_vm *vm, 3017 struct radeon_fence *fence); 3018uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 3019int radeon_vm_update_page_directory(struct radeon_device *rdev, 3020 struct radeon_vm *vm); 3021int radeon_vm_clear_freed(struct radeon_device *rdev, 3022 struct radeon_vm *vm); 3023int radeon_vm_clear_invalids(struct radeon_device *rdev, 3024 struct radeon_vm *vm); 3025int radeon_vm_bo_update(struct radeon_device *rdev, 3026 struct radeon_bo_va *bo_va, 3027 struct ttm_mem_reg *mem); 3028void radeon_vm_bo_invalidate(struct radeon_device *rdev, 3029 struct radeon_bo *bo); 3030struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 3031 struct radeon_bo *bo); 3032struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 3033 struct radeon_vm *vm, 3034 struct radeon_bo *bo); 3035int radeon_vm_bo_set_addr(struct radeon_device *rdev, 3036 struct radeon_bo_va *bo_va, 3037 uint64_t offset, 3038 uint32_t flags); 3039void radeon_vm_bo_rmv(struct radeon_device *rdev, 3040 struct radeon_bo_va *bo_va); 3041 3042/* audio */ 3043void r600_audio_update_hdmi(struct work_struct *work); 3044struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); 3045struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); 3046void r600_audio_enable(struct radeon_device *rdev, 3047 struct r600_audio_pin *pin, 3048 u8 enable_mask); 3049void dce6_audio_enable(struct radeon_device *rdev, 3050 struct r600_audio_pin *pin, 3051 u8 enable_mask); 3052 3053/* 3054 * R600 vram scratch functions 3055 */ 3056int r600_vram_scratch_init(struct radeon_device *rdev); 3057void r600_vram_scratch_fini(struct radeon_device *rdev); 3058 3059/* 3060 * r600 cs checking helper 3061 */ 3062unsigned r600_mip_minify(unsigned size, unsigned level); 3063bool r600_fmt_is_valid_color(u32 format); 3064bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 3065int r600_fmt_get_blocksize(u32 format); 3066int r600_fmt_get_nblocksx(u32 format, u32 w); 3067int r600_fmt_get_nblocksy(u32 format, u32 h); 3068 3069/* 3070 * r600 functions used by radeon_encoder.c 3071 */ 3072struct radeon_hdmi_acr { 3073 u32 clock; 3074 3075 int n_32khz; 3076 int cts_32khz; 3077 3078 int n_44_1khz; 3079 int cts_44_1khz; 3080 3081 int n_48khz; 3082 int cts_48khz; 3083 3084}; 3085 3086extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 3087 3088extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 3089 u32 tiling_pipe_num, 3090 u32 max_rb_num, 3091 u32 total_max_rb_num, 3092 u32 enabled_rb_mask); 3093 3094/* 3095 * evergreen functions used by radeon_encoder.c 3096 */ 3097 3098extern int ni_init_microcode(struct radeon_device *rdev); 3099extern int ni_mc_load_microcode(struct radeon_device *rdev); 3100 3101/* radeon_acpi.c */ 3102#if defined(CONFIG_ACPI) 3103extern int radeon_acpi_init(struct radeon_device *rdev); 3104extern void radeon_acpi_fini(struct radeon_device *rdev); 3105extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev); 3106extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev, 3107 u8 perf_req, bool advertise); 3108extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev); 3109#else 3110static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 3111static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 3112#endif 3113 3114int radeon_cs_packet_parse(struct radeon_cs_parser *p, 3115 struct radeon_cs_packet *pkt, 3116 unsigned idx); 3117bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p); 3118void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3119 struct radeon_cs_packet *pkt); 3120int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3121 struct radeon_bo_list **cs_reloc, 3122 int nomm); 3123int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3124 uint32_t *vline_start_end, 3125 uint32_t *vline_status); 3126 3127#include "radeon_object.h" 3128 3129#endif 3130