1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include "drmP.h" 25#include "radeon.h" 26#include "radeon_asic.h" 27#include "sid.h" 28#include "r600_dpm.h" 29#include "si_dpm.h" 30#include "atom.h" 31#include <linux/math64.h> 32#include <linux/seq_file.h> 33 34#define MC_CG_ARB_FREQ_F0 0x0a 35#define MC_CG_ARB_FREQ_F1 0x0b 36#define MC_CG_ARB_FREQ_F2 0x0c 37#define MC_CG_ARB_FREQ_F3 0x0d 38 39#define SMC_RAM_END 0x20000 40 41#define SCLK_MIN_DEEPSLEEP_FREQ 1350 42 43static const struct si_cac_config_reg cac_weights_tahiti[] = 44{ 45 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 46 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 47 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 49 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 50 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 56 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 58 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 59 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 61 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 63 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 64 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 65 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 67 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 68 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 77 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 80 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 81 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 83 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 84 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 86 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 105 { 0xFFFFFFFF } 106}; 107 108static const struct si_cac_config_reg lcac_tahiti[] = 109{ 110 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 111 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 112 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 114 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 116 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 118 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 120 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 124 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 126 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 128 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 130 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 134 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 138 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 140 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 142 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 144 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 146 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 148 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 150 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 152 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 154 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 156 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 158 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 162 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 164 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 166 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 168 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 170 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 174 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 176 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 178 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 180 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 186 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 188 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 190 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 192 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 196 { 0xFFFFFFFF } 197 198}; 199 200static const struct si_cac_config_reg cac_override_tahiti[] = 201{ 202 { 0xFFFFFFFF } 203}; 204 205static const struct si_powertune_data powertune_data_tahiti = 206{ 207 ((1 << 16) | 27027), 208 6, 209 0, 210 4, 211 95, 212 { 213 0UL, 214 0UL, 215 4521550UL, 216 309631529UL, 217 -1270850L, 218 4513710L, 219 40 220 }, 221 595000000UL, 222 12, 223 { 224 0, 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0 232 }, 233 true 234}; 235 236static const struct si_dte_data dte_data_tahiti = 237{ 238 { 1159409, 0, 0, 0, 0 }, 239 { 777, 0, 0, 0, 0 }, 240 2, 241 54000, 242 127000, 243 25, 244 2, 245 10, 246 13, 247 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 248 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 249 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 250 85, 251 false 252}; 253 254static const struct si_dte_data dte_data_tahiti_le = 255{ 256 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 }, 257 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 }, 258 0x5, 259 0xAFC8, 260 0x64, 261 0x32, 262 1, 263 0, 264 0x10, 265 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 }, 266 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 }, 267 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 }, 268 85, 269 true 270}; 271 272static const struct si_dte_data dte_data_tahiti_pro = 273{ 274 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 275 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 276 5, 277 45000, 278 100, 279 0xA, 280 1, 281 0, 282 0x10, 283 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 284 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 285 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 286 90, 287 true 288}; 289 290static const struct si_dte_data dte_data_new_zealand = 291{ 292 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 293 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 294 0x5, 295 0xAFC8, 296 0x69, 297 0x32, 298 1, 299 0, 300 0x10, 301 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 302 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 303 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 304 85, 305 true 306}; 307 308static const struct si_dte_data dte_data_aruba_pro = 309{ 310 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 311 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 312 5, 313 45000, 314 100, 315 0xA, 316 1, 317 0, 318 0x10, 319 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 320 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 321 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 322 90, 323 true 324}; 325 326static const struct si_dte_data dte_data_malta = 327{ 328 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 329 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 330 5, 331 45000, 332 100, 333 0xA, 334 1, 335 0, 336 0x10, 337 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 338 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 339 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 340 90, 341 true 342}; 343 344struct si_cac_config_reg cac_weights_pitcairn[] = 345{ 346 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 347 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 348 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 349 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 350 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 351 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 352 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 354 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 355 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 356 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 357 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 358 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 359 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 360 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 362 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 364 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 365 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 366 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 367 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 368 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 369 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 372 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 373 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 377 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 379 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 381 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 382 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 383 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 385 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 389 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 390 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 391 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 392 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 393 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 394 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 395 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 396 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 397 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 398 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 399 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 400 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 401 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 402 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 403 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 404 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 405 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 406 { 0xFFFFFFFF } 407}; 408 409static const struct si_cac_config_reg lcac_pitcairn[] = 410{ 411 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 412 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 413 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 414 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 415 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 416 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 417 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 418 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 419 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 420 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 421 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 422 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 423 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 424 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 425 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 426 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 427 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 428 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 429 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 430 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 431 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 432 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 433 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 434 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 435 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 436 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 437 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 438 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 439 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 440 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 441 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 442 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 443 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 444 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 445 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 446 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 447 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 448 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 449 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 450 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 451 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 452 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 453 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 454 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 455 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 456 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 457 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 458 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 459 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 460 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 461 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 462 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 463 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 464 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 465 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 466 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 467 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 468 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 469 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 470 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 471 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 472 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 473 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 474 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 475 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 476 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 477 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 478 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 479 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 480 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 481 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 482 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 483 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 484 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 485 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 486 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 487 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 488 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 489 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 490 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 491 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 492 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 493 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 495 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 496 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 497 { 0xFFFFFFFF } 498}; 499 500static const struct si_cac_config_reg cac_override_pitcairn[] = 501{ 502 { 0xFFFFFFFF } 503}; 504 505static const struct si_powertune_data powertune_data_pitcairn = 506{ 507 ((1 << 16) | 27027), 508 5, 509 0, 510 6, 511 100, 512 { 513 51600000UL, 514 1800000UL, 515 7194395UL, 516 309631529UL, 517 -1270850L, 518 4513710L, 519 100 520 }, 521 117830498UL, 522 12, 523 { 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 0, 531 0 532 }, 533 true 534}; 535 536static const struct si_dte_data dte_data_pitcairn = 537{ 538 { 0, 0, 0, 0, 0 }, 539 { 0, 0, 0, 0, 0 }, 540 0, 541 0, 542 0, 543 0, 544 0, 545 0, 546 0, 547 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 548 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 549 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 550 0, 551 false 552}; 553 554static const struct si_dte_data dte_data_curacao_xt = 555{ 556 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 557 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 558 5, 559 45000, 560 100, 561 0xA, 562 1, 563 0, 564 0x10, 565 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 566 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 567 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 568 90, 569 true 570}; 571 572static const struct si_dte_data dte_data_curacao_pro = 573{ 574 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 575 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 576 5, 577 45000, 578 100, 579 0xA, 580 1, 581 0, 582 0x10, 583 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 584 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 585 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 586 90, 587 true 588}; 589 590static const struct si_dte_data dte_data_neptune_xt = 591{ 592 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 593 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 594 5, 595 45000, 596 100, 597 0xA, 598 1, 599 0, 600 0x10, 601 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 602 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 603 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 604 90, 605 true 606}; 607 608static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 609{ 610 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 611 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 612 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 613 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 614 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 615 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 616 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 617 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 618 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 619 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 620 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 621 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 622 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 623 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 624 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 625 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 626 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 627 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 628 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 629 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 630 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 631 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 632 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 633 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 634 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 635 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 636 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 637 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 639 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 640 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 641 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 642 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 643 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 644 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 645 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 646 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 648 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 650 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 651 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 653 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 654 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 655 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 656 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 657 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 658 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 659 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 662 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 664 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 665 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 666 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 667 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 668 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 669 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 670 { 0xFFFFFFFF } 671}; 672 673static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 674{ 675 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 676 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 677 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 678 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 679 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 680 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 681 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 682 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 683 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 684 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 685 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 686 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 687 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 688 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 689 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 690 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 691 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 692 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 693 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 694 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 695 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 696 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 697 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 698 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 699 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 700 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 701 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 702 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 704 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 705 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 706 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 707 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 708 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 709 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 710 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 711 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 713 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 715 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 716 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 718 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 719 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 720 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 721 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 723 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 724 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 727 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 729 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 730 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 731 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 732 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 733 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 734 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 735 { 0xFFFFFFFF } 736}; 737 738static const struct si_cac_config_reg cac_weights_heathrow[] = 739{ 740 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 741 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 742 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 743 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 744 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 746 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 747 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 748 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 749 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 750 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 751 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 752 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 754 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 755 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 756 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 757 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 758 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 759 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 760 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 761 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 762 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 763 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 764 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 765 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 766 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 767 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 769 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 770 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 771 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 772 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 773 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 774 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 775 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 776 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 778 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 780 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 781 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 783 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 784 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 785 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 786 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 788 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 789 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 792 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 794 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 795 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 796 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 797 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 798 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 799 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 800 { 0xFFFFFFFF } 801}; 802 803static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 804{ 805 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 806 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 807 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 808 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 809 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 811 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 812 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 813 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 814 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 815 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 816 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 817 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 818 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 819 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 820 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 821 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 822 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 823 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 824 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 825 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 826 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 827 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 828 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 829 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 830 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 831 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 832 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 834 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 835 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 836 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 837 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 838 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 839 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 840 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 841 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 843 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 845 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 846 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 848 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 849 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 850 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 851 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 853 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 854 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 857 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 859 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 860 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 861 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 862 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 863 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 864 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 865 { 0xFFFFFFFF } 866}; 867 868static const struct si_cac_config_reg cac_weights_cape_verde[] = 869{ 870 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 871 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 872 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 873 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 874 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 876 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 877 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 878 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 879 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 880 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 881 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 882 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 883 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 884 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 885 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 886 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 887 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 888 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 889 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 890 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 891 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 892 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 893 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 894 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 895 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 896 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 897 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 899 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 900 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 901 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 902 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 903 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 904 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 905 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 906 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 908 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 910 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 911 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 913 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 914 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 915 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 916 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 918 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 919 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 920 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 921 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 922 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 923 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 924 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 925 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 926 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 927 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 928 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 929 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 930 { 0xFFFFFFFF } 931}; 932 933static const struct si_cac_config_reg lcac_cape_verde[] = 934{ 935 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 936 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 937 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 938 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 940 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 942 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 943 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 944 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 945 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 947 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 948 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 949 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 950 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 951 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 952 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 953 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 954 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 955 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 957 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 959 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 960 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 962 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 963 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 964 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 966 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 968 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 970 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 972 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 973 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 974 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 975 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 976 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 977 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 978 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 979 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 980 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 981 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 982 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 983 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 984 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 985 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 986 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 987 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 988 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 989 { 0xFFFFFFFF } 990}; 991 992static const struct si_cac_config_reg cac_override_cape_verde[] = 993{ 994 { 0xFFFFFFFF } 995}; 996 997static const struct si_powertune_data powertune_data_cape_verde = 998{ 999 ((1 << 16) | 0x6993), 1000 5, 1001 0, 1002 7, 1003 105, 1004 { 1005 0UL, 1006 0UL, 1007 7194395UL, 1008 309631529UL, 1009 -1270850L, 1010 4513710L, 1011 100 1012 }, 1013 117830498UL, 1014 12, 1015 { 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 0, 1023 0 1024 }, 1025 true 1026}; 1027 1028static const struct si_dte_data dte_data_cape_verde = 1029{ 1030 { 0, 0, 0, 0, 0 }, 1031 { 0, 0, 0, 0, 0 }, 1032 0, 1033 0, 1034 0, 1035 0, 1036 0, 1037 0, 1038 0, 1039 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1040 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1041 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1042 0, 1043 false 1044}; 1045 1046static const struct si_dte_data dte_data_venus_xtx = 1047{ 1048 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1049 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1050 5, 1051 55000, 1052 0x69, 1053 0xA, 1054 1, 1055 0, 1056 0x3, 1057 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1058 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 90, 1061 true 1062}; 1063 1064static const struct si_dte_data dte_data_venus_xt = 1065{ 1066 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1067 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1068 5, 1069 55000, 1070 0x69, 1071 0xA, 1072 1, 1073 0, 1074 0x3, 1075 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1076 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 90, 1079 true 1080}; 1081 1082static const struct si_dte_data dte_data_venus_pro = 1083{ 1084 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1085 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1086 5, 1087 55000, 1088 0x69, 1089 0xA, 1090 1, 1091 0, 1092 0x3, 1093 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1094 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1095 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1096 90, 1097 true 1098}; 1099 1100struct si_cac_config_reg cac_weights_oland[] = 1101{ 1102 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1104 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1105 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1106 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1107 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1108 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1109 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1110 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1111 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1112 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1121 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1122 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1123 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1124 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1125 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1126 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1127 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1128 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1129 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1145 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1146 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1147 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1148 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1149 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1150 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1162 { 0xFFFFFFFF } 1163}; 1164 1165static const struct si_cac_config_reg cac_weights_mars_pro[] = 1166{ 1167 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1169 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1170 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1171 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1172 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1173 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1174 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1175 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1176 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1177 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1186 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1187 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1188 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1189 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1190 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1191 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1192 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1193 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1194 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1227 { 0xFFFFFFFF } 1228}; 1229 1230static const struct si_cac_config_reg cac_weights_mars_xt[] = 1231{ 1232 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1234 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1235 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1236 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1251 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1252 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1253 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1254 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1255 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1256 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1257 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1258 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1259 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1292 { 0xFFFFFFFF } 1293}; 1294 1295static const struct si_cac_config_reg cac_weights_oland_pro[] = 1296{ 1297 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1299 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1300 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1301 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1316 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1317 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1318 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1319 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1320 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1321 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1322 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1323 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1324 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1357 { 0xFFFFFFFF } 1358}; 1359 1360static const struct si_cac_config_reg cac_weights_oland_xt[] = 1361{ 1362 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1364 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1365 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1366 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1381 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1382 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1383 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1384 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1385 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1386 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1387 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1388 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1389 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1422 { 0xFFFFFFFF } 1423}; 1424 1425static const struct si_cac_config_reg lcac_oland[] = 1426{ 1427 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0xFFFFFFFF } 1470}; 1471 1472static const struct si_cac_config_reg lcac_mars_pro[] = 1473{ 1474 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1516 { 0xFFFFFFFF } 1517}; 1518 1519static const struct si_cac_config_reg cac_override_oland[] = 1520{ 1521 { 0xFFFFFFFF } 1522}; 1523 1524static const struct si_powertune_data powertune_data_oland = 1525{ 1526 ((1 << 16) | 0x6993), 1527 5, 1528 0, 1529 7, 1530 105, 1531 { 1532 0UL, 1533 0UL, 1534 7194395UL, 1535 309631529UL, 1536 -1270850L, 1537 4513710L, 1538 100 1539 }, 1540 117830498UL, 1541 12, 1542 { 1543 0, 1544 0, 1545 0, 1546 0, 1547 0, 1548 0, 1549 0, 1550 0 1551 }, 1552 true 1553}; 1554 1555static const struct si_powertune_data powertune_data_mars_pro = 1556{ 1557 ((1 << 16) | 0x6993), 1558 5, 1559 0, 1560 7, 1561 105, 1562 { 1563 0UL, 1564 0UL, 1565 7194395UL, 1566 309631529UL, 1567 -1270850L, 1568 4513710L, 1569 100 1570 }, 1571 117830498UL, 1572 12, 1573 { 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 0, 1581 0 1582 }, 1583 true 1584}; 1585 1586static const struct si_dte_data dte_data_oland = 1587{ 1588 { 0, 0, 0, 0, 0 }, 1589 { 0, 0, 0, 0, 0 }, 1590 0, 1591 0, 1592 0, 1593 0, 1594 0, 1595 0, 1596 0, 1597 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1598 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1600 0, 1601 false 1602}; 1603 1604static const struct si_dte_data dte_data_mars_pro = 1605{ 1606 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1607 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1608 5, 1609 55000, 1610 105, 1611 0xA, 1612 1, 1613 0, 1614 0x10, 1615 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1616 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1617 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1618 90, 1619 true 1620}; 1621 1622static const struct si_dte_data dte_data_sun_xt = 1623{ 1624 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1625 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1626 5, 1627 55000, 1628 105, 1629 0xA, 1630 1, 1631 0, 1632 0x10, 1633 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1634 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1635 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1636 90, 1637 true 1638}; 1639 1640 1641static const struct si_cac_config_reg cac_weights_hainan[] = 1642{ 1643 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1645 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1646 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1647 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1648 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1649 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1650 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1652 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1653 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1662 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1663 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1664 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1665 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1666 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1667 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1668 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1669 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1670 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1686 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1687 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1688 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1689 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1690 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1691 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1692 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1693 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1694 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1695 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1696 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1697 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1698 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1699 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1700 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1701 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1702 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1703 { 0xFFFFFFFF } 1704}; 1705 1706static const struct si_powertune_data powertune_data_hainan = 1707{ 1708 ((1 << 16) | 0x6993), 1709 5, 1710 0, 1711 9, 1712 105, 1713 { 1714 0UL, 1715 0UL, 1716 7194395UL, 1717 309631529UL, 1718 -1270850L, 1719 4513710L, 1720 100 1721 }, 1722 117830498UL, 1723 12, 1724 { 1725 0, 1726 0, 1727 0, 1728 0, 1729 0, 1730 0, 1731 0, 1732 0 1733 }, 1734 true 1735}; 1736 1737struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1738struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1739struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1740struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1741 1742extern int si_mc_load_microcode(struct radeon_device *rdev); 1743 1744static int si_populate_voltage_value(struct radeon_device *rdev, 1745 const struct atom_voltage_table *table, 1746 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1747static int si_get_std_voltage_value(struct radeon_device *rdev, 1748 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1749 u16 *std_voltage); 1750static int si_write_smc_soft_register(struct radeon_device *rdev, 1751 u16 reg_offset, u32 value); 1752static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1753 struct rv7xx_pl *pl, 1754 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1755static int si_calculate_sclk_params(struct radeon_device *rdev, 1756 u32 engine_clock, 1757 SISLANDS_SMC_SCLK_VALUE *sclk); 1758 1759static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1760static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1761 1762static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1763{ 1764 struct si_power_info *pi = rdev->pm.dpm.priv; 1765 1766 return pi; 1767} 1768 1769static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1770 u16 v, s32 t, u32 ileakage, u32 *leakage) 1771{ 1772 s64 kt, kv, leakage_w, i_leakage, vddc; 1773 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1774 s64 tmp; 1775 1776 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1777 vddc = div64_s64(drm_int2fixp(v), 1000); 1778 temperature = div64_s64(drm_int2fixp(t), 1000); 1779 1780 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1781 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1782 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1783 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1784 t_ref = drm_int2fixp(coeff->t_ref); 1785 1786 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1787 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1788 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1789 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1790 1791 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1792 1793 *leakage = drm_fixp2int(leakage_w * 1000); 1794} 1795 1796static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1797 const struct ni_leakage_coeffients *coeff, 1798 u16 v, 1799 s32 t, 1800 u32 i_leakage, 1801 u32 *leakage) 1802{ 1803 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1804} 1805 1806static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1807 const u32 fixed_kt, u16 v, 1808 u32 ileakage, u32 *leakage) 1809{ 1810 s64 kt, kv, leakage_w, i_leakage, vddc; 1811 1812 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1813 vddc = div64_s64(drm_int2fixp(v), 1000); 1814 1815 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1816 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1817 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1818 1819 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1820 1821 *leakage = drm_fixp2int(leakage_w * 1000); 1822} 1823 1824static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1825 const struct ni_leakage_coeffients *coeff, 1826 const u32 fixed_kt, 1827 u16 v, 1828 u32 i_leakage, 1829 u32 *leakage) 1830{ 1831 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1832} 1833 1834 1835static void si_update_dte_from_pl2(struct radeon_device *rdev, 1836 struct si_dte_data *dte_data) 1837{ 1838 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1839 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1840 u32 k = dte_data->k; 1841 u32 t_max = dte_data->max_t; 1842 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1843 u32 t_0 = dte_data->t0; 1844 u32 i; 1845 1846 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1847 dte_data->tdep_count = 3; 1848 1849 for (i = 0; i < k; i++) { 1850 dte_data->r[i] = 1851 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1852 (p_limit2 * (u32)100); 1853 } 1854 1855 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1856 1857 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1858 dte_data->tdep_r[i] = dte_data->r[4]; 1859 } 1860 } else { 1861 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1862 } 1863} 1864 1865static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1866{ 1867 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1868 struct si_power_info *si_pi = si_get_pi(rdev); 1869 bool update_dte_from_pl2 = false; 1870 1871 if (rdev->family == CHIP_TAHITI) { 1872 si_pi->cac_weights = cac_weights_tahiti; 1873 si_pi->lcac_config = lcac_tahiti; 1874 si_pi->cac_override = cac_override_tahiti; 1875 si_pi->powertune_data = &powertune_data_tahiti; 1876 si_pi->dte_data = dte_data_tahiti; 1877 1878 switch (rdev->pdev->device) { 1879 case 0x6798: 1880 si_pi->dte_data.enable_dte_by_default = true; 1881 break; 1882 case 0x6799: 1883 si_pi->dte_data = dte_data_new_zealand; 1884 break; 1885 case 0x6790: 1886 case 0x6791: 1887 case 0x6792: 1888 case 0x679E: 1889 si_pi->dte_data = dte_data_aruba_pro; 1890 update_dte_from_pl2 = true; 1891 break; 1892 case 0x679B: 1893 si_pi->dte_data = dte_data_malta; 1894 update_dte_from_pl2 = true; 1895 break; 1896 case 0x679A: 1897 si_pi->dte_data = dte_data_tahiti_pro; 1898 update_dte_from_pl2 = true; 1899 break; 1900 default: 1901 if (si_pi->dte_data.enable_dte_by_default == true) 1902 DRM_ERROR("DTE is not enabled!\n"); 1903 break; 1904 } 1905 } else if (rdev->family == CHIP_PITCAIRN) { 1906 switch (rdev->pdev->device) { 1907 case 0x6810: 1908 case 0x6818: 1909 si_pi->cac_weights = cac_weights_pitcairn; 1910 si_pi->lcac_config = lcac_pitcairn; 1911 si_pi->cac_override = cac_override_pitcairn; 1912 si_pi->powertune_data = &powertune_data_pitcairn; 1913 si_pi->dte_data = dte_data_curacao_xt; 1914 update_dte_from_pl2 = true; 1915 break; 1916 case 0x6819: 1917 case 0x6811: 1918 si_pi->cac_weights = cac_weights_pitcairn; 1919 si_pi->lcac_config = lcac_pitcairn; 1920 si_pi->cac_override = cac_override_pitcairn; 1921 si_pi->powertune_data = &powertune_data_pitcairn; 1922 si_pi->dte_data = dte_data_curacao_pro; 1923 update_dte_from_pl2 = true; 1924 break; 1925 case 0x6800: 1926 case 0x6806: 1927 si_pi->cac_weights = cac_weights_pitcairn; 1928 si_pi->lcac_config = lcac_pitcairn; 1929 si_pi->cac_override = cac_override_pitcairn; 1930 si_pi->powertune_data = &powertune_data_pitcairn; 1931 si_pi->dte_data = dte_data_neptune_xt; 1932 update_dte_from_pl2 = true; 1933 break; 1934 default: 1935 si_pi->cac_weights = cac_weights_pitcairn; 1936 si_pi->lcac_config = lcac_pitcairn; 1937 si_pi->cac_override = cac_override_pitcairn; 1938 si_pi->powertune_data = &powertune_data_pitcairn; 1939 si_pi->dte_data = dte_data_pitcairn; 1940 break; 1941 } 1942 } else if (rdev->family == CHIP_VERDE) { 1943 si_pi->lcac_config = lcac_cape_verde; 1944 si_pi->cac_override = cac_override_cape_verde; 1945 si_pi->powertune_data = &powertune_data_cape_verde; 1946 1947 switch (rdev->pdev->device) { 1948 case 0x683B: 1949 case 0x683F: 1950 case 0x6829: 1951 case 0x6835: 1952 si_pi->cac_weights = cac_weights_cape_verde_pro; 1953 si_pi->dte_data = dte_data_cape_verde; 1954 break; 1955 case 0x682C: 1956 si_pi->cac_weights = cac_weights_cape_verde_pro; 1957 si_pi->dte_data = dte_data_sun_xt; 1958 break; 1959 case 0x6825: 1960 case 0x6827: 1961 si_pi->cac_weights = cac_weights_heathrow; 1962 si_pi->dte_data = dte_data_cape_verde; 1963 break; 1964 case 0x6824: 1965 case 0x682D: 1966 si_pi->cac_weights = cac_weights_chelsea_xt; 1967 si_pi->dte_data = dte_data_cape_verde; 1968 break; 1969 case 0x682F: 1970 si_pi->cac_weights = cac_weights_chelsea_pro; 1971 si_pi->dte_data = dte_data_cape_verde; 1972 break; 1973 case 0x6820: 1974 si_pi->cac_weights = cac_weights_heathrow; 1975 si_pi->dte_data = dte_data_venus_xtx; 1976 break; 1977 case 0x6821: 1978 si_pi->cac_weights = cac_weights_heathrow; 1979 si_pi->dte_data = dte_data_venus_xt; 1980 break; 1981 case 0x6823: 1982 case 0x682B: 1983 case 0x6822: 1984 case 0x682A: 1985 si_pi->cac_weights = cac_weights_chelsea_pro; 1986 si_pi->dte_data = dte_data_venus_pro; 1987 break; 1988 default: 1989 si_pi->cac_weights = cac_weights_cape_verde; 1990 si_pi->dte_data = dte_data_cape_verde; 1991 break; 1992 } 1993 } else if (rdev->family == CHIP_OLAND) { 1994 switch (rdev->pdev->device) { 1995 case 0x6601: 1996 case 0x6621: 1997 case 0x6603: 1998 case 0x6605: 1999 si_pi->cac_weights = cac_weights_mars_pro; 2000 si_pi->lcac_config = lcac_mars_pro; 2001 si_pi->cac_override = cac_override_oland; 2002 si_pi->powertune_data = &powertune_data_mars_pro; 2003 si_pi->dte_data = dte_data_mars_pro; 2004 update_dte_from_pl2 = true; 2005 break; 2006 case 0x6600: 2007 case 0x6606: 2008 case 0x6620: 2009 case 0x6604: 2010 si_pi->cac_weights = cac_weights_mars_xt; 2011 si_pi->lcac_config = lcac_mars_pro; 2012 si_pi->cac_override = cac_override_oland; 2013 si_pi->powertune_data = &powertune_data_mars_pro; 2014 si_pi->dte_data = dte_data_mars_pro; 2015 update_dte_from_pl2 = true; 2016 break; 2017 case 0x6611: 2018 case 0x6613: 2019 case 0x6608: 2020 si_pi->cac_weights = cac_weights_oland_pro; 2021 si_pi->lcac_config = lcac_mars_pro; 2022 si_pi->cac_override = cac_override_oland; 2023 si_pi->powertune_data = &powertune_data_mars_pro; 2024 si_pi->dte_data = dte_data_mars_pro; 2025 update_dte_from_pl2 = true; 2026 break; 2027 case 0x6610: 2028 si_pi->cac_weights = cac_weights_oland_xt; 2029 si_pi->lcac_config = lcac_mars_pro; 2030 si_pi->cac_override = cac_override_oland; 2031 si_pi->powertune_data = &powertune_data_mars_pro; 2032 si_pi->dte_data = dte_data_mars_pro; 2033 update_dte_from_pl2 = true; 2034 break; 2035 default: 2036 si_pi->cac_weights = cac_weights_oland; 2037 si_pi->lcac_config = lcac_oland; 2038 si_pi->cac_override = cac_override_oland; 2039 si_pi->powertune_data = &powertune_data_oland; 2040 si_pi->dte_data = dte_data_oland; 2041 break; 2042 } 2043 } else if (rdev->family == CHIP_HAINAN) { 2044 si_pi->cac_weights = cac_weights_hainan; 2045 si_pi->lcac_config = lcac_oland; 2046 si_pi->cac_override = cac_override_oland; 2047 si_pi->powertune_data = &powertune_data_hainan; 2048 si_pi->dte_data = dte_data_sun_xt; 2049 update_dte_from_pl2 = true; 2050 } else { 2051 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2052 return; 2053 } 2054 2055 ni_pi->enable_power_containment = false; 2056 ni_pi->enable_cac = false; 2057 ni_pi->enable_sq_ramping = false; 2058 si_pi->enable_dte = false; 2059 2060 if (si_pi->powertune_data->enable_powertune_by_default) { 2061 ni_pi->enable_power_containment= true; 2062 ni_pi->enable_cac = true; 2063 if (si_pi->dte_data.enable_dte_by_default) { 2064 si_pi->enable_dte = true; 2065 if (update_dte_from_pl2) 2066 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2067 2068 } 2069 ni_pi->enable_sq_ramping = true; 2070 } 2071 2072 ni_pi->driver_calculate_cac_leakage = true; 2073 ni_pi->cac_configuration_required = true; 2074 2075 if (ni_pi->cac_configuration_required) { 2076 ni_pi->support_cac_long_term_average = true; 2077 si_pi->dyn_powertune_data.l2_lta_window_size = 2078 si_pi->powertune_data->l2_lta_window_size_default; 2079 si_pi->dyn_powertune_data.lts_truncate = 2080 si_pi->powertune_data->lts_truncate_default; 2081 } else { 2082 ni_pi->support_cac_long_term_average = false; 2083 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2084 si_pi->dyn_powertune_data.lts_truncate = 0; 2085 } 2086 2087 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2088} 2089 2090static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2091{ 2092 return 1; 2093} 2094 2095static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2096{ 2097 u32 xclk; 2098 u32 wintime; 2099 u32 cac_window; 2100 u32 cac_window_size; 2101 2102 xclk = radeon_get_xclk(rdev); 2103 2104 if (xclk == 0) 2105 return 0; 2106 2107 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2108 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2109 2110 wintime = (cac_window_size * 100) / xclk; 2111 2112 return wintime; 2113} 2114 2115static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2116{ 2117 return power_in_watts; 2118} 2119 2120static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2121 bool adjust_polarity, 2122 u32 tdp_adjustment, 2123 u32 *tdp_limit, 2124 u32 *near_tdp_limit) 2125{ 2126 u32 adjustment_delta, max_tdp_limit; 2127 2128 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2129 return -EINVAL; 2130 2131 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2132 2133 if (adjust_polarity) { 2134 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2135 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2136 } else { 2137 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2138 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2139 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2140 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2141 else 2142 *near_tdp_limit = 0; 2143 } 2144 2145 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2146 return -EINVAL; 2147 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2148 return -EINVAL; 2149 2150 return 0; 2151} 2152 2153static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2154 struct radeon_ps *radeon_state) 2155{ 2156 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2157 struct si_power_info *si_pi = si_get_pi(rdev); 2158 2159 if (ni_pi->enable_power_containment) { 2160 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2161 PP_SIslands_PAPMParameters *papm_parm; 2162 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2163 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2164 u32 tdp_limit; 2165 u32 near_tdp_limit; 2166 int ret; 2167 2168 if (scaling_factor == 0) 2169 return -EINVAL; 2170 2171 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2172 2173 ret = si_calculate_adjusted_tdp_limits(rdev, 2174 false, /* ??? */ 2175 rdev->pm.dpm.tdp_adjustment, 2176 &tdp_limit, 2177 &near_tdp_limit); 2178 if (ret) 2179 return ret; 2180 2181 smc_table->dpm2Params.TDPLimit = 2182 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2183 smc_table->dpm2Params.NearTDPLimit = 2184 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2185 smc_table->dpm2Params.SafePowerLimit = 2186 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2187 2188 ret = si_copy_bytes_to_smc(rdev, 2189 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2190 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2191 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2192 sizeof(u32) * 3, 2193 si_pi->sram_end); 2194 if (ret) 2195 return ret; 2196 2197 if (si_pi->enable_ppm) { 2198 papm_parm = &si_pi->papm_parm; 2199 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2200 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2201 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2202 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2203 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2204 papm_parm->PlatformPowerLimit = 0xffffffff; 2205 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2206 2207 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2208 (u8 *)papm_parm, 2209 sizeof(PP_SIslands_PAPMParameters), 2210 si_pi->sram_end); 2211 if (ret) 2212 return ret; 2213 } 2214 } 2215 return 0; 2216} 2217 2218static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2219 struct radeon_ps *radeon_state) 2220{ 2221 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2222 struct si_power_info *si_pi = si_get_pi(rdev); 2223 2224 if (ni_pi->enable_power_containment) { 2225 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2226 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2227 int ret; 2228 2229 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2230 2231 smc_table->dpm2Params.NearTDPLimit = 2232 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2233 smc_table->dpm2Params.SafePowerLimit = 2234 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2235 2236 ret = si_copy_bytes_to_smc(rdev, 2237 (si_pi->state_table_start + 2238 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2239 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2240 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2241 sizeof(u32) * 2, 2242 si_pi->sram_end); 2243 if (ret) 2244 return ret; 2245 } 2246 2247 return 0; 2248} 2249 2250static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2251 const u16 prev_std_vddc, 2252 const u16 curr_std_vddc) 2253{ 2254 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2255 u64 prev_vddc = (u64)prev_std_vddc; 2256 u64 curr_vddc = (u64)curr_std_vddc; 2257 u64 pwr_efficiency_ratio, n, d; 2258 2259 if ((prev_vddc == 0) || (curr_vddc == 0)) 2260 return 0; 2261 2262 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2263 d = prev_vddc * prev_vddc; 2264 pwr_efficiency_ratio = div64_u64(n, d); 2265 2266 if (pwr_efficiency_ratio > (u64)0xFFFF) 2267 return 0; 2268 2269 return (u16)pwr_efficiency_ratio; 2270} 2271 2272static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2273 struct radeon_ps *radeon_state) 2274{ 2275 struct si_power_info *si_pi = si_get_pi(rdev); 2276 2277 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2278 radeon_state->vclk && radeon_state->dclk) 2279 return true; 2280 2281 return false; 2282} 2283 2284static int si_populate_power_containment_values(struct radeon_device *rdev, 2285 struct radeon_ps *radeon_state, 2286 SISLANDS_SMC_SWSTATE *smc_state) 2287{ 2288 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2289 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2290 struct ni_ps *state = ni_get_ps(radeon_state); 2291 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2292 u32 prev_sclk; 2293 u32 max_sclk; 2294 u32 min_sclk; 2295 u16 prev_std_vddc; 2296 u16 curr_std_vddc; 2297 int i; 2298 u16 pwr_efficiency_ratio; 2299 u8 max_ps_percent; 2300 bool disable_uvd_power_tune; 2301 int ret; 2302 2303 if (ni_pi->enable_power_containment == false) 2304 return 0; 2305 2306 if (state->performance_level_count == 0) 2307 return -EINVAL; 2308 2309 if (smc_state->levelCount != state->performance_level_count) 2310 return -EINVAL; 2311 2312 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2313 2314 smc_state->levels[0].dpm2.MaxPS = 0; 2315 smc_state->levels[0].dpm2.NearTDPDec = 0; 2316 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2317 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2318 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2319 2320 for (i = 1; i < state->performance_level_count; i++) { 2321 prev_sclk = state->performance_levels[i-1].sclk; 2322 max_sclk = state->performance_levels[i].sclk; 2323 if (i == 1) 2324 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2325 else 2326 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2327 2328 if (prev_sclk > max_sclk) 2329 return -EINVAL; 2330 2331 if ((max_ps_percent == 0) || 2332 (prev_sclk == max_sclk) || 2333 disable_uvd_power_tune) { 2334 min_sclk = max_sclk; 2335 } else if (i == 1) { 2336 min_sclk = prev_sclk; 2337 } else { 2338 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2339 } 2340 2341 if (min_sclk < state->performance_levels[0].sclk) 2342 min_sclk = state->performance_levels[0].sclk; 2343 2344 if (min_sclk == 0) 2345 return -EINVAL; 2346 2347 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2348 state->performance_levels[i-1].vddc, &vddc); 2349 if (ret) 2350 return ret; 2351 2352 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2353 if (ret) 2354 return ret; 2355 2356 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2357 state->performance_levels[i].vddc, &vddc); 2358 if (ret) 2359 return ret; 2360 2361 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2362 if (ret) 2363 return ret; 2364 2365 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2366 prev_std_vddc, curr_std_vddc); 2367 2368 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2369 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2370 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2371 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2372 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2373 } 2374 2375 return 0; 2376} 2377 2378static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2379 struct radeon_ps *radeon_state, 2380 SISLANDS_SMC_SWSTATE *smc_state) 2381{ 2382 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2383 struct ni_ps *state = ni_get_ps(radeon_state); 2384 u32 sq_power_throttle, sq_power_throttle2; 2385 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2386 int i; 2387 2388 if (state->performance_level_count == 0) 2389 return -EINVAL; 2390 2391 if (smc_state->levelCount != state->performance_level_count) 2392 return -EINVAL; 2393 2394 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2395 return -EINVAL; 2396 2397 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2398 enable_sq_ramping = false; 2399 2400 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2401 enable_sq_ramping = false; 2402 2403 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2404 enable_sq_ramping = false; 2405 2406 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2407 enable_sq_ramping = false; 2408 2409 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2410 enable_sq_ramping = false; 2411 2412 for (i = 0; i < state->performance_level_count; i++) { 2413 sq_power_throttle = 0; 2414 sq_power_throttle2 = 0; 2415 2416 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2417 enable_sq_ramping) { 2418 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2419 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2420 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2421 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2422 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2423 } else { 2424 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2425 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2426 } 2427 2428 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2429 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2430 } 2431 2432 return 0; 2433} 2434 2435static int si_enable_power_containment(struct radeon_device *rdev, 2436 struct radeon_ps *radeon_new_state, 2437 bool enable) 2438{ 2439 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2440 PPSMC_Result smc_result; 2441 int ret = 0; 2442 2443 if (ni_pi->enable_power_containment) { 2444 if (enable) { 2445 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2446 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2447 if (smc_result != PPSMC_Result_OK) { 2448 ret = -EINVAL; 2449 ni_pi->pc_enabled = false; 2450 } else { 2451 ni_pi->pc_enabled = true; 2452 } 2453 } 2454 } else { 2455 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2456 if (smc_result != PPSMC_Result_OK) 2457 ret = -EINVAL; 2458 ni_pi->pc_enabled = false; 2459 } 2460 } 2461 2462 return ret; 2463} 2464 2465static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2466{ 2467 struct si_power_info *si_pi = si_get_pi(rdev); 2468 int ret = 0; 2469 struct si_dte_data *dte_data = &si_pi->dte_data; 2470 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2471 u32 table_size; 2472 u8 tdep_count; 2473 u32 i; 2474 2475 if (dte_data == NULL) 2476 si_pi->enable_dte = false; 2477 2478 if (si_pi->enable_dte == false) 2479 return 0; 2480 2481 if (dte_data->k <= 0) 2482 return -EINVAL; 2483 2484 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2485 if (dte_tables == NULL) { 2486 si_pi->enable_dte = false; 2487 return -ENOMEM; 2488 } 2489 2490 table_size = dte_data->k; 2491 2492 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2493 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2494 2495 tdep_count = dte_data->tdep_count; 2496 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2497 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2498 2499 dte_tables->K = cpu_to_be32(table_size); 2500 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2501 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2502 dte_tables->WindowSize = dte_data->window_size; 2503 dte_tables->temp_select = dte_data->temp_select; 2504 dte_tables->DTE_mode = dte_data->dte_mode; 2505 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2506 2507 if (tdep_count > 0) 2508 table_size--; 2509 2510 for (i = 0; i < table_size; i++) { 2511 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2512 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2513 } 2514 2515 dte_tables->Tdep_count = tdep_count; 2516 2517 for (i = 0; i < (u32)tdep_count; i++) { 2518 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2519 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2520 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2521 } 2522 2523 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2524 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2525 kfree(dte_tables); 2526 2527 return ret; 2528} 2529 2530static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2531 u16 *max, u16 *min) 2532{ 2533 struct si_power_info *si_pi = si_get_pi(rdev); 2534 struct radeon_cac_leakage_table *table = 2535 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2536 u32 i; 2537 u32 v0_loadline; 2538 2539 2540 if (table == NULL) 2541 return -EINVAL; 2542 2543 *max = 0; 2544 *min = 0xFFFF; 2545 2546 for (i = 0; i < table->count; i++) { 2547 if (table->entries[i].vddc > *max) 2548 *max = table->entries[i].vddc; 2549 if (table->entries[i].vddc < *min) 2550 *min = table->entries[i].vddc; 2551 } 2552 2553 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2554 return -EINVAL; 2555 2556 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2557 2558 if (v0_loadline > 0xFFFFUL) 2559 return -EINVAL; 2560 2561 *min = (u16)v0_loadline; 2562 2563 if ((*min > *max) || (*max == 0) || (*min == 0)) 2564 return -EINVAL; 2565 2566 return 0; 2567} 2568 2569static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2570{ 2571 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2572 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2573} 2574 2575static int si_init_dte_leakage_table(struct radeon_device *rdev, 2576 PP_SIslands_CacConfig *cac_tables, 2577 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2578 u16 t0, u16 t_step) 2579{ 2580 struct si_power_info *si_pi = si_get_pi(rdev); 2581 u32 leakage; 2582 unsigned int i, j; 2583 s32 t; 2584 u32 smc_leakage; 2585 u32 scaling_factor; 2586 u16 voltage; 2587 2588 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2589 2590 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2591 t = (1000 * (i * t_step + t0)); 2592 2593 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2594 voltage = vddc_max - (vddc_step * j); 2595 2596 si_calculate_leakage_for_v_and_t(rdev, 2597 &si_pi->powertune_data->leakage_coefficients, 2598 voltage, 2599 t, 2600 si_pi->dyn_powertune_data.cac_leakage, 2601 &leakage); 2602 2603 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2604 2605 if (smc_leakage > 0xFFFF) 2606 smc_leakage = 0xFFFF; 2607 2608 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2609 cpu_to_be16((u16)smc_leakage); 2610 } 2611 } 2612 return 0; 2613} 2614 2615static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2616 PP_SIslands_CacConfig *cac_tables, 2617 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2618{ 2619 struct si_power_info *si_pi = si_get_pi(rdev); 2620 u32 leakage; 2621 unsigned int i, j; 2622 u32 smc_leakage; 2623 u32 scaling_factor; 2624 u16 voltage; 2625 2626 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2627 2628 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2629 voltage = vddc_max - (vddc_step * j); 2630 2631 si_calculate_leakage_for_v(rdev, 2632 &si_pi->powertune_data->leakage_coefficients, 2633 si_pi->powertune_data->fixed_kt, 2634 voltage, 2635 si_pi->dyn_powertune_data.cac_leakage, 2636 &leakage); 2637 2638 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2639 2640 if (smc_leakage > 0xFFFF) 2641 smc_leakage = 0xFFFF; 2642 2643 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2644 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2645 cpu_to_be16((u16)smc_leakage); 2646 } 2647 return 0; 2648} 2649 2650static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2651{ 2652 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2653 struct si_power_info *si_pi = si_get_pi(rdev); 2654 PP_SIslands_CacConfig *cac_tables = NULL; 2655 u16 vddc_max, vddc_min, vddc_step; 2656 u16 t0, t_step; 2657 u32 load_line_slope, reg; 2658 int ret = 0; 2659 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2660 2661 if (ni_pi->enable_cac == false) 2662 return 0; 2663 2664 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2665 if (!cac_tables) 2666 return -ENOMEM; 2667 2668 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2669 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2670 WREG32(CG_CAC_CTRL, reg); 2671 2672 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2673 si_pi->dyn_powertune_data.dc_pwr_value = 2674 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2675 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2676 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2677 2678 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2679 2680 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2681 if (ret) 2682 goto done_free; 2683 2684 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2685 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2686 t_step = 4; 2687 t0 = 60; 2688 2689 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2690 ret = si_init_dte_leakage_table(rdev, cac_tables, 2691 vddc_max, vddc_min, vddc_step, 2692 t0, t_step); 2693 else 2694 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2695 vddc_max, vddc_min, vddc_step); 2696 if (ret) 2697 goto done_free; 2698 2699 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2700 2701 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2702 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2703 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2704 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2705 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2706 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2707 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2708 cac_tables->calculation_repeats = cpu_to_be32(2); 2709 cac_tables->dc_cac = cpu_to_be32(0); 2710 cac_tables->log2_PG_LKG_SCALE = 12; 2711 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2712 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2713 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2714 2715 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2716 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2717 2718 if (ret) 2719 goto done_free; 2720 2721 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2722 2723done_free: 2724 if (ret) { 2725 ni_pi->enable_cac = false; 2726 ni_pi->enable_power_containment = false; 2727 } 2728 2729 kfree(cac_tables); 2730 2731 return 0; 2732} 2733 2734static int si_program_cac_config_registers(struct radeon_device *rdev, 2735 const struct si_cac_config_reg *cac_config_regs) 2736{ 2737 const struct si_cac_config_reg *config_regs = cac_config_regs; 2738 u32 data = 0, offset; 2739 2740 if (!config_regs) 2741 return -EINVAL; 2742 2743 while (config_regs->offset != 0xFFFFFFFF) { 2744 switch (config_regs->type) { 2745 case SISLANDS_CACCONFIG_CGIND: 2746 offset = SMC_CG_IND_START + config_regs->offset; 2747 if (offset < SMC_CG_IND_END) 2748 data = RREG32_SMC(offset); 2749 break; 2750 default: 2751 data = RREG32(config_regs->offset << 2); 2752 break; 2753 } 2754 2755 data &= ~config_regs->mask; 2756 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2757 2758 switch (config_regs->type) { 2759 case SISLANDS_CACCONFIG_CGIND: 2760 offset = SMC_CG_IND_START + config_regs->offset; 2761 if (offset < SMC_CG_IND_END) 2762 WREG32_SMC(offset, data); 2763 break; 2764 default: 2765 WREG32(config_regs->offset << 2, data); 2766 break; 2767 } 2768 config_regs++; 2769 } 2770 return 0; 2771} 2772 2773static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2774{ 2775 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2776 struct si_power_info *si_pi = si_get_pi(rdev); 2777 int ret; 2778 2779 if ((ni_pi->enable_cac == false) || 2780 (ni_pi->cac_configuration_required == false)) 2781 return 0; 2782 2783 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2784 if (ret) 2785 return ret; 2786 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2787 if (ret) 2788 return ret; 2789 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2790 if (ret) 2791 return ret; 2792 2793 return 0; 2794} 2795 2796static int si_enable_smc_cac(struct radeon_device *rdev, 2797 struct radeon_ps *radeon_new_state, 2798 bool enable) 2799{ 2800 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2801 struct si_power_info *si_pi = si_get_pi(rdev); 2802 PPSMC_Result smc_result; 2803 int ret = 0; 2804 2805 if (ni_pi->enable_cac) { 2806 if (enable) { 2807 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2808 if (ni_pi->support_cac_long_term_average) { 2809 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2810 if (smc_result != PPSMC_Result_OK) 2811 ni_pi->support_cac_long_term_average = false; 2812 } 2813 2814 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2815 if (smc_result != PPSMC_Result_OK) { 2816 ret = -EINVAL; 2817 ni_pi->cac_enabled = false; 2818 } else { 2819 ni_pi->cac_enabled = true; 2820 } 2821 2822 if (si_pi->enable_dte) { 2823 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2824 if (smc_result != PPSMC_Result_OK) 2825 ret = -EINVAL; 2826 } 2827 } 2828 } else if (ni_pi->cac_enabled) { 2829 if (si_pi->enable_dte) 2830 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2831 2832 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2833 2834 ni_pi->cac_enabled = false; 2835 2836 if (ni_pi->support_cac_long_term_average) 2837 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2838 } 2839 } 2840 return ret; 2841} 2842 2843static int si_init_smc_spll_table(struct radeon_device *rdev) 2844{ 2845 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2846 struct si_power_info *si_pi = si_get_pi(rdev); 2847 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2848 SISLANDS_SMC_SCLK_VALUE sclk_params; 2849 u32 fb_div, p_div; 2850 u32 clk_s, clk_v; 2851 u32 sclk = 0; 2852 int ret = 0; 2853 u32 tmp; 2854 int i; 2855 2856 if (si_pi->spll_table_start == 0) 2857 return -EINVAL; 2858 2859 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2860 if (spll_table == NULL) 2861 return -ENOMEM; 2862 2863 for (i = 0; i < 256; i++) { 2864 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2865 if (ret) 2866 break; 2867 2868 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2869 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2870 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2871 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2872 2873 fb_div &= ~0x00001FFF; 2874 fb_div >>= 1; 2875 clk_v >>= 6; 2876 2877 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2878 ret = -EINVAL; 2879 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2880 ret = -EINVAL; 2881 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2882 ret = -EINVAL; 2883 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2884 ret = -EINVAL; 2885 2886 if (ret) 2887 break; 2888 2889 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2890 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2891 spll_table->freq[i] = cpu_to_be32(tmp); 2892 2893 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2894 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2895 spll_table->ss[i] = cpu_to_be32(tmp); 2896 2897 sclk += 512; 2898 } 2899 2900 2901 if (!ret) 2902 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2903 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2904 si_pi->sram_end); 2905 2906 if (ret) 2907 ni_pi->enable_power_containment = false; 2908 2909 kfree(spll_table); 2910 2911 return ret; 2912} 2913 2914struct si_dpm_quirk { 2915 u32 chip_vendor; 2916 u32 chip_device; 2917 u32 subsys_vendor; 2918 u32 subsys_device; 2919 u32 max_sclk; 2920 u32 max_mclk; 2921}; 2922 2923/* cards with dpm stability problems */ 2924static struct si_dpm_quirk si_dpm_quirk_list[] = { 2925 /* PITCAIRN - https://bugs.freedesktop.org/show_bug.cgi?id=76490 */ 2926 { PCI_VENDOR_ID_ATI, 0x6810, 0x1462, 0x3036, 0, 120000 }, 2927 { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, 2928 { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, 2929 { PCI_VENDOR_ID_ATI, 0x6811, 0x1762, 0x2015, 0, 120000 }, 2930 { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, 2931 { PCI_VENDOR_ID_ATI, 0x6811, 0x148c, 0x2015, 0, 120000 }, 2932 { PCI_VENDOR_ID_ATI, 0x6810, 0x1682, 0x9275, 0, 120000 }, 2933 { 0, 0, 0, 0 }, 2934}; 2935 2936static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2937 struct radeon_ps *rps) 2938{ 2939 struct ni_ps *ps = ni_get_ps(rps); 2940 struct radeon_clock_and_voltage_limits *max_limits; 2941 bool disable_mclk_switching = false; 2942 bool disable_sclk_switching = false; 2943 u32 mclk, sclk; 2944 u16 vddc, vddci; 2945 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2946 u32 max_sclk = 0, max_mclk = 0; 2947 int i; 2948 struct si_dpm_quirk *p = si_dpm_quirk_list; 2949 2950 /* Apply dpm quirks */ 2951 while (p && p->chip_device != 0) { 2952 if (rdev->pdev->vendor == p->chip_vendor && 2953 rdev->pdev->device == p->chip_device && 2954 rdev->pdev->subsystem_vendor == p->subsys_vendor && 2955 rdev->pdev->subsystem_device == p->subsys_device) { 2956 max_sclk = p->max_sclk; 2957 max_mclk = p->max_mclk; 2958 break; 2959 } 2960 ++p; 2961 } 2962 2963 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 2964 ni_dpm_vblank_too_short(rdev)) 2965 disable_mclk_switching = true; 2966 2967 if (rps->vclk || rps->dclk) { 2968 disable_mclk_switching = true; 2969 disable_sclk_switching = true; 2970 } 2971 2972 if (rdev->pm.dpm.ac_power) 2973 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 2974 else 2975 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 2976 2977 for (i = ps->performance_level_count - 2; i >= 0; i--) { 2978 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 2979 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 2980 } 2981 if (rdev->pm.dpm.ac_power == false) { 2982 for (i = 0; i < ps->performance_level_count; i++) { 2983 if (ps->performance_levels[i].mclk > max_limits->mclk) 2984 ps->performance_levels[i].mclk = max_limits->mclk; 2985 if (ps->performance_levels[i].sclk > max_limits->sclk) 2986 ps->performance_levels[i].sclk = max_limits->sclk; 2987 if (ps->performance_levels[i].vddc > max_limits->vddc) 2988 ps->performance_levels[i].vddc = max_limits->vddc; 2989 if (ps->performance_levels[i].vddci > max_limits->vddci) 2990 ps->performance_levels[i].vddci = max_limits->vddci; 2991 } 2992 } 2993 2994 /* limit clocks to max supported clocks based on voltage dependency tables */ 2995 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 2996 &max_sclk_vddc); 2997 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 2998 &max_mclk_vddci); 2999 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3000 &max_mclk_vddc); 3001 3002 for (i = 0; i < ps->performance_level_count; i++) { 3003 if (max_sclk_vddc) { 3004 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3005 ps->performance_levels[i].sclk = max_sclk_vddc; 3006 } 3007 if (max_mclk_vddci) { 3008 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3009 ps->performance_levels[i].mclk = max_mclk_vddci; 3010 } 3011 if (max_mclk_vddc) { 3012 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3013 ps->performance_levels[i].mclk = max_mclk_vddc; 3014 } 3015 if (max_mclk) { 3016 if (ps->performance_levels[i].mclk > max_mclk) 3017 ps->performance_levels[i].mclk = max_mclk; 3018 } 3019 if (max_sclk) { 3020 if (ps->performance_levels[i].sclk > max_sclk) 3021 ps->performance_levels[i].sclk = max_sclk; 3022 } 3023 } 3024 3025 /* XXX validate the min clocks required for display */ 3026 3027 if (disable_mclk_switching) { 3028 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3029 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3030 } else { 3031 mclk = ps->performance_levels[0].mclk; 3032 vddci = ps->performance_levels[0].vddci; 3033 } 3034 3035 if (disable_sclk_switching) { 3036 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3037 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3038 } else { 3039 sclk = ps->performance_levels[0].sclk; 3040 vddc = ps->performance_levels[0].vddc; 3041 } 3042 3043 /* adjusted low state */ 3044 ps->performance_levels[0].sclk = sclk; 3045 ps->performance_levels[0].mclk = mclk; 3046 ps->performance_levels[0].vddc = vddc; 3047 ps->performance_levels[0].vddci = vddci; 3048 3049 if (disable_sclk_switching) { 3050 sclk = ps->performance_levels[0].sclk; 3051 for (i = 1; i < ps->performance_level_count; i++) { 3052 if (sclk < ps->performance_levels[i].sclk) 3053 sclk = ps->performance_levels[i].sclk; 3054 } 3055 for (i = 0; i < ps->performance_level_count; i++) { 3056 ps->performance_levels[i].sclk = sclk; 3057 ps->performance_levels[i].vddc = vddc; 3058 } 3059 } else { 3060 for (i = 1; i < ps->performance_level_count; i++) { 3061 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3062 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3063 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3064 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3065 } 3066 } 3067 3068 if (disable_mclk_switching) { 3069 mclk = ps->performance_levels[0].mclk; 3070 for (i = 1; i < ps->performance_level_count; i++) { 3071 if (mclk < ps->performance_levels[i].mclk) 3072 mclk = ps->performance_levels[i].mclk; 3073 } 3074 for (i = 0; i < ps->performance_level_count; i++) { 3075 ps->performance_levels[i].mclk = mclk; 3076 ps->performance_levels[i].vddci = vddci; 3077 } 3078 } else { 3079 for (i = 1; i < ps->performance_level_count; i++) { 3080 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3081 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3082 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3083 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3084 } 3085 } 3086 3087 for (i = 0; i < ps->performance_level_count; i++) 3088 btc_adjust_clock_combinations(rdev, max_limits, 3089 &ps->performance_levels[i]); 3090 3091 for (i = 0; i < ps->performance_level_count; i++) { 3092 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3093 ps->performance_levels[i].sclk, 3094 max_limits->vddc, &ps->performance_levels[i].vddc); 3095 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3096 ps->performance_levels[i].mclk, 3097 max_limits->vddci, &ps->performance_levels[i].vddci); 3098 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3099 ps->performance_levels[i].mclk, 3100 max_limits->vddc, &ps->performance_levels[i].vddc); 3101 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3102 rdev->clock.current_dispclk, 3103 max_limits->vddc, &ps->performance_levels[i].vddc); 3104 } 3105 3106 for (i = 0; i < ps->performance_level_count; i++) { 3107 btc_apply_voltage_delta_rules(rdev, 3108 max_limits->vddc, max_limits->vddci, 3109 &ps->performance_levels[i].vddc, 3110 &ps->performance_levels[i].vddci); 3111 } 3112 3113 ps->dc_compatible = true; 3114 for (i = 0; i < ps->performance_level_count; i++) { 3115 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3116 ps->dc_compatible = false; 3117 } 3118 3119} 3120 3121#if 0 3122static int si_read_smc_soft_register(struct radeon_device *rdev, 3123 u16 reg_offset, u32 *value) 3124{ 3125 struct si_power_info *si_pi = si_get_pi(rdev); 3126 3127 return si_read_smc_sram_dword(rdev, 3128 si_pi->soft_regs_start + reg_offset, value, 3129 si_pi->sram_end); 3130} 3131#endif 3132 3133static int si_write_smc_soft_register(struct radeon_device *rdev, 3134 u16 reg_offset, u32 value) 3135{ 3136 struct si_power_info *si_pi = si_get_pi(rdev); 3137 3138 return si_write_smc_sram_dword(rdev, 3139 si_pi->soft_regs_start + reg_offset, 3140 value, si_pi->sram_end); 3141} 3142 3143static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3144{ 3145 bool ret = false; 3146 u32 tmp, width, row, column, bank, density; 3147 bool is_memory_gddr5, is_special; 3148 3149 tmp = RREG32(MC_SEQ_MISC0); 3150 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3151 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3152 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3153 3154 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3155 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3156 3157 tmp = RREG32(MC_ARB_RAMCFG); 3158 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3159 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3160 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3161 3162 density = (1 << (row + column - 20 + bank)) * width; 3163 3164 if ((rdev->pdev->device == 0x6819) && 3165 is_memory_gddr5 && is_special && (density == 0x400)) 3166 ret = true; 3167 3168 return ret; 3169} 3170 3171static void si_get_leakage_vddc(struct radeon_device *rdev) 3172{ 3173 struct si_power_info *si_pi = si_get_pi(rdev); 3174 u16 vddc, count = 0; 3175 int i, ret; 3176 3177 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3178 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3179 3180 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3181 si_pi->leakage_voltage.entries[count].voltage = vddc; 3182 si_pi->leakage_voltage.entries[count].leakage_index = 3183 SISLANDS_LEAKAGE_INDEX0 + i; 3184 count++; 3185 } 3186 } 3187 si_pi->leakage_voltage.count = count; 3188} 3189 3190static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3191 u32 index, u16 *leakage_voltage) 3192{ 3193 struct si_power_info *si_pi = si_get_pi(rdev); 3194 int i; 3195 3196 if (leakage_voltage == NULL) 3197 return -EINVAL; 3198 3199 if ((index & 0xff00) != 0xff00) 3200 return -EINVAL; 3201 3202 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3203 return -EINVAL; 3204 3205 if (index < SISLANDS_LEAKAGE_INDEX0) 3206 return -EINVAL; 3207 3208 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3209 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3210 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3211 return 0; 3212 } 3213 } 3214 return -EAGAIN; 3215} 3216 3217static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3218{ 3219 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3220 bool want_thermal_protection; 3221 enum radeon_dpm_event_src dpm_event_src; 3222 3223 switch (sources) { 3224 case 0: 3225 default: 3226 want_thermal_protection = false; 3227 break; 3228 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3229 want_thermal_protection = true; 3230 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3231 break; 3232 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3233 want_thermal_protection = true; 3234 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3235 break; 3236 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3237 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3238 want_thermal_protection = true; 3239 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3240 break; 3241 } 3242 3243 if (want_thermal_protection) { 3244 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3245 if (pi->thermal_protection) 3246 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3247 } else { 3248 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3249 } 3250} 3251 3252static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3253 enum radeon_dpm_auto_throttle_src source, 3254 bool enable) 3255{ 3256 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3257 3258 if (enable) { 3259 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3260 pi->active_auto_throttle_sources |= 1 << source; 3261 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3262 } 3263 } else { 3264 if (pi->active_auto_throttle_sources & (1 << source)) { 3265 pi->active_auto_throttle_sources &= ~(1 << source); 3266 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3267 } 3268 } 3269} 3270 3271static void si_start_dpm(struct radeon_device *rdev) 3272{ 3273 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3274} 3275 3276static void si_stop_dpm(struct radeon_device *rdev) 3277{ 3278 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3279} 3280 3281static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3282{ 3283 if (enable) 3284 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3285 else 3286 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3287 3288} 3289 3290#if 0 3291static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3292 u32 thermal_level) 3293{ 3294 PPSMC_Result ret; 3295 3296 if (thermal_level == 0) { 3297 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3298 if (ret == PPSMC_Result_OK) 3299 return 0; 3300 else 3301 return -EINVAL; 3302 } 3303 return 0; 3304} 3305 3306static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3307{ 3308 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3309} 3310#endif 3311 3312#if 0 3313static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3314{ 3315 if (ac_power) 3316 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3317 0 : -EINVAL; 3318 3319 return 0; 3320} 3321#endif 3322 3323static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3324 PPSMC_Msg msg, u32 parameter) 3325{ 3326 WREG32(SMC_SCRATCH0, parameter); 3327 return si_send_msg_to_smc(rdev, msg); 3328} 3329 3330static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3331{ 3332 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3333 return -EINVAL; 3334 3335 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3336 0 : -EINVAL; 3337} 3338 3339int si_dpm_force_performance_level(struct radeon_device *rdev, 3340 enum radeon_dpm_forced_level level) 3341{ 3342 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3343 struct ni_ps *ps = ni_get_ps(rps); 3344 u32 levels = ps->performance_level_count; 3345 3346 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3347 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3348 return -EINVAL; 3349 3350 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3351 return -EINVAL; 3352 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3353 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3354 return -EINVAL; 3355 3356 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3357 return -EINVAL; 3358 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3359 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3360 return -EINVAL; 3361 3362 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3363 return -EINVAL; 3364 } 3365 3366 rdev->pm.dpm.forced_level = level; 3367 3368 return 0; 3369} 3370 3371#if 0 3372static int si_set_boot_state(struct radeon_device *rdev) 3373{ 3374 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3375 0 : -EINVAL; 3376} 3377#endif 3378 3379static int si_set_sw_state(struct radeon_device *rdev) 3380{ 3381 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3382 0 : -EINVAL; 3383} 3384 3385static int si_halt_smc(struct radeon_device *rdev) 3386{ 3387 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3388 return -EINVAL; 3389 3390 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3391 0 : -EINVAL; 3392} 3393 3394static int si_resume_smc(struct radeon_device *rdev) 3395{ 3396 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3397 return -EINVAL; 3398 3399 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3400 0 : -EINVAL; 3401} 3402 3403static void si_dpm_start_smc(struct radeon_device *rdev) 3404{ 3405 si_program_jump_on_start(rdev); 3406 si_start_smc(rdev); 3407 si_start_smc_clock(rdev); 3408} 3409 3410static void si_dpm_stop_smc(struct radeon_device *rdev) 3411{ 3412 si_reset_smc(rdev); 3413 si_stop_smc_clock(rdev); 3414} 3415 3416static int si_process_firmware_header(struct radeon_device *rdev) 3417{ 3418 struct si_power_info *si_pi = si_get_pi(rdev); 3419 u32 tmp; 3420 int ret; 3421 3422 ret = si_read_smc_sram_dword(rdev, 3423 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3424 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3425 &tmp, si_pi->sram_end); 3426 if (ret) 3427 return ret; 3428 3429 si_pi->state_table_start = tmp; 3430 3431 ret = si_read_smc_sram_dword(rdev, 3432 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3433 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3434 &tmp, si_pi->sram_end); 3435 if (ret) 3436 return ret; 3437 3438 si_pi->soft_regs_start = tmp; 3439 3440 ret = si_read_smc_sram_dword(rdev, 3441 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3442 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3443 &tmp, si_pi->sram_end); 3444 if (ret) 3445 return ret; 3446 3447 si_pi->mc_reg_table_start = tmp; 3448 3449 ret = si_read_smc_sram_dword(rdev, 3450 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3451 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3452 &tmp, si_pi->sram_end); 3453 if (ret) 3454 return ret; 3455 3456 si_pi->fan_table_start = tmp; 3457 3458 ret = si_read_smc_sram_dword(rdev, 3459 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3460 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3461 &tmp, si_pi->sram_end); 3462 if (ret) 3463 return ret; 3464 3465 si_pi->arb_table_start = tmp; 3466 3467 ret = si_read_smc_sram_dword(rdev, 3468 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3469 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3470 &tmp, si_pi->sram_end); 3471 if (ret) 3472 return ret; 3473 3474 si_pi->cac_table_start = tmp; 3475 3476 ret = si_read_smc_sram_dword(rdev, 3477 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3478 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3479 &tmp, si_pi->sram_end); 3480 if (ret) 3481 return ret; 3482 3483 si_pi->dte_table_start = tmp; 3484 3485 ret = si_read_smc_sram_dword(rdev, 3486 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3487 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3488 &tmp, si_pi->sram_end); 3489 if (ret) 3490 return ret; 3491 3492 si_pi->spll_table_start = tmp; 3493 3494 ret = si_read_smc_sram_dword(rdev, 3495 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3496 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3497 &tmp, si_pi->sram_end); 3498 if (ret) 3499 return ret; 3500 3501 si_pi->papm_cfg_table_start = tmp; 3502 3503 return ret; 3504} 3505 3506static void si_read_clock_registers(struct radeon_device *rdev) 3507{ 3508 struct si_power_info *si_pi = si_get_pi(rdev); 3509 3510 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3511 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3512 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3513 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3514 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3515 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3516 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3517 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3518 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3519 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3520 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3521 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3522 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3523 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3524 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3525} 3526 3527static void si_enable_thermal_protection(struct radeon_device *rdev, 3528 bool enable) 3529{ 3530 if (enable) 3531 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3532 else 3533 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3534} 3535 3536static void si_enable_acpi_power_management(struct radeon_device *rdev) 3537{ 3538 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3539} 3540 3541#if 0 3542static int si_enter_ulp_state(struct radeon_device *rdev) 3543{ 3544 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3545 3546 udelay(25000); 3547 3548 return 0; 3549} 3550 3551static int si_exit_ulp_state(struct radeon_device *rdev) 3552{ 3553 int i; 3554 3555 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3556 3557 udelay(7000); 3558 3559 for (i = 0; i < rdev->usec_timeout; i++) { 3560 if (RREG32(SMC_RESP_0) == 1) 3561 break; 3562 udelay(1000); 3563 } 3564 3565 return 0; 3566} 3567#endif 3568 3569static int si_notify_smc_display_change(struct radeon_device *rdev, 3570 bool has_display) 3571{ 3572 PPSMC_Msg msg = has_display ? 3573 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3574 3575 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3576 0 : -EINVAL; 3577} 3578 3579static void si_program_response_times(struct radeon_device *rdev) 3580{ 3581 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out; 3582 u32 vddc_dly, acpi_dly, vbi_dly; 3583 u32 reference_clock; 3584 3585 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3586 3587 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3588 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time; 3589 3590 if (voltage_response_time == 0) 3591 voltage_response_time = 1000; 3592 3593 acpi_delay_time = 15000; 3594 vbi_time_out = 100000; 3595 3596 reference_clock = radeon_get_xclk(rdev); 3597 3598 vddc_dly = (voltage_response_time * reference_clock) / 100; 3599 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3600 vbi_dly = (vbi_time_out * reference_clock) / 100; 3601 3602 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3603 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3604 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3605 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3606} 3607 3608static void si_program_ds_registers(struct radeon_device *rdev) 3609{ 3610 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3611 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3612 3613 if (eg_pi->sclk_deep_sleep) { 3614 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3615 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3616 ~AUTOSCALE_ON_SS_CLEAR); 3617 } 3618} 3619 3620static void si_program_display_gap(struct radeon_device *rdev) 3621{ 3622 u32 tmp, pipe; 3623 int i; 3624 3625 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3626 if (rdev->pm.dpm.new_active_crtc_count > 0) 3627 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3628 else 3629 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3630 3631 if (rdev->pm.dpm.new_active_crtc_count > 1) 3632 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3633 else 3634 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3635 3636 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3637 3638 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3639 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3640 3641 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3642 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3643 /* find the first active crtc */ 3644 for (i = 0; i < rdev->num_crtc; i++) { 3645 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3646 break; 3647 } 3648 if (i == rdev->num_crtc) 3649 pipe = 0; 3650 else 3651 pipe = i; 3652 3653 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3654 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3655 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3656 } 3657 3658 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3659 * This can be a problem on PowerXpress systems or if you want to use the card 3660 * for offscreen rendering or compute if there are no crtcs enabled. 3661 */ 3662 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3663} 3664 3665static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3666{ 3667 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3668 3669 if (enable) { 3670 if (pi->sclk_ss) 3671 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3672 } else { 3673 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3674 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3675 } 3676} 3677 3678static void si_setup_bsp(struct radeon_device *rdev) 3679{ 3680 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3681 u32 xclk = radeon_get_xclk(rdev); 3682 3683 r600_calculate_u_and_p(pi->asi, 3684 xclk, 3685 16, 3686 &pi->bsp, 3687 &pi->bsu); 3688 3689 r600_calculate_u_and_p(pi->pasi, 3690 xclk, 3691 16, 3692 &pi->pbsp, 3693 &pi->pbsu); 3694 3695 3696 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3697 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3698 3699 WREG32(CG_BSP, pi->dsp); 3700} 3701 3702static void si_program_git(struct radeon_device *rdev) 3703{ 3704 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3705} 3706 3707static void si_program_tp(struct radeon_device *rdev) 3708{ 3709 int i; 3710 enum r600_td td = R600_TD_DFLT; 3711 3712 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3713 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3714 3715 if (td == R600_TD_AUTO) 3716 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3717 else 3718 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3719 3720 if (td == R600_TD_UP) 3721 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3722 3723 if (td == R600_TD_DOWN) 3724 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3725} 3726 3727static void si_program_tpp(struct radeon_device *rdev) 3728{ 3729 WREG32(CG_TPC, R600_TPC_DFLT); 3730} 3731 3732static void si_program_sstp(struct radeon_device *rdev) 3733{ 3734 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3735} 3736 3737static void si_enable_display_gap(struct radeon_device *rdev) 3738{ 3739 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3740 3741 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3742 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3743 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3744 3745 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3746 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3747 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3748 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3749} 3750 3751static void si_program_vc(struct radeon_device *rdev) 3752{ 3753 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3754 3755 WREG32(CG_FTV, pi->vrc); 3756} 3757 3758static void si_clear_vc(struct radeon_device *rdev) 3759{ 3760 WREG32(CG_FTV, 0); 3761} 3762 3763u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3764{ 3765 u8 mc_para_index; 3766 3767 if (memory_clock < 10000) 3768 mc_para_index = 0; 3769 else if (memory_clock >= 80000) 3770 mc_para_index = 0x0f; 3771 else 3772 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3773 return mc_para_index; 3774} 3775 3776u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3777{ 3778 u8 mc_para_index; 3779 3780 if (strobe_mode) { 3781 if (memory_clock < 12500) 3782 mc_para_index = 0x00; 3783 else if (memory_clock > 47500) 3784 mc_para_index = 0x0f; 3785 else 3786 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3787 } else { 3788 if (memory_clock < 65000) 3789 mc_para_index = 0x00; 3790 else if (memory_clock > 135000) 3791 mc_para_index = 0x0f; 3792 else 3793 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3794 } 3795 return mc_para_index; 3796} 3797 3798static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3799{ 3800 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3801 bool strobe_mode = false; 3802 u8 result = 0; 3803 3804 if (mclk <= pi->mclk_strobe_mode_threshold) 3805 strobe_mode = true; 3806 3807 if (pi->mem_gddr5) 3808 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3809 else 3810 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3811 3812 if (strobe_mode) 3813 result |= SISLANDS_SMC_STROBE_ENABLE; 3814 3815 return result; 3816} 3817 3818static int si_upload_firmware(struct radeon_device *rdev) 3819{ 3820 struct si_power_info *si_pi = si_get_pi(rdev); 3821 int ret; 3822 3823 si_reset_smc(rdev); 3824 si_stop_smc_clock(rdev); 3825 3826 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3827 3828 return ret; 3829} 3830 3831static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3832 const struct atom_voltage_table *table, 3833 const struct radeon_phase_shedding_limits_table *limits) 3834{ 3835 u32 data, num_bits, num_levels; 3836 3837 if ((table == NULL) || (limits == NULL)) 3838 return false; 3839 3840 data = table->mask_low; 3841 3842 num_bits = hweight32(data); 3843 3844 if (num_bits == 0) 3845 return false; 3846 3847 num_levels = (1 << num_bits); 3848 3849 if (table->count != num_levels) 3850 return false; 3851 3852 if (limits->count != (num_levels - 1)) 3853 return false; 3854 3855 return true; 3856} 3857 3858void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3859 u32 max_voltage_steps, 3860 struct atom_voltage_table *voltage_table) 3861{ 3862 unsigned int i, diff; 3863 3864 if (voltage_table->count <= max_voltage_steps) 3865 return; 3866 3867 diff = voltage_table->count - max_voltage_steps; 3868 3869 for (i= 0; i < max_voltage_steps; i++) 3870 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3871 3872 voltage_table->count = max_voltage_steps; 3873} 3874 3875static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3876 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3877 struct atom_voltage_table *voltage_table) 3878{ 3879 u32 i; 3880 3881 if (voltage_dependency_table == NULL) 3882 return -EINVAL; 3883 3884 voltage_table->mask_low = 0; 3885 voltage_table->phase_delay = 0; 3886 3887 voltage_table->count = voltage_dependency_table->count; 3888 for (i = 0; i < voltage_table->count; i++) { 3889 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3890 voltage_table->entries[i].smio_low = 0; 3891 } 3892 3893 return 0; 3894} 3895 3896static int si_construct_voltage_tables(struct radeon_device *rdev) 3897{ 3898 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3899 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3900 struct si_power_info *si_pi = si_get_pi(rdev); 3901 int ret; 3902 3903 if (pi->voltage_control) { 3904 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3905 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3906 if (ret) 3907 return ret; 3908 3909 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3910 si_trim_voltage_table_to_fit_state_table(rdev, 3911 SISLANDS_MAX_NO_VREG_STEPS, 3912 &eg_pi->vddc_voltage_table); 3913 } else if (si_pi->voltage_control_svi2) { 3914 ret = si_get_svi2_voltage_table(rdev, 3915 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3916 &eg_pi->vddc_voltage_table); 3917 if (ret) 3918 return ret; 3919 } else { 3920 return -EINVAL; 3921 } 3922 3923 if (eg_pi->vddci_control) { 3924 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3925 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3926 if (ret) 3927 return ret; 3928 3929 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3930 si_trim_voltage_table_to_fit_state_table(rdev, 3931 SISLANDS_MAX_NO_VREG_STEPS, 3932 &eg_pi->vddci_voltage_table); 3933 } 3934 if (si_pi->vddci_control_svi2) { 3935 ret = si_get_svi2_voltage_table(rdev, 3936 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3937 &eg_pi->vddci_voltage_table); 3938 if (ret) 3939 return ret; 3940 } 3941 3942 if (pi->mvdd_control) { 3943 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3944 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3945 3946 if (ret) { 3947 pi->mvdd_control = false; 3948 return ret; 3949 } 3950 3951 if (si_pi->mvdd_voltage_table.count == 0) { 3952 pi->mvdd_control = false; 3953 return -EINVAL; 3954 } 3955 3956 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3957 si_trim_voltage_table_to_fit_state_table(rdev, 3958 SISLANDS_MAX_NO_VREG_STEPS, 3959 &si_pi->mvdd_voltage_table); 3960 } 3961 3962 if (si_pi->vddc_phase_shed_control) { 3963 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3964 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 3965 if (ret) 3966 si_pi->vddc_phase_shed_control = false; 3967 3968 if ((si_pi->vddc_phase_shed_table.count == 0) || 3969 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 3970 si_pi->vddc_phase_shed_control = false; 3971 } 3972 3973 return 0; 3974} 3975 3976static void si_populate_smc_voltage_table(struct radeon_device *rdev, 3977 const struct atom_voltage_table *voltage_table, 3978 SISLANDS_SMC_STATETABLE *table) 3979{ 3980 unsigned int i; 3981 3982 for (i = 0; i < voltage_table->count; i++) 3983 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 3984} 3985 3986static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 3987 SISLANDS_SMC_STATETABLE *table) 3988{ 3989 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3990 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3991 struct si_power_info *si_pi = si_get_pi(rdev); 3992 u8 i; 3993 3994 if (si_pi->voltage_control_svi2) { 3995 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 3996 si_pi->svc_gpio_id); 3997 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 3998 si_pi->svd_gpio_id); 3999 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4000 2); 4001 } else { 4002 if (eg_pi->vddc_voltage_table.count) { 4003 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4004 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4005 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4006 4007 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4008 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4009 table->maxVDDCIndexInPPTable = i; 4010 break; 4011 } 4012 } 4013 } 4014 4015 if (eg_pi->vddci_voltage_table.count) { 4016 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4017 4018 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4019 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4020 } 4021 4022 4023 if (si_pi->mvdd_voltage_table.count) { 4024 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4025 4026 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4027 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4028 } 4029 4030 if (si_pi->vddc_phase_shed_control) { 4031 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4032 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4033 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4034 4035 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4036 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4037 4038 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4039 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4040 } else { 4041 si_pi->vddc_phase_shed_control = false; 4042 } 4043 } 4044 } 4045 4046 return 0; 4047} 4048 4049static int si_populate_voltage_value(struct radeon_device *rdev, 4050 const struct atom_voltage_table *table, 4051 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4052{ 4053 unsigned int i; 4054 4055 for (i = 0; i < table->count; i++) { 4056 if (value <= table->entries[i].value) { 4057 voltage->index = (u8)i; 4058 voltage->value = cpu_to_be16(table->entries[i].value); 4059 break; 4060 } 4061 } 4062 4063 if (i >= table->count) 4064 return -EINVAL; 4065 4066 return 0; 4067} 4068 4069static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4070 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4071{ 4072 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4073 struct si_power_info *si_pi = si_get_pi(rdev); 4074 4075 if (pi->mvdd_control) { 4076 if (mclk <= pi->mvdd_split_frequency) 4077 voltage->index = 0; 4078 else 4079 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4080 4081 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4082 } 4083 return 0; 4084} 4085 4086static int si_get_std_voltage_value(struct radeon_device *rdev, 4087 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4088 u16 *std_voltage) 4089{ 4090 u16 v_index; 4091 bool voltage_found = false; 4092 *std_voltage = be16_to_cpu(voltage->value); 4093 4094 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4095 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4096 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4097 return -EINVAL; 4098 4099 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4100 if (be16_to_cpu(voltage->value) == 4101 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4102 voltage_found = true; 4103 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4104 *std_voltage = 4105 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4106 else 4107 *std_voltage = 4108 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4109 break; 4110 } 4111 } 4112 4113 if (!voltage_found) { 4114 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4115 if (be16_to_cpu(voltage->value) <= 4116 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4117 voltage_found = true; 4118 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4119 *std_voltage = 4120 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4121 else 4122 *std_voltage = 4123 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4124 break; 4125 } 4126 } 4127 } 4128 } else { 4129 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4130 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4131 } 4132 } 4133 4134 return 0; 4135} 4136 4137static int si_populate_std_voltage_value(struct radeon_device *rdev, 4138 u16 value, u8 index, 4139 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4140{ 4141 voltage->index = index; 4142 voltage->value = cpu_to_be16(value); 4143 4144 return 0; 4145} 4146 4147static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4148 const struct radeon_phase_shedding_limits_table *limits, 4149 u16 voltage, u32 sclk, u32 mclk, 4150 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4151{ 4152 unsigned int i; 4153 4154 for (i = 0; i < limits->count; i++) { 4155 if ((voltage <= limits->entries[i].voltage) && 4156 (sclk <= limits->entries[i].sclk) && 4157 (mclk <= limits->entries[i].mclk)) 4158 break; 4159 } 4160 4161 smc_voltage->phase_settings = (u8)i; 4162 4163 return 0; 4164} 4165 4166static int si_init_arb_table_index(struct radeon_device *rdev) 4167{ 4168 struct si_power_info *si_pi = si_get_pi(rdev); 4169 u32 tmp; 4170 int ret; 4171 4172 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4173 if (ret) 4174 return ret; 4175 4176 tmp &= 0x00FFFFFF; 4177 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4178 4179 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4180} 4181 4182static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4183{ 4184 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4185} 4186 4187static int si_reset_to_default(struct radeon_device *rdev) 4188{ 4189 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4190 0 : -EINVAL; 4191} 4192 4193static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4194{ 4195 struct si_power_info *si_pi = si_get_pi(rdev); 4196 u32 tmp; 4197 int ret; 4198 4199 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4200 &tmp, si_pi->sram_end); 4201 if (ret) 4202 return ret; 4203 4204 tmp = (tmp >> 24) & 0xff; 4205 4206 if (tmp == MC_CG_ARB_FREQ_F0) 4207 return 0; 4208 4209 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4210} 4211 4212static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4213 u32 engine_clock) 4214{ 4215 u32 dram_rows; 4216 u32 dram_refresh_rate; 4217 u32 mc_arb_rfsh_rate; 4218 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4219 4220 if (tmp >= 4) 4221 dram_rows = 16384; 4222 else 4223 dram_rows = 1 << (tmp + 10); 4224 4225 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4226 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4227 4228 return mc_arb_rfsh_rate; 4229} 4230 4231static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4232 struct rv7xx_pl *pl, 4233 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4234{ 4235 u32 dram_timing; 4236 u32 dram_timing2; 4237 u32 burst_time; 4238 4239 arb_regs->mc_arb_rfsh_rate = 4240 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4241 4242 radeon_atom_set_engine_dram_timings(rdev, 4243 pl->sclk, 4244 pl->mclk); 4245 4246 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4247 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4248 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4249 4250 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4251 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4252 arb_regs->mc_arb_burst_time = (u8)burst_time; 4253 4254 return 0; 4255} 4256 4257static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4258 struct radeon_ps *radeon_state, 4259 unsigned int first_arb_set) 4260{ 4261 struct si_power_info *si_pi = si_get_pi(rdev); 4262 struct ni_ps *state = ni_get_ps(radeon_state); 4263 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4264 int i, ret = 0; 4265 4266 for (i = 0; i < state->performance_level_count; i++) { 4267 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4268 if (ret) 4269 break; 4270 ret = si_copy_bytes_to_smc(rdev, 4271 si_pi->arb_table_start + 4272 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4273 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4274 (u8 *)&arb_regs, 4275 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4276 si_pi->sram_end); 4277 if (ret) 4278 break; 4279 } 4280 4281 return ret; 4282} 4283 4284static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4285 struct radeon_ps *radeon_new_state) 4286{ 4287 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4288 SISLANDS_DRIVER_STATE_ARB_INDEX); 4289} 4290 4291static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4292 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4293{ 4294 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4295 struct si_power_info *si_pi = si_get_pi(rdev); 4296 4297 if (pi->mvdd_control) 4298 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4299 si_pi->mvdd_bootup_value, voltage); 4300 4301 return 0; 4302} 4303 4304static int si_populate_smc_initial_state(struct radeon_device *rdev, 4305 struct radeon_ps *radeon_initial_state, 4306 SISLANDS_SMC_STATETABLE *table) 4307{ 4308 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4309 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4310 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4311 struct si_power_info *si_pi = si_get_pi(rdev); 4312 u32 reg; 4313 int ret; 4314 4315 table->initialState.levels[0].mclk.vDLL_CNTL = 4316 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4317 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4318 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4319 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4320 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4321 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4322 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4323 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4324 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4325 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4326 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4327 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4328 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4329 table->initialState.levels[0].mclk.vMPLL_SS = 4330 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4331 table->initialState.levels[0].mclk.vMPLL_SS2 = 4332 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4333 4334 table->initialState.levels[0].mclk.mclk_value = 4335 cpu_to_be32(initial_state->performance_levels[0].mclk); 4336 4337 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4338 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4339 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4340 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4341 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4342 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4343 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4344 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4345 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4346 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4347 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4348 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4349 4350 table->initialState.levels[0].sclk.sclk_value = 4351 cpu_to_be32(initial_state->performance_levels[0].sclk); 4352 4353 table->initialState.levels[0].arbRefreshState = 4354 SISLANDS_INITIAL_STATE_ARB_INDEX; 4355 4356 table->initialState.levels[0].ACIndex = 0; 4357 4358 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4359 initial_state->performance_levels[0].vddc, 4360 &table->initialState.levels[0].vddc); 4361 4362 if (!ret) { 4363 u16 std_vddc; 4364 4365 ret = si_get_std_voltage_value(rdev, 4366 &table->initialState.levels[0].vddc, 4367 &std_vddc); 4368 if (!ret) 4369 si_populate_std_voltage_value(rdev, std_vddc, 4370 table->initialState.levels[0].vddc.index, 4371 &table->initialState.levels[0].std_vddc); 4372 } 4373 4374 if (eg_pi->vddci_control) 4375 si_populate_voltage_value(rdev, 4376 &eg_pi->vddci_voltage_table, 4377 initial_state->performance_levels[0].vddci, 4378 &table->initialState.levels[0].vddci); 4379 4380 if (si_pi->vddc_phase_shed_control) 4381 si_populate_phase_shedding_value(rdev, 4382 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4383 initial_state->performance_levels[0].vddc, 4384 initial_state->performance_levels[0].sclk, 4385 initial_state->performance_levels[0].mclk, 4386 &table->initialState.levels[0].vddc); 4387 4388 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4389 4390 reg = CG_R(0xffff) | CG_L(0); 4391 table->initialState.levels[0].aT = cpu_to_be32(reg); 4392 4393 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4394 4395 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4396 4397 if (pi->mem_gddr5) { 4398 table->initialState.levels[0].strobeMode = 4399 si_get_strobe_mode_settings(rdev, 4400 initial_state->performance_levels[0].mclk); 4401 4402 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4403 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4404 else 4405 table->initialState.levels[0].mcFlags = 0; 4406 } 4407 4408 table->initialState.levelCount = 1; 4409 4410 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4411 4412 table->initialState.levels[0].dpm2.MaxPS = 0; 4413 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4414 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4415 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4416 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4417 4418 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4419 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4420 4421 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4422 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4423 4424 return 0; 4425} 4426 4427static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4428 SISLANDS_SMC_STATETABLE *table) 4429{ 4430 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4431 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4432 struct si_power_info *si_pi = si_get_pi(rdev); 4433 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4434 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4435 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4436 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4437 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4438 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4439 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4440 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4441 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4442 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4443 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4444 u32 reg; 4445 int ret; 4446 4447 table->ACPIState = table->initialState; 4448 4449 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4450 4451 if (pi->acpi_vddc) { 4452 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4453 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4454 if (!ret) { 4455 u16 std_vddc; 4456 4457 ret = si_get_std_voltage_value(rdev, 4458 &table->ACPIState.levels[0].vddc, &std_vddc); 4459 if (!ret) 4460 si_populate_std_voltage_value(rdev, std_vddc, 4461 table->ACPIState.levels[0].vddc.index, 4462 &table->ACPIState.levels[0].std_vddc); 4463 } 4464 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4465 4466 if (si_pi->vddc_phase_shed_control) { 4467 si_populate_phase_shedding_value(rdev, 4468 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4469 pi->acpi_vddc, 4470 0, 4471 0, 4472 &table->ACPIState.levels[0].vddc); 4473 } 4474 } else { 4475 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4476 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4477 if (!ret) { 4478 u16 std_vddc; 4479 4480 ret = si_get_std_voltage_value(rdev, 4481 &table->ACPIState.levels[0].vddc, &std_vddc); 4482 4483 if (!ret) 4484 si_populate_std_voltage_value(rdev, std_vddc, 4485 table->ACPIState.levels[0].vddc.index, 4486 &table->ACPIState.levels[0].std_vddc); 4487 } 4488 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4489 si_pi->sys_pcie_mask, 4490 si_pi->boot_pcie_gen, 4491 RADEON_PCIE_GEN1); 4492 4493 if (si_pi->vddc_phase_shed_control) 4494 si_populate_phase_shedding_value(rdev, 4495 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4496 pi->min_vddc_in_table, 4497 0, 4498 0, 4499 &table->ACPIState.levels[0].vddc); 4500 } 4501 4502 if (pi->acpi_vddc) { 4503 if (eg_pi->acpi_vddci) 4504 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4505 eg_pi->acpi_vddci, 4506 &table->ACPIState.levels[0].vddci); 4507 } 4508 4509 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4510 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4511 4512 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4513 4514 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4515 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4516 4517 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4518 cpu_to_be32(dll_cntl); 4519 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4520 cpu_to_be32(mclk_pwrmgt_cntl); 4521 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4522 cpu_to_be32(mpll_ad_func_cntl); 4523 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4524 cpu_to_be32(mpll_dq_func_cntl); 4525 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4526 cpu_to_be32(mpll_func_cntl); 4527 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4528 cpu_to_be32(mpll_func_cntl_1); 4529 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4530 cpu_to_be32(mpll_func_cntl_2); 4531 table->ACPIState.levels[0].mclk.vMPLL_SS = 4532 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4533 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4534 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4535 4536 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4537 cpu_to_be32(spll_func_cntl); 4538 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4539 cpu_to_be32(spll_func_cntl_2); 4540 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4541 cpu_to_be32(spll_func_cntl_3); 4542 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4543 cpu_to_be32(spll_func_cntl_4); 4544 4545 table->ACPIState.levels[0].mclk.mclk_value = 0; 4546 table->ACPIState.levels[0].sclk.sclk_value = 0; 4547 4548 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4549 4550 if (eg_pi->dynamic_ac_timing) 4551 table->ACPIState.levels[0].ACIndex = 0; 4552 4553 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4554 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4555 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4556 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4557 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4558 4559 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4560 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4561 4562 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4563 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4564 4565 return 0; 4566} 4567 4568static int si_populate_ulv_state(struct radeon_device *rdev, 4569 SISLANDS_SMC_SWSTATE *state) 4570{ 4571 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4572 struct si_power_info *si_pi = si_get_pi(rdev); 4573 struct si_ulv_param *ulv = &si_pi->ulv; 4574 u32 sclk_in_sr = 1350; /* ??? */ 4575 int ret; 4576 4577 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4578 &state->levels[0]); 4579 if (!ret) { 4580 if (eg_pi->sclk_deep_sleep) { 4581 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4582 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4583 else 4584 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4585 } 4586 if (ulv->one_pcie_lane_in_ulv) 4587 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4588 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4589 state->levels[0].ACIndex = 1; 4590 state->levels[0].std_vddc = state->levels[0].vddc; 4591 state->levelCount = 1; 4592 4593 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4594 } 4595 4596 return ret; 4597} 4598 4599static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4600{ 4601 struct si_power_info *si_pi = si_get_pi(rdev); 4602 struct si_ulv_param *ulv = &si_pi->ulv; 4603 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4604 int ret; 4605 4606 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4607 &arb_regs); 4608 if (ret) 4609 return ret; 4610 4611 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4612 ulv->volt_change_delay); 4613 4614 ret = si_copy_bytes_to_smc(rdev, 4615 si_pi->arb_table_start + 4616 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4617 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4618 (u8 *)&arb_regs, 4619 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4620 si_pi->sram_end); 4621 4622 return ret; 4623} 4624 4625static void si_get_mvdd_configuration(struct radeon_device *rdev) 4626{ 4627 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4628 4629 pi->mvdd_split_frequency = 30000; 4630} 4631 4632static int si_init_smc_table(struct radeon_device *rdev) 4633{ 4634 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4635 struct si_power_info *si_pi = si_get_pi(rdev); 4636 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4637 const struct si_ulv_param *ulv = &si_pi->ulv; 4638 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4639 int ret; 4640 u32 lane_width; 4641 u32 vr_hot_gpio; 4642 4643 si_populate_smc_voltage_tables(rdev, table); 4644 4645 switch (rdev->pm.int_thermal_type) { 4646 case THERMAL_TYPE_SI: 4647 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4648 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4649 break; 4650 case THERMAL_TYPE_NONE: 4651 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4652 break; 4653 default: 4654 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4655 break; 4656 } 4657 4658 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4659 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4660 4661 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4662 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4663 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4664 } 4665 4666 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4667 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4668 4669 if (pi->mem_gddr5) 4670 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4671 4672 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4673 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4674 4675 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4676 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4677 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4678 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4679 vr_hot_gpio); 4680 } 4681 4682 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4683 if (ret) 4684 return ret; 4685 4686 ret = si_populate_smc_acpi_state(rdev, table); 4687 if (ret) 4688 return ret; 4689 4690 table->driverState = table->initialState; 4691 4692 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4693 SISLANDS_INITIAL_STATE_ARB_INDEX); 4694 if (ret) 4695 return ret; 4696 4697 if (ulv->supported && ulv->pl.vddc) { 4698 ret = si_populate_ulv_state(rdev, &table->ULVState); 4699 if (ret) 4700 return ret; 4701 4702 ret = si_program_ulv_memory_timing_parameters(rdev); 4703 if (ret) 4704 return ret; 4705 4706 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4707 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4708 4709 lane_width = radeon_get_pcie_lanes(rdev); 4710 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4711 } else { 4712 table->ULVState = table->initialState; 4713 } 4714 4715 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4716 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4717 si_pi->sram_end); 4718} 4719 4720static int si_calculate_sclk_params(struct radeon_device *rdev, 4721 u32 engine_clock, 4722 SISLANDS_SMC_SCLK_VALUE *sclk) 4723{ 4724 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4725 struct si_power_info *si_pi = si_get_pi(rdev); 4726 struct atom_clock_dividers dividers; 4727 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4728 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4729 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4730 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4731 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4732 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4733 u64 tmp; 4734 u32 reference_clock = rdev->clock.spll.reference_freq; 4735 u32 reference_divider; 4736 u32 fbdiv; 4737 int ret; 4738 4739 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4740 engine_clock, false, ÷rs); 4741 if (ret) 4742 return ret; 4743 4744 reference_divider = 1 + dividers.ref_div; 4745 4746 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4747 do_div(tmp, reference_clock); 4748 fbdiv = (u32) tmp; 4749 4750 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4751 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4752 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4753 4754 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4755 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4756 4757 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4758 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4759 spll_func_cntl_3 |= SPLL_DITHEN; 4760 4761 if (pi->sclk_ss) { 4762 struct radeon_atom_ss ss; 4763 u32 vco_freq = engine_clock * dividers.post_div; 4764 4765 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4766 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4767 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4768 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4769 4770 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4771 cg_spll_spread_spectrum |= CLK_S(clk_s); 4772 cg_spll_spread_spectrum |= SSEN; 4773 4774 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4775 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4776 } 4777 } 4778 4779 sclk->sclk_value = engine_clock; 4780 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4781 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4782 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4783 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4784 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4785 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4786 4787 return 0; 4788} 4789 4790static int si_populate_sclk_value(struct radeon_device *rdev, 4791 u32 engine_clock, 4792 SISLANDS_SMC_SCLK_VALUE *sclk) 4793{ 4794 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4795 int ret; 4796 4797 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4798 if (!ret) { 4799 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4800 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4801 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4802 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4803 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4804 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4805 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4806 } 4807 4808 return ret; 4809} 4810 4811static int si_populate_mclk_value(struct radeon_device *rdev, 4812 u32 engine_clock, 4813 u32 memory_clock, 4814 SISLANDS_SMC_MCLK_VALUE *mclk, 4815 bool strobe_mode, 4816 bool dll_state_on) 4817{ 4818 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4819 struct si_power_info *si_pi = si_get_pi(rdev); 4820 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4821 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4822 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4823 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4824 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4825 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4826 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4827 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4828 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4829 struct atom_mpll_param mpll_param; 4830 int ret; 4831 4832 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4833 if (ret) 4834 return ret; 4835 4836 mpll_func_cntl &= ~BWCTRL_MASK; 4837 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4838 4839 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4840 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4841 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4842 4843 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4844 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4845 4846 if (pi->mem_gddr5) { 4847 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4848 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4849 YCLK_POST_DIV(mpll_param.post_div); 4850 } 4851 4852 if (pi->mclk_ss) { 4853 struct radeon_atom_ss ss; 4854 u32 freq_nom; 4855 u32 tmp; 4856 u32 reference_clock = rdev->clock.mpll.reference_freq; 4857 4858 if (pi->mem_gddr5) 4859 freq_nom = memory_clock * 4; 4860 else 4861 freq_nom = memory_clock * 2; 4862 4863 tmp = freq_nom / reference_clock; 4864 tmp = tmp * tmp; 4865 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4866 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4867 u32 clks = reference_clock * 5 / ss.rate; 4868 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4869 4870 mpll_ss1 &= ~CLKV_MASK; 4871 mpll_ss1 |= CLKV(clkv); 4872 4873 mpll_ss2 &= ~CLKS_MASK; 4874 mpll_ss2 |= CLKS(clks); 4875 } 4876 } 4877 4878 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4879 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4880 4881 if (dll_state_on) 4882 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4883 else 4884 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4885 4886 mclk->mclk_value = cpu_to_be32(memory_clock); 4887 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4888 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4889 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4890 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4891 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4892 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4893 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4894 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4895 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4896 4897 return 0; 4898} 4899 4900static void si_populate_smc_sp(struct radeon_device *rdev, 4901 struct radeon_ps *radeon_state, 4902 SISLANDS_SMC_SWSTATE *smc_state) 4903{ 4904 struct ni_ps *ps = ni_get_ps(radeon_state); 4905 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4906 int i; 4907 4908 for (i = 0; i < ps->performance_level_count - 1; i++) 4909 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4910 4911 smc_state->levels[ps->performance_level_count - 1].bSP = 4912 cpu_to_be32(pi->psp); 4913} 4914 4915static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4916 struct rv7xx_pl *pl, 4917 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4918{ 4919 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4920 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4921 struct si_power_info *si_pi = si_get_pi(rdev); 4922 int ret; 4923 bool dll_state_on; 4924 u16 std_vddc; 4925 bool gmc_pg = false; 4926 4927 if (eg_pi->pcie_performance_request && 4928 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4929 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4930 else 4931 level->gen2PCIE = (u8)pl->pcie_gen; 4932 4933 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4934 if (ret) 4935 return ret; 4936 4937 level->mcFlags = 0; 4938 4939 if (pi->mclk_stutter_mode_threshold && 4940 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4941 !eg_pi->uvd_enabled && 4942 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4943 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4944 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4945 4946 if (gmc_pg) 4947 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4948 } 4949 4950 if (pi->mem_gddr5) { 4951 if (pl->mclk > pi->mclk_edc_enable_threshold) 4952 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4953 4954 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4955 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 4956 4957 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 4958 4959 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 4960 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 4961 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 4962 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4963 else 4964 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 4965 } else { 4966 dll_state_on = false; 4967 } 4968 } else { 4969 level->strobeMode = si_get_strobe_mode_settings(rdev, 4970 pl->mclk); 4971 4972 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 4973 } 4974 4975 ret = si_populate_mclk_value(rdev, 4976 pl->sclk, 4977 pl->mclk, 4978 &level->mclk, 4979 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 4980 if (ret) 4981 return ret; 4982 4983 ret = si_populate_voltage_value(rdev, 4984 &eg_pi->vddc_voltage_table, 4985 pl->vddc, &level->vddc); 4986 if (ret) 4987 return ret; 4988 4989 4990 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 4991 if (ret) 4992 return ret; 4993 4994 ret = si_populate_std_voltage_value(rdev, std_vddc, 4995 level->vddc.index, &level->std_vddc); 4996 if (ret) 4997 return ret; 4998 4999 if (eg_pi->vddci_control) { 5000 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5001 pl->vddci, &level->vddci); 5002 if (ret) 5003 return ret; 5004 } 5005 5006 if (si_pi->vddc_phase_shed_control) { 5007 ret = si_populate_phase_shedding_value(rdev, 5008 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5009 pl->vddc, 5010 pl->sclk, 5011 pl->mclk, 5012 &level->vddc); 5013 if (ret) 5014 return ret; 5015 } 5016 5017 level->MaxPoweredUpCU = si_pi->max_cu; 5018 5019 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5020 5021 return ret; 5022} 5023 5024static int si_populate_smc_t(struct radeon_device *rdev, 5025 struct radeon_ps *radeon_state, 5026 SISLANDS_SMC_SWSTATE *smc_state) 5027{ 5028 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5029 struct ni_ps *state = ni_get_ps(radeon_state); 5030 u32 a_t; 5031 u32 t_l, t_h; 5032 u32 high_bsp; 5033 int i, ret; 5034 5035 if (state->performance_level_count >= 9) 5036 return -EINVAL; 5037 5038 if (state->performance_level_count < 2) { 5039 a_t = CG_R(0xffff) | CG_L(0); 5040 smc_state->levels[0].aT = cpu_to_be32(a_t); 5041 return 0; 5042 } 5043 5044 smc_state->levels[0].aT = cpu_to_be32(0); 5045 5046 for (i = 0; i <= state->performance_level_count - 2; i++) { 5047 ret = r600_calculate_at( 5048 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5049 100 * R600_AH_DFLT, 5050 state->performance_levels[i + 1].sclk, 5051 state->performance_levels[i].sclk, 5052 &t_l, 5053 &t_h); 5054 5055 if (ret) { 5056 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5057 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5058 } 5059 5060 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5061 a_t |= CG_R(t_l * pi->bsp / 20000); 5062 smc_state->levels[i].aT = cpu_to_be32(a_t); 5063 5064 high_bsp = (i == state->performance_level_count - 2) ? 5065 pi->pbsp : pi->bsp; 5066 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5067 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5068 } 5069 5070 return 0; 5071} 5072 5073static int si_disable_ulv(struct radeon_device *rdev) 5074{ 5075 struct si_power_info *si_pi = si_get_pi(rdev); 5076 struct si_ulv_param *ulv = &si_pi->ulv; 5077 5078 if (ulv->supported) 5079 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5080 0 : -EINVAL; 5081 5082 return 0; 5083} 5084 5085static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5086 struct radeon_ps *radeon_state) 5087{ 5088 const struct si_power_info *si_pi = si_get_pi(rdev); 5089 const struct si_ulv_param *ulv = &si_pi->ulv; 5090 const struct ni_ps *state = ni_get_ps(radeon_state); 5091 int i; 5092 5093 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5094 return false; 5095 5096 /* XXX validate against display requirements! */ 5097 5098 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5099 if (rdev->clock.current_dispclk <= 5100 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5101 if (ulv->pl.vddc < 5102 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5103 return false; 5104 } 5105 } 5106 5107 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5108 return false; 5109 5110 return true; 5111} 5112 5113static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5114 struct radeon_ps *radeon_new_state) 5115{ 5116 const struct si_power_info *si_pi = si_get_pi(rdev); 5117 const struct si_ulv_param *ulv = &si_pi->ulv; 5118 5119 if (ulv->supported) { 5120 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5121 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5122 0 : -EINVAL; 5123 } 5124 return 0; 5125} 5126 5127static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5128 struct radeon_ps *radeon_state, 5129 SISLANDS_SMC_SWSTATE *smc_state) 5130{ 5131 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5132 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5133 struct si_power_info *si_pi = si_get_pi(rdev); 5134 struct ni_ps *state = ni_get_ps(radeon_state); 5135 int i, ret; 5136 u32 threshold; 5137 u32 sclk_in_sr = 1350; /* ??? */ 5138 5139 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5140 return -EINVAL; 5141 5142 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5143 5144 if (radeon_state->vclk && radeon_state->dclk) { 5145 eg_pi->uvd_enabled = true; 5146 if (eg_pi->smu_uvd_hs) 5147 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5148 } else { 5149 eg_pi->uvd_enabled = false; 5150 } 5151 5152 if (state->dc_compatible) 5153 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5154 5155 smc_state->levelCount = 0; 5156 for (i = 0; i < state->performance_level_count; i++) { 5157 if (eg_pi->sclk_deep_sleep) { 5158 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5159 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5160 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5161 else 5162 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5163 } 5164 } 5165 5166 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5167 &smc_state->levels[i]); 5168 smc_state->levels[i].arbRefreshState = 5169 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5170 5171 if (ret) 5172 return ret; 5173 5174 if (ni_pi->enable_power_containment) 5175 smc_state->levels[i].displayWatermark = 5176 (state->performance_levels[i].sclk < threshold) ? 5177 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5178 else 5179 smc_state->levels[i].displayWatermark = (i < 2) ? 5180 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5181 5182 if (eg_pi->dynamic_ac_timing) 5183 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5184 else 5185 smc_state->levels[i].ACIndex = 0; 5186 5187 smc_state->levelCount++; 5188 } 5189 5190 si_write_smc_soft_register(rdev, 5191 SI_SMC_SOFT_REGISTER_watermark_threshold, 5192 threshold / 512); 5193 5194 si_populate_smc_sp(rdev, radeon_state, smc_state); 5195 5196 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5197 if (ret) 5198 ni_pi->enable_power_containment = false; 5199 5200 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5201 if (ret) 5202 ni_pi->enable_sq_ramping = false; 5203 5204 return si_populate_smc_t(rdev, radeon_state, smc_state); 5205} 5206 5207static int si_upload_sw_state(struct radeon_device *rdev, 5208 struct radeon_ps *radeon_new_state) 5209{ 5210 struct si_power_info *si_pi = si_get_pi(rdev); 5211 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5212 int ret; 5213 u32 address = si_pi->state_table_start + 5214 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5215 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5216 ((new_state->performance_level_count - 1) * 5217 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5218 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5219 5220 memset(smc_state, 0, state_size); 5221 5222 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5223 if (ret) 5224 return ret; 5225 5226 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5227 state_size, si_pi->sram_end); 5228 5229 return ret; 5230} 5231 5232static int si_upload_ulv_state(struct radeon_device *rdev) 5233{ 5234 struct si_power_info *si_pi = si_get_pi(rdev); 5235 struct si_ulv_param *ulv = &si_pi->ulv; 5236 int ret = 0; 5237 5238 if (ulv->supported && ulv->pl.vddc) { 5239 u32 address = si_pi->state_table_start + 5240 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5241 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5242 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5243 5244 memset(smc_state, 0, state_size); 5245 5246 ret = si_populate_ulv_state(rdev, smc_state); 5247 if (!ret) 5248 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5249 state_size, si_pi->sram_end); 5250 } 5251 5252 return ret; 5253} 5254 5255static int si_upload_smc_data(struct radeon_device *rdev) 5256{ 5257 struct radeon_crtc *radeon_crtc = NULL; 5258 int i; 5259 5260 if (rdev->pm.dpm.new_active_crtc_count == 0) 5261 return 0; 5262 5263 for (i = 0; i < rdev->num_crtc; i++) { 5264 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5265 radeon_crtc = rdev->mode_info.crtcs[i]; 5266 break; 5267 } 5268 } 5269 5270 if (radeon_crtc == NULL) 5271 return 0; 5272 5273 if (radeon_crtc->line_time <= 0) 5274 return 0; 5275 5276 if (si_write_smc_soft_register(rdev, 5277 SI_SMC_SOFT_REGISTER_crtc_index, 5278 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5279 return 0; 5280 5281 if (si_write_smc_soft_register(rdev, 5282 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5283 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5284 return 0; 5285 5286 if (si_write_smc_soft_register(rdev, 5287 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5288 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5289 return 0; 5290 5291 return 0; 5292} 5293 5294static int si_set_mc_special_registers(struct radeon_device *rdev, 5295 struct si_mc_reg_table *table) 5296{ 5297 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5298 u8 i, j, k; 5299 u32 temp_reg; 5300 5301 for (i = 0, j = table->last; i < table->last; i++) { 5302 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5303 return -EINVAL; 5304 switch (table->mc_reg_address[i].s1 << 2) { 5305 case MC_SEQ_MISC1: 5306 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5307 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5308 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5309 for (k = 0; k < table->num_entries; k++) 5310 table->mc_reg_table_entry[k].mc_data[j] = 5311 ((temp_reg & 0xffff0000)) | 5312 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5313 j++; 5314 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5315 return -EINVAL; 5316 5317 temp_reg = RREG32(MC_PMG_CMD_MRS); 5318 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5319 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5320 for (k = 0; k < table->num_entries; k++) { 5321 table->mc_reg_table_entry[k].mc_data[j] = 5322 (temp_reg & 0xffff0000) | 5323 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5324 if (!pi->mem_gddr5) 5325 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5326 } 5327 j++; 5328 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5329 return -EINVAL; 5330 5331 if (!pi->mem_gddr5) { 5332 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5333 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5334 for (k = 0; k < table->num_entries; k++) 5335 table->mc_reg_table_entry[k].mc_data[j] = 5336 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5337 j++; 5338 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5339 return -EINVAL; 5340 } 5341 break; 5342 case MC_SEQ_RESERVE_M: 5343 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5344 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5345 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5346 for(k = 0; k < table->num_entries; k++) 5347 table->mc_reg_table_entry[k].mc_data[j] = 5348 (temp_reg & 0xffff0000) | 5349 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5350 j++; 5351 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5352 return -EINVAL; 5353 break; 5354 default: 5355 break; 5356 } 5357 } 5358 5359 table->last = j; 5360 5361 return 0; 5362} 5363 5364static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5365{ 5366 bool result = true; 5367 5368 switch (in_reg) { 5369 case MC_SEQ_RAS_TIMING >> 2: 5370 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5371 break; 5372 case MC_SEQ_CAS_TIMING >> 2: 5373 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5374 break; 5375 case MC_SEQ_MISC_TIMING >> 2: 5376 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5377 break; 5378 case MC_SEQ_MISC_TIMING2 >> 2: 5379 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5380 break; 5381 case MC_SEQ_RD_CTL_D0 >> 2: 5382 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5383 break; 5384 case MC_SEQ_RD_CTL_D1 >> 2: 5385 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5386 break; 5387 case MC_SEQ_WR_CTL_D0 >> 2: 5388 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5389 break; 5390 case MC_SEQ_WR_CTL_D1 >> 2: 5391 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5392 break; 5393 case MC_PMG_CMD_EMRS >> 2: 5394 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5395 break; 5396 case MC_PMG_CMD_MRS >> 2: 5397 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5398 break; 5399 case MC_PMG_CMD_MRS1 >> 2: 5400 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5401 break; 5402 case MC_SEQ_PMG_TIMING >> 2: 5403 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5404 break; 5405 case MC_PMG_CMD_MRS2 >> 2: 5406 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5407 break; 5408 case MC_SEQ_WR_CTL_2 >> 2: 5409 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5410 break; 5411 default: 5412 result = false; 5413 break; 5414 } 5415 5416 return result; 5417} 5418 5419static void si_set_valid_flag(struct si_mc_reg_table *table) 5420{ 5421 u8 i, j; 5422 5423 for (i = 0; i < table->last; i++) { 5424 for (j = 1; j < table->num_entries; j++) { 5425 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5426 table->valid_flag |= 1 << i; 5427 break; 5428 } 5429 } 5430 } 5431} 5432 5433static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5434{ 5435 u32 i; 5436 u16 address; 5437 5438 for (i = 0; i < table->last; i++) 5439 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5440 address : table->mc_reg_address[i].s1; 5441 5442} 5443 5444static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5445 struct si_mc_reg_table *si_table) 5446{ 5447 u8 i, j; 5448 5449 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5450 return -EINVAL; 5451 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5452 return -EINVAL; 5453 5454 for (i = 0; i < table->last; i++) 5455 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5456 si_table->last = table->last; 5457 5458 for (i = 0; i < table->num_entries; i++) { 5459 si_table->mc_reg_table_entry[i].mclk_max = 5460 table->mc_reg_table_entry[i].mclk_max; 5461 for (j = 0; j < table->last; j++) { 5462 si_table->mc_reg_table_entry[i].mc_data[j] = 5463 table->mc_reg_table_entry[i].mc_data[j]; 5464 } 5465 } 5466 si_table->num_entries = table->num_entries; 5467 5468 return 0; 5469} 5470 5471static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5472{ 5473 struct si_power_info *si_pi = si_get_pi(rdev); 5474 struct atom_mc_reg_table *table; 5475 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5476 u8 module_index = rv770_get_memory_module_index(rdev); 5477 int ret; 5478 5479 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5480 if (!table) 5481 return -ENOMEM; 5482 5483 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5484 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5485 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5486 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5487 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5488 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5489 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5490 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5491 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5492 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5493 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5494 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5495 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5496 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5497 5498 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5499 if (ret) 5500 goto init_mc_done; 5501 5502 ret = si_copy_vbios_mc_reg_table(table, si_table); 5503 if (ret) 5504 goto init_mc_done; 5505 5506 si_set_s0_mc_reg_index(si_table); 5507 5508 ret = si_set_mc_special_registers(rdev, si_table); 5509 if (ret) 5510 goto init_mc_done; 5511 5512 si_set_valid_flag(si_table); 5513 5514init_mc_done: 5515 kfree(table); 5516 5517 return ret; 5518 5519} 5520 5521static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5522 SMC_SIslands_MCRegisters *mc_reg_table) 5523{ 5524 struct si_power_info *si_pi = si_get_pi(rdev); 5525 u32 i, j; 5526 5527 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5528 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5529 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5530 break; 5531 mc_reg_table->address[i].s0 = 5532 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5533 mc_reg_table->address[i].s1 = 5534 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5535 i++; 5536 } 5537 } 5538 mc_reg_table->last = (u8)i; 5539} 5540 5541static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5542 SMC_SIslands_MCRegisterSet *data, 5543 u32 num_entries, u32 valid_flag) 5544{ 5545 u32 i, j; 5546 5547 for(i = 0, j = 0; j < num_entries; j++) { 5548 if (valid_flag & (1 << j)) { 5549 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5550 i++; 5551 } 5552 } 5553} 5554 5555static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5556 struct rv7xx_pl *pl, 5557 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5558{ 5559 struct si_power_info *si_pi = si_get_pi(rdev); 5560 u32 i = 0; 5561 5562 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5563 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5564 break; 5565 } 5566 5567 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5568 --i; 5569 5570 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5571 mc_reg_table_data, si_pi->mc_reg_table.last, 5572 si_pi->mc_reg_table.valid_flag); 5573} 5574 5575static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5576 struct radeon_ps *radeon_state, 5577 SMC_SIslands_MCRegisters *mc_reg_table) 5578{ 5579 struct ni_ps *state = ni_get_ps(radeon_state); 5580 int i; 5581 5582 for (i = 0; i < state->performance_level_count; i++) { 5583 si_convert_mc_reg_table_entry_to_smc(rdev, 5584 &state->performance_levels[i], 5585 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5586 } 5587} 5588 5589static int si_populate_mc_reg_table(struct radeon_device *rdev, 5590 struct radeon_ps *radeon_boot_state) 5591{ 5592 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5593 struct si_power_info *si_pi = si_get_pi(rdev); 5594 struct si_ulv_param *ulv = &si_pi->ulv; 5595 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5596 5597 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5598 5599 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5600 5601 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5602 5603 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5604 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5605 5606 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5607 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5608 si_pi->mc_reg_table.last, 5609 si_pi->mc_reg_table.valid_flag); 5610 5611 if (ulv->supported && ulv->pl.vddc != 0) 5612 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5613 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5614 else 5615 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5616 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5617 si_pi->mc_reg_table.last, 5618 si_pi->mc_reg_table.valid_flag); 5619 5620 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5621 5622 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5623 (u8 *)smc_mc_reg_table, 5624 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5625} 5626 5627static int si_upload_mc_reg_table(struct radeon_device *rdev, 5628 struct radeon_ps *radeon_new_state) 5629{ 5630 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5631 struct si_power_info *si_pi = si_get_pi(rdev); 5632 u32 address = si_pi->mc_reg_table_start + 5633 offsetof(SMC_SIslands_MCRegisters, 5634 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5635 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5636 5637 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5638 5639 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5640 5641 5642 return si_copy_bytes_to_smc(rdev, address, 5643 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5644 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5645 si_pi->sram_end); 5646 5647} 5648 5649static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5650{ 5651 if (enable) 5652 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5653 else 5654 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5655} 5656 5657static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5658 struct radeon_ps *radeon_state) 5659{ 5660 struct ni_ps *state = ni_get_ps(radeon_state); 5661 int i; 5662 u16 pcie_speed, max_speed = 0; 5663 5664 for (i = 0; i < state->performance_level_count; i++) { 5665 pcie_speed = state->performance_levels[i].pcie_gen; 5666 if (max_speed < pcie_speed) 5667 max_speed = pcie_speed; 5668 } 5669 return max_speed; 5670} 5671 5672static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5673{ 5674 u32 speed_cntl; 5675 5676 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5677 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5678 5679 return (u16)speed_cntl; 5680} 5681 5682static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5683 struct radeon_ps *radeon_new_state, 5684 struct radeon_ps *radeon_current_state) 5685{ 5686 struct si_power_info *si_pi = si_get_pi(rdev); 5687 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5688 enum radeon_pcie_gen current_link_speed; 5689 5690 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5691 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5692 else 5693 current_link_speed = si_pi->force_pcie_gen; 5694 5695 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5696 si_pi->pspp_notify_required = false; 5697 if (target_link_speed > current_link_speed) { 5698 switch (target_link_speed) { 5699#if defined(CONFIG_ACPI) 5700 case RADEON_PCIE_GEN3: 5701 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5702 break; 5703 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5704 if (current_link_speed == RADEON_PCIE_GEN2) 5705 break; 5706 case RADEON_PCIE_GEN2: 5707 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5708 break; 5709#endif 5710 default: 5711 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5712 break; 5713 } 5714 } else { 5715 if (target_link_speed < current_link_speed) 5716 si_pi->pspp_notify_required = true; 5717 } 5718} 5719 5720static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5721 struct radeon_ps *radeon_new_state, 5722 struct radeon_ps *radeon_current_state) 5723{ 5724 struct si_power_info *si_pi = si_get_pi(rdev); 5725 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5726 u8 request; 5727 5728 if (si_pi->pspp_notify_required) { 5729 if (target_link_speed == RADEON_PCIE_GEN3) 5730 request = PCIE_PERF_REQ_PECI_GEN3; 5731 else if (target_link_speed == RADEON_PCIE_GEN2) 5732 request = PCIE_PERF_REQ_PECI_GEN2; 5733 else 5734 request = PCIE_PERF_REQ_PECI_GEN1; 5735 5736 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5737 (si_get_current_pcie_speed(rdev) > 0)) 5738 return; 5739 5740#if defined(CONFIG_ACPI) 5741 radeon_acpi_pcie_performance_request(rdev, request, false); 5742#endif 5743 } 5744} 5745 5746#if 0 5747static int si_ds_request(struct radeon_device *rdev, 5748 bool ds_status_on, u32 count_write) 5749{ 5750 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5751 5752 if (eg_pi->sclk_deep_sleep) { 5753 if (ds_status_on) 5754 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5755 PPSMC_Result_OK) ? 5756 0 : -EINVAL; 5757 else 5758 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5759 PPSMC_Result_OK) ? 0 : -EINVAL; 5760 } 5761 return 0; 5762} 5763#endif 5764 5765static void si_set_max_cu_value(struct radeon_device *rdev) 5766{ 5767 struct si_power_info *si_pi = si_get_pi(rdev); 5768 5769 if (rdev->family == CHIP_VERDE) { 5770 switch (rdev->pdev->device) { 5771 case 0x6820: 5772 case 0x6825: 5773 case 0x6821: 5774 case 0x6823: 5775 case 0x6827: 5776 si_pi->max_cu = 10; 5777 break; 5778 case 0x682D: 5779 case 0x6824: 5780 case 0x682F: 5781 case 0x6826: 5782 si_pi->max_cu = 8; 5783 break; 5784 case 0x6828: 5785 case 0x6830: 5786 case 0x6831: 5787 case 0x6838: 5788 case 0x6839: 5789 case 0x683D: 5790 si_pi->max_cu = 10; 5791 break; 5792 case 0x683B: 5793 case 0x683F: 5794 case 0x6829: 5795 si_pi->max_cu = 8; 5796 break; 5797 default: 5798 si_pi->max_cu = 0; 5799 break; 5800 } 5801 } else { 5802 si_pi->max_cu = 0; 5803 } 5804} 5805 5806static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5807 struct radeon_clock_voltage_dependency_table *table) 5808{ 5809 u32 i; 5810 int j; 5811 u16 leakage_voltage; 5812 5813 if (table) { 5814 for (i = 0; i < table->count; i++) { 5815 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5816 table->entries[i].v, 5817 &leakage_voltage)) { 5818 case 0: 5819 table->entries[i].v = leakage_voltage; 5820 break; 5821 case -EAGAIN: 5822 return -EINVAL; 5823 case -EINVAL: 5824 default: 5825 break; 5826 } 5827 } 5828 5829 for (j = (table->count - 2); j >= 0; j--) { 5830 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5831 table->entries[j].v : table->entries[j + 1].v; 5832 } 5833 } 5834 return 0; 5835} 5836 5837static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5838{ 5839 int ret = 0; 5840 5841 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5842 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5843 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5844 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5845 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5846 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5847 return ret; 5848} 5849 5850static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5851 struct radeon_ps *radeon_new_state, 5852 struct radeon_ps *radeon_current_state) 5853{ 5854 u32 lane_width; 5855 u32 new_lane_width = 5856 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5857 u32 current_lane_width = 5858 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; 5859 5860 if (new_lane_width != current_lane_width) { 5861 radeon_set_pcie_lanes(rdev, new_lane_width); 5862 lane_width = radeon_get_pcie_lanes(rdev); 5863 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5864 } 5865} 5866 5867void si_dpm_setup_asic(struct radeon_device *rdev) 5868{ 5869 int r; 5870 5871 r = si_mc_load_microcode(rdev); 5872 if (r) 5873 DRM_ERROR("Failed to load MC firmware!\n"); 5874 rv770_get_memory_type(rdev); 5875 si_read_clock_registers(rdev); 5876 si_enable_acpi_power_management(rdev); 5877} 5878 5879static int si_thermal_enable_alert(struct radeon_device *rdev, 5880 bool enable) 5881{ 5882 u32 thermal_int = RREG32(CG_THERMAL_INT); 5883 5884 if (enable) { 5885 PPSMC_Result result; 5886 5887 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5888 WREG32(CG_THERMAL_INT, thermal_int); 5889 rdev->irq.dpm_thermal = false; 5890 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5891 if (result != PPSMC_Result_OK) { 5892 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5893 return -EINVAL; 5894 } 5895 } else { 5896 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5897 WREG32(CG_THERMAL_INT, thermal_int); 5898 rdev->irq.dpm_thermal = true; 5899 } 5900 5901 return 0; 5902} 5903 5904static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5905 int min_temp, int max_temp) 5906{ 5907 int low_temp = 0 * 1000; 5908 int high_temp = 255 * 1000; 5909 5910 if (low_temp < min_temp) 5911 low_temp = min_temp; 5912 if (high_temp > max_temp) 5913 high_temp = max_temp; 5914 if (high_temp < low_temp) { 5915 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5916 return -EINVAL; 5917 } 5918 5919 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5920 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5921 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5922 5923 rdev->pm.dpm.thermal.min_temp = low_temp; 5924 rdev->pm.dpm.thermal.max_temp = high_temp; 5925 5926 return 0; 5927} 5928 5929static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 5930{ 5931 struct si_power_info *si_pi = si_get_pi(rdev); 5932 u32 tmp; 5933 5934 if (si_pi->fan_ctrl_is_in_default_mode) { 5935 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 5936 si_pi->fan_ctrl_default_mode = tmp; 5937 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 5938 si_pi->t_min = tmp; 5939 si_pi->fan_ctrl_is_in_default_mode = false; 5940 } 5941 5942 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 5943 tmp |= TMIN(0); 5944 WREG32(CG_FDO_CTRL2, tmp); 5945 5946 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 5947 tmp |= FDO_PWM_MODE(mode); 5948 WREG32(CG_FDO_CTRL2, tmp); 5949} 5950 5951static int si_thermal_setup_fan_table(struct radeon_device *rdev) 5952{ 5953 struct si_power_info *si_pi = si_get_pi(rdev); 5954 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 5955 u32 duty100; 5956 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 5957 u16 fdo_min, slope1, slope2; 5958 u32 reference_clock, tmp; 5959 int ret; 5960 u64 tmp64; 5961 5962 if (!si_pi->fan_table_start) { 5963 rdev->pm.dpm.fan.ucode_fan_control = false; 5964 return 0; 5965 } 5966 5967 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 5968 5969 if (duty100 == 0) { 5970 rdev->pm.dpm.fan.ucode_fan_control = false; 5971 return 0; 5972 } 5973 5974 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 5975 do_div(tmp64, 10000); 5976 fdo_min = (u16)tmp64; 5977 5978 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 5979 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 5980 5981 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 5982 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 5983 5984 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 5985 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 5986 5987 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 5988 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 5989 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 5990 5991 fan_table.slope1 = cpu_to_be16(slope1); 5992 fan_table.slope2 = cpu_to_be16(slope2); 5993 5994 fan_table.fdo_min = cpu_to_be16(fdo_min); 5995 5996 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 5997 5998 fan_table.hys_up = cpu_to_be16(1); 5999 6000 fan_table.hys_slope = cpu_to_be16(1); 6001 6002 fan_table.temp_resp_lim = cpu_to_be16(5); 6003 6004 reference_clock = radeon_get_xclk(rdev); 6005 6006 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6007 reference_clock) / 1600); 6008 6009 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6010 6011 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6012 fan_table.temp_src = (uint8_t)tmp; 6013 6014 ret = si_copy_bytes_to_smc(rdev, 6015 si_pi->fan_table_start, 6016 (u8 *)(&fan_table), 6017 sizeof(fan_table), 6018 si_pi->sram_end); 6019 6020 if (ret) { 6021 DRM_ERROR("Failed to load fan table to the SMC."); 6022 rdev->pm.dpm.fan.ucode_fan_control = false; 6023 } 6024 6025 return 0; 6026} 6027 6028static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6029{ 6030 struct si_power_info *si_pi = si_get_pi(rdev); 6031 PPSMC_Result ret; 6032 6033 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6034 if (ret == PPSMC_Result_OK) { 6035 si_pi->fan_is_controlled_by_smc = true; 6036 return 0; 6037 } else { 6038 return -EINVAL; 6039 } 6040} 6041 6042static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6043{ 6044 struct si_power_info *si_pi = si_get_pi(rdev); 6045 PPSMC_Result ret; 6046 6047 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6048 6049 if (ret == PPSMC_Result_OK) { 6050 si_pi->fan_is_controlled_by_smc = false; 6051 return 0; 6052 } else { 6053 return -EINVAL; 6054 } 6055} 6056 6057int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6058 u32 *speed) 6059{ 6060 u32 duty, duty100; 6061 u64 tmp64; 6062 6063 if (rdev->pm.no_fan) 6064 return -ENOENT; 6065 6066 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6067 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6068 6069 if (duty100 == 0) 6070 return -EINVAL; 6071 6072 tmp64 = (u64)duty * 100; 6073 do_div(tmp64, duty100); 6074 *speed = (u32)tmp64; 6075 6076 if (*speed > 100) 6077 *speed = 100; 6078 6079 return 0; 6080} 6081 6082int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6083 u32 speed) 6084{ 6085 struct si_power_info *si_pi = si_get_pi(rdev); 6086 u32 tmp; 6087 u32 duty, duty100; 6088 u64 tmp64; 6089 6090 if (rdev->pm.no_fan) 6091 return -ENOENT; 6092 6093 if (si_pi->fan_is_controlled_by_smc) 6094 return -EINVAL; 6095 6096 if (speed > 100) 6097 return -EINVAL; 6098 6099 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6100 6101 if (duty100 == 0) 6102 return -EINVAL; 6103 6104 tmp64 = (u64)speed * duty100; 6105 do_div(tmp64, 100); 6106 duty = (u32)tmp64; 6107 6108 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6109 tmp |= FDO_STATIC_DUTY(duty); 6110 WREG32(CG_FDO_CTRL0, tmp); 6111 6112 return 0; 6113} 6114 6115void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6116{ 6117 if (mode) { 6118 /* stop auto-manage */ 6119 if (rdev->pm.dpm.fan.ucode_fan_control) 6120 si_fan_ctrl_stop_smc_fan_control(rdev); 6121 si_fan_ctrl_set_static_mode(rdev, mode); 6122 } else { 6123 /* restart auto-manage */ 6124 if (rdev->pm.dpm.fan.ucode_fan_control) 6125 si_thermal_start_smc_fan_control(rdev); 6126 else 6127 si_fan_ctrl_set_default_mode(rdev); 6128 } 6129} 6130 6131u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6132{ 6133 struct si_power_info *si_pi = si_get_pi(rdev); 6134 u32 tmp; 6135 6136 if (si_pi->fan_is_controlled_by_smc) 6137 return 0; 6138 6139 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6140 return (tmp >> FDO_PWM_MODE_SHIFT); 6141} 6142 6143#if 0 6144static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6145 u32 *speed) 6146{ 6147 u32 tach_period; 6148 u32 xclk = radeon_get_xclk(rdev); 6149 6150 if (rdev->pm.no_fan) 6151 return -ENOENT; 6152 6153 if (rdev->pm.fan_pulses_per_revolution == 0) 6154 return -ENOENT; 6155 6156 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6157 if (tach_period == 0) 6158 return -ENOENT; 6159 6160 *speed = 60 * xclk * 10000 / tach_period; 6161 6162 return 0; 6163} 6164 6165static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6166 u32 speed) 6167{ 6168 u32 tach_period, tmp; 6169 u32 xclk = radeon_get_xclk(rdev); 6170 6171 if (rdev->pm.no_fan) 6172 return -ENOENT; 6173 6174 if (rdev->pm.fan_pulses_per_revolution == 0) 6175 return -ENOENT; 6176 6177 if ((speed < rdev->pm.fan_min_rpm) || 6178 (speed > rdev->pm.fan_max_rpm)) 6179 return -EINVAL; 6180 6181 if (rdev->pm.dpm.fan.ucode_fan_control) 6182 si_fan_ctrl_stop_smc_fan_control(rdev); 6183 6184 tach_period = 60 * xclk * 10000 / (8 * speed); 6185 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6186 tmp |= TARGET_PERIOD(tach_period); 6187 WREG32(CG_TACH_CTRL, tmp); 6188 6189 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6190 6191 return 0; 6192} 6193#endif 6194 6195static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6196{ 6197 struct si_power_info *si_pi = si_get_pi(rdev); 6198 u32 tmp; 6199 6200 if (!si_pi->fan_ctrl_is_in_default_mode) { 6201 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6202 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6203 WREG32(CG_FDO_CTRL2, tmp); 6204 6205 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6206 tmp |= TMIN(si_pi->t_min); 6207 WREG32(CG_FDO_CTRL2, tmp); 6208 si_pi->fan_ctrl_is_in_default_mode = true; 6209 } 6210} 6211 6212static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6213{ 6214 if (rdev->pm.dpm.fan.ucode_fan_control) { 6215 si_fan_ctrl_start_smc_fan_control(rdev); 6216 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6217 } 6218} 6219 6220static void si_thermal_initialize(struct radeon_device *rdev) 6221{ 6222 u32 tmp; 6223 6224 if (rdev->pm.fan_pulses_per_revolution) { 6225 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6226 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6227 WREG32(CG_TACH_CTRL, tmp); 6228 } 6229 6230 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6231 tmp |= TACH_PWM_RESP_RATE(0x28); 6232 WREG32(CG_FDO_CTRL2, tmp); 6233} 6234 6235static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6236{ 6237 int ret; 6238 6239 si_thermal_initialize(rdev); 6240 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6241 if (ret) 6242 return ret; 6243 ret = si_thermal_enable_alert(rdev, true); 6244 if (ret) 6245 return ret; 6246 if (rdev->pm.dpm.fan.ucode_fan_control) { 6247 ret = si_halt_smc(rdev); 6248 if (ret) 6249 return ret; 6250 ret = si_thermal_setup_fan_table(rdev); 6251 if (ret) 6252 return ret; 6253 ret = si_resume_smc(rdev); 6254 if (ret) 6255 return ret; 6256 si_thermal_start_smc_fan_control(rdev); 6257 } 6258 6259 return 0; 6260} 6261 6262static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6263{ 6264 if (!rdev->pm.no_fan) { 6265 si_fan_ctrl_set_default_mode(rdev); 6266 si_fan_ctrl_stop_smc_fan_control(rdev); 6267 } 6268} 6269 6270int si_dpm_enable(struct radeon_device *rdev) 6271{ 6272 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6274 struct si_power_info *si_pi = si_get_pi(rdev); 6275 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6276 int ret; 6277 6278 if (si_is_smc_running(rdev)) 6279 return -EINVAL; 6280 if (pi->voltage_control || si_pi->voltage_control_svi2) 6281 si_enable_voltage_control(rdev, true); 6282 if (pi->mvdd_control) 6283 si_get_mvdd_configuration(rdev); 6284 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6285 ret = si_construct_voltage_tables(rdev); 6286 if (ret) { 6287 DRM_ERROR("si_construct_voltage_tables failed\n"); 6288 return ret; 6289 } 6290 } 6291 if (eg_pi->dynamic_ac_timing) { 6292 ret = si_initialize_mc_reg_table(rdev); 6293 if (ret) 6294 eg_pi->dynamic_ac_timing = false; 6295 } 6296 if (pi->dynamic_ss) 6297 si_enable_spread_spectrum(rdev, true); 6298 if (pi->thermal_protection) 6299 si_enable_thermal_protection(rdev, true); 6300 si_setup_bsp(rdev); 6301 si_program_git(rdev); 6302 si_program_tp(rdev); 6303 si_program_tpp(rdev); 6304 si_program_sstp(rdev); 6305 si_enable_display_gap(rdev); 6306 si_program_vc(rdev); 6307 ret = si_upload_firmware(rdev); 6308 if (ret) { 6309 DRM_ERROR("si_upload_firmware failed\n"); 6310 return ret; 6311 } 6312 ret = si_process_firmware_header(rdev); 6313 if (ret) { 6314 DRM_ERROR("si_process_firmware_header failed\n"); 6315 return ret; 6316 } 6317 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6318 if (ret) { 6319 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6320 return ret; 6321 } 6322 ret = si_init_smc_table(rdev); 6323 if (ret) { 6324 DRM_ERROR("si_init_smc_table failed\n"); 6325 return ret; 6326 } 6327 ret = si_init_smc_spll_table(rdev); 6328 if (ret) { 6329 DRM_ERROR("si_init_smc_spll_table failed\n"); 6330 return ret; 6331 } 6332 ret = si_init_arb_table_index(rdev); 6333 if (ret) { 6334 DRM_ERROR("si_init_arb_table_index failed\n"); 6335 return ret; 6336 } 6337 if (eg_pi->dynamic_ac_timing) { 6338 ret = si_populate_mc_reg_table(rdev, boot_ps); 6339 if (ret) { 6340 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6341 return ret; 6342 } 6343 } 6344 ret = si_initialize_smc_cac_tables(rdev); 6345 if (ret) { 6346 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6347 return ret; 6348 } 6349 ret = si_initialize_hardware_cac_manager(rdev); 6350 if (ret) { 6351 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6352 return ret; 6353 } 6354 ret = si_initialize_smc_dte_tables(rdev); 6355 if (ret) { 6356 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6357 return ret; 6358 } 6359 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6360 if (ret) { 6361 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6362 return ret; 6363 } 6364 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6365 if (ret) { 6366 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6367 return ret; 6368 } 6369 si_program_response_times(rdev); 6370 si_program_ds_registers(rdev); 6371 si_dpm_start_smc(rdev); 6372 ret = si_notify_smc_display_change(rdev, false); 6373 if (ret) { 6374 DRM_ERROR("si_notify_smc_display_change failed\n"); 6375 return ret; 6376 } 6377 si_enable_sclk_control(rdev, true); 6378 si_start_dpm(rdev); 6379 6380 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6381 6382 si_thermal_start_thermal_controller(rdev); 6383 6384 ni_update_current_ps(rdev, boot_ps); 6385 6386 return 0; 6387} 6388 6389static int si_set_temperature_range(struct radeon_device *rdev) 6390{ 6391 int ret; 6392 6393 ret = si_thermal_enable_alert(rdev, false); 6394 if (ret) 6395 return ret; 6396 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6397 if (ret) 6398 return ret; 6399 ret = si_thermal_enable_alert(rdev, true); 6400 if (ret) 6401 return ret; 6402 6403 return ret; 6404} 6405 6406int si_dpm_late_enable(struct radeon_device *rdev) 6407{ 6408 int ret; 6409 6410 ret = si_set_temperature_range(rdev); 6411 if (ret) 6412 return ret; 6413 6414 return ret; 6415} 6416 6417void si_dpm_disable(struct radeon_device *rdev) 6418{ 6419 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6420 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6421 6422 if (!si_is_smc_running(rdev)) 6423 return; 6424 si_thermal_stop_thermal_controller(rdev); 6425 si_disable_ulv(rdev); 6426 si_clear_vc(rdev); 6427 if (pi->thermal_protection) 6428 si_enable_thermal_protection(rdev, false); 6429 si_enable_power_containment(rdev, boot_ps, false); 6430 si_enable_smc_cac(rdev, boot_ps, false); 6431 si_enable_spread_spectrum(rdev, false); 6432 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6433 si_stop_dpm(rdev); 6434 si_reset_to_default(rdev); 6435 si_dpm_stop_smc(rdev); 6436 si_force_switch_to_arb_f0(rdev); 6437 6438 ni_update_current_ps(rdev, boot_ps); 6439} 6440 6441int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6442{ 6443 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6444 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6445 struct radeon_ps *new_ps = &requested_ps; 6446 6447 ni_update_requested_ps(rdev, new_ps); 6448 6449 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6450 6451 return 0; 6452} 6453 6454static int si_power_control_set_level(struct radeon_device *rdev) 6455{ 6456 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6457 int ret; 6458 6459 ret = si_restrict_performance_levels_before_switch(rdev); 6460 if (ret) 6461 return ret; 6462 ret = si_halt_smc(rdev); 6463 if (ret) 6464 return ret; 6465 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6466 if (ret) 6467 return ret; 6468 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6469 if (ret) 6470 return ret; 6471 ret = si_resume_smc(rdev); 6472 if (ret) 6473 return ret; 6474 ret = si_set_sw_state(rdev); 6475 if (ret) 6476 return ret; 6477 return 0; 6478} 6479 6480int si_dpm_set_power_state(struct radeon_device *rdev) 6481{ 6482 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6483 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6484 struct radeon_ps *old_ps = &eg_pi->current_rps; 6485 int ret; 6486 6487 ret = si_disable_ulv(rdev); 6488 if (ret) { 6489 DRM_ERROR("si_disable_ulv failed\n"); 6490 return ret; 6491 } 6492 ret = si_restrict_performance_levels_before_switch(rdev); 6493 if (ret) { 6494 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6495 return ret; 6496 } 6497 if (eg_pi->pcie_performance_request) 6498 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6499 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6500 ret = si_enable_power_containment(rdev, new_ps, false); 6501 if (ret) { 6502 DRM_ERROR("si_enable_power_containment failed\n"); 6503 return ret; 6504 } 6505 ret = si_enable_smc_cac(rdev, new_ps, false); 6506 if (ret) { 6507 DRM_ERROR("si_enable_smc_cac failed\n"); 6508 return ret; 6509 } 6510 ret = si_halt_smc(rdev); 6511 if (ret) { 6512 DRM_ERROR("si_halt_smc failed\n"); 6513 return ret; 6514 } 6515 ret = si_upload_sw_state(rdev, new_ps); 6516 if (ret) { 6517 DRM_ERROR("si_upload_sw_state failed\n"); 6518 return ret; 6519 } 6520 ret = si_upload_smc_data(rdev); 6521 if (ret) { 6522 DRM_ERROR("si_upload_smc_data failed\n"); 6523 return ret; 6524 } 6525 ret = si_upload_ulv_state(rdev); 6526 if (ret) { 6527 DRM_ERROR("si_upload_ulv_state failed\n"); 6528 return ret; 6529 } 6530 if (eg_pi->dynamic_ac_timing) { 6531 ret = si_upload_mc_reg_table(rdev, new_ps); 6532 if (ret) { 6533 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6534 return ret; 6535 } 6536 } 6537 ret = si_program_memory_timing_parameters(rdev, new_ps); 6538 if (ret) { 6539 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6540 return ret; 6541 } 6542 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6543 6544 ret = si_resume_smc(rdev); 6545 if (ret) { 6546 DRM_ERROR("si_resume_smc failed\n"); 6547 return ret; 6548 } 6549 ret = si_set_sw_state(rdev); 6550 if (ret) { 6551 DRM_ERROR("si_set_sw_state failed\n"); 6552 return ret; 6553 } 6554 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6555 if (eg_pi->pcie_performance_request) 6556 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6557 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6558 if (ret) { 6559 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6560 return ret; 6561 } 6562 ret = si_enable_smc_cac(rdev, new_ps, true); 6563 if (ret) { 6564 DRM_ERROR("si_enable_smc_cac failed\n"); 6565 return ret; 6566 } 6567 ret = si_enable_power_containment(rdev, new_ps, true); 6568 if (ret) { 6569 DRM_ERROR("si_enable_power_containment failed\n"); 6570 return ret; 6571 } 6572 6573 ret = si_power_control_set_level(rdev); 6574 if (ret) { 6575 DRM_ERROR("si_power_control_set_level failed\n"); 6576 return ret; 6577 } 6578 6579 return 0; 6580} 6581 6582void si_dpm_post_set_power_state(struct radeon_device *rdev) 6583{ 6584 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6585 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6586 6587 ni_update_current_ps(rdev, new_ps); 6588} 6589 6590#if 0 6591void si_dpm_reset_asic(struct radeon_device *rdev) 6592{ 6593 si_restrict_performance_levels_before_switch(rdev); 6594 si_disable_ulv(rdev); 6595 si_set_boot_state(rdev); 6596} 6597#endif 6598 6599void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6600{ 6601 si_program_display_gap(rdev); 6602} 6603 6604union power_info { 6605 struct _ATOM_POWERPLAY_INFO info; 6606 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6607 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6608 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6609 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6610 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6611}; 6612 6613union pplib_clock_info { 6614 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6615 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6616 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6617 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6618 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6619}; 6620 6621union pplib_power_state { 6622 struct _ATOM_PPLIB_STATE v1; 6623 struct _ATOM_PPLIB_STATE_V2 v2; 6624}; 6625 6626static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6627 struct radeon_ps *rps, 6628 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6629 u8 table_rev) 6630{ 6631 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6632 rps->class = le16_to_cpu(non_clock_info->usClassification); 6633 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6634 6635 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6636 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6637 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6638 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6639 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6640 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6641 } else { 6642 rps->vclk = 0; 6643 rps->dclk = 0; 6644 } 6645 6646 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6647 rdev->pm.dpm.boot_ps = rps; 6648 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6649 rdev->pm.dpm.uvd_ps = rps; 6650} 6651 6652static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6653 struct radeon_ps *rps, int index, 6654 union pplib_clock_info *clock_info) 6655{ 6656 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6657 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6658 struct si_power_info *si_pi = si_get_pi(rdev); 6659 struct ni_ps *ps = ni_get_ps(rps); 6660 u16 leakage_voltage; 6661 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6662 int ret; 6663 6664 ps->performance_level_count = index + 1; 6665 6666 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6667 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6668 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6669 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6670 6671 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6672 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6673 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6674 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6675 si_pi->sys_pcie_mask, 6676 si_pi->boot_pcie_gen, 6677 clock_info->si.ucPCIEGen); 6678 6679 /* patch up vddc if necessary */ 6680 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6681 &leakage_voltage); 6682 if (ret == 0) 6683 pl->vddc = leakage_voltage; 6684 6685 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6686 pi->acpi_vddc = pl->vddc; 6687 eg_pi->acpi_vddci = pl->vddci; 6688 si_pi->acpi_pcie_gen = pl->pcie_gen; 6689 } 6690 6691 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6692 index == 0) { 6693 /* XXX disable for A0 tahiti */ 6694 si_pi->ulv.supported = false; 6695 si_pi->ulv.pl = *pl; 6696 si_pi->ulv.one_pcie_lane_in_ulv = false; 6697 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6698 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6699 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6700 } 6701 6702 if (pi->min_vddc_in_table > pl->vddc) 6703 pi->min_vddc_in_table = pl->vddc; 6704 6705 if (pi->max_vddc_in_table < pl->vddc) 6706 pi->max_vddc_in_table = pl->vddc; 6707 6708 /* patch up boot state */ 6709 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6710 u16 vddc, vddci, mvdd; 6711 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6712 pl->mclk = rdev->clock.default_mclk; 6713 pl->sclk = rdev->clock.default_sclk; 6714 pl->vddc = vddc; 6715 pl->vddci = vddci; 6716 si_pi->mvdd_bootup_value = mvdd; 6717 } 6718 6719 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6720 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6721 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6722 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6723 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6724 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6725 } 6726} 6727 6728static int si_parse_power_table(struct radeon_device *rdev) 6729{ 6730 struct radeon_mode_info *mode_info = &rdev->mode_info; 6731 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6732 union pplib_power_state *power_state; 6733 int i, j, k, non_clock_array_index, clock_array_index; 6734 union pplib_clock_info *clock_info; 6735 struct _StateArray *state_array; 6736 struct _ClockInfoArray *clock_info_array; 6737 struct _NonClockInfoArray *non_clock_info_array; 6738 union power_info *power_info; 6739 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6740 u16 data_offset; 6741 u8 frev, crev; 6742 u8 *power_state_offset; 6743 struct ni_ps *ps; 6744 6745 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6746 &frev, &crev, &data_offset)) 6747 return -EINVAL; 6748 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6749 6750 state_array = (struct _StateArray *) 6751 (mode_info->atom_context->bios + data_offset + 6752 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6753 clock_info_array = (struct _ClockInfoArray *) 6754 (mode_info->atom_context->bios + data_offset + 6755 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6756 non_clock_info_array = (struct _NonClockInfoArray *) 6757 (mode_info->atom_context->bios + data_offset + 6758 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6759 6760 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * 6761 state_array->ucNumEntries, GFP_KERNEL); 6762 if (!rdev->pm.dpm.ps) 6763 return -ENOMEM; 6764 power_state_offset = (u8 *)state_array->states; 6765 for (i = 0; i < state_array->ucNumEntries; i++) { 6766 u8 *idx; 6767 power_state = (union pplib_power_state *)power_state_offset; 6768 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6769 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6770 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6771 if (!rdev->pm.power_state[i].clock_info) 6772 return -EINVAL; 6773 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6774 if (ps == NULL) { 6775 kfree(rdev->pm.dpm.ps); 6776 return -ENOMEM; 6777 } 6778 rdev->pm.dpm.ps[i].ps_priv = ps; 6779 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6780 non_clock_info, 6781 non_clock_info_array->ucEntrySize); 6782 k = 0; 6783 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6784 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6785 clock_array_index = idx[j]; 6786 if (clock_array_index >= clock_info_array->ucNumEntries) 6787 continue; 6788 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6789 break; 6790 clock_info = (union pplib_clock_info *) 6791 ((u8 *)&clock_info_array->clockInfo[0] + 6792 (clock_array_index * clock_info_array->ucEntrySize)); 6793 si_parse_pplib_clock_info(rdev, 6794 &rdev->pm.dpm.ps[i], k, 6795 clock_info); 6796 k++; 6797 } 6798 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6799 } 6800 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6801 return 0; 6802} 6803 6804int si_dpm_init(struct radeon_device *rdev) 6805{ 6806 struct rv7xx_power_info *pi; 6807 struct evergreen_power_info *eg_pi; 6808 struct ni_power_info *ni_pi; 6809 struct si_power_info *si_pi; 6810 struct atom_clock_dividers dividers; 6811 int ret; 6812 u32 mask; 6813 6814 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6815 if (si_pi == NULL) 6816 return -ENOMEM; 6817 rdev->pm.dpm.priv = si_pi; 6818 ni_pi = &si_pi->ni; 6819 eg_pi = &ni_pi->eg; 6820 pi = &eg_pi->rv7xx; 6821 6822 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 6823 if (ret) 6824 si_pi->sys_pcie_mask = 0; 6825 else 6826 si_pi->sys_pcie_mask = mask; 6827 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6828 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6829 6830 si_set_max_cu_value(rdev); 6831 6832 rv770_get_max_vddc(rdev); 6833 si_get_leakage_vddc(rdev); 6834 si_patch_dependency_tables_based_on_leakage(rdev); 6835 6836 pi->acpi_vddc = 0; 6837 eg_pi->acpi_vddci = 0; 6838 pi->min_vddc_in_table = 0; 6839 pi->max_vddc_in_table = 0; 6840 6841 ret = r600_get_platform_caps(rdev); 6842 if (ret) 6843 return ret; 6844 6845 ret = si_parse_power_table(rdev); 6846 if (ret) 6847 return ret; 6848 ret = r600_parse_extended_power_table(rdev); 6849 if (ret) 6850 return ret; 6851 6852 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6853 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL); 6854 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6855 r600_free_extended_power_table(rdev); 6856 return -ENOMEM; 6857 } 6858 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6859 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6860 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6861 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6862 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6863 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6864 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6865 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6866 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6867 6868 if (rdev->pm.dpm.voltage_response_time == 0) 6869 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6870 if (rdev->pm.dpm.backbias_response_time == 0) 6871 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6872 6873 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6874 0, false, ÷rs); 6875 if (ret) 6876 pi->ref_div = dividers.ref_div + 1; 6877 else 6878 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6879 6880 eg_pi->smu_uvd_hs = false; 6881 6882 pi->mclk_strobe_mode_threshold = 40000; 6883 if (si_is_special_1gb_platform(rdev)) 6884 pi->mclk_stutter_mode_threshold = 0; 6885 else 6886 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6887 pi->mclk_edc_enable_threshold = 40000; 6888 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6889 6890 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6891 6892 pi->voltage_control = 6893 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6894 VOLTAGE_OBJ_GPIO_LUT); 6895 if (!pi->voltage_control) { 6896 si_pi->voltage_control_svi2 = 6897 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6898 VOLTAGE_OBJ_SVID2); 6899 if (si_pi->voltage_control_svi2) 6900 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6901 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6902 } 6903 6904 pi->mvdd_control = 6905 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6906 VOLTAGE_OBJ_GPIO_LUT); 6907 6908 eg_pi->vddci_control = 6909 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6910 VOLTAGE_OBJ_GPIO_LUT); 6911 if (!eg_pi->vddci_control) 6912 si_pi->vddci_control_svi2 = 6913 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 6914 VOLTAGE_OBJ_SVID2); 6915 6916 si_pi->vddc_phase_shed_control = 6917 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6918 VOLTAGE_OBJ_PHASE_LUT); 6919 6920 rv770_get_engine_memory_ss(rdev); 6921 6922 pi->asi = RV770_ASI_DFLT; 6923 pi->pasi = CYPRESS_HASI_DFLT; 6924 pi->vrc = SISLANDS_VRC_DFLT; 6925 6926 pi->gfx_clock_gating = true; 6927 6928 eg_pi->sclk_deep_sleep = true; 6929 si_pi->sclk_deep_sleep_above_low = false; 6930 6931 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 6932 pi->thermal_protection = true; 6933 else 6934 pi->thermal_protection = false; 6935 6936 eg_pi->dynamic_ac_timing = true; 6937 6938 eg_pi->light_sleep = true; 6939#if defined(CONFIG_ACPI) 6940 eg_pi->pcie_performance_request = 6941 radeon_acpi_is_pcie_performance_request_supported(rdev); 6942#else 6943 eg_pi->pcie_performance_request = false; 6944#endif 6945 6946 si_pi->sram_end = SMC_RAM_END; 6947 6948 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 6949 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 6950 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 6951 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 6952 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 6953 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 6954 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 6955 6956 si_initialize_powertune_defaults(rdev); 6957 6958 /* make sure dc limits are valid */ 6959 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 6960 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 6961 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 6962 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 6963 6964 si_pi->fan_ctrl_is_in_default_mode = true; 6965 6966 return 0; 6967} 6968 6969void si_dpm_fini(struct radeon_device *rdev) 6970{ 6971 int i; 6972 6973 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 6974 kfree(rdev->pm.dpm.ps[i].ps_priv); 6975 } 6976 kfree(rdev->pm.dpm.ps); 6977 kfree(rdev->pm.dpm.priv); 6978 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 6979 r600_free_extended_power_table(rdev); 6980} 6981 6982void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 6983 struct seq_file *m) 6984{ 6985 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6986 struct radeon_ps *rps = &eg_pi->current_rps; 6987 struct ni_ps *ps = ni_get_ps(rps); 6988 struct rv7xx_pl *pl; 6989 u32 current_index = 6990 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 6991 CURRENT_STATE_INDEX_SHIFT; 6992 6993 if (current_index >= ps->performance_level_count) { 6994 seq_printf(m, "invalid dpm profile %d\n", current_index); 6995 } else { 6996 pl = &ps->performance_levels[current_index]; 6997 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 6998 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 6999 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7000 } 7001} 7002 7003u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7004{ 7005 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7006 struct radeon_ps *rps = &eg_pi->current_rps; 7007 struct ni_ps *ps = ni_get_ps(rps); 7008 struct rv7xx_pl *pl; 7009 u32 current_index = 7010 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7011 CURRENT_STATE_INDEX_SHIFT; 7012 7013 if (current_index >= ps->performance_level_count) { 7014 return 0; 7015 } else { 7016 pl = &ps->performance_levels[current_index]; 7017 return pl->sclk; 7018 } 7019} 7020 7021u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7022{ 7023 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7024 struct radeon_ps *rps = &eg_pi->current_rps; 7025 struct ni_ps *ps = ni_get_ps(rps); 7026 struct rv7xx_pl *pl; 7027 u32 current_index = 7028 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7029 CURRENT_STATE_INDEX_SHIFT; 7030 7031 if (current_index >= ps->performance_level_count) { 7032 return 0; 7033 } else { 7034 pl = &ps->performance_levels[current_index]; 7035 return pl->mclk; 7036 } 7037} 7038