1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/of_gpio.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/regulator/consumer.h>
18#include <linux/workqueue.h>
19
20#include <drm/drm_dp_helper.h>
21#include <drm/drm_panel.h>
22
23#include "dpaux.h"
24#include "drm.h"
25
26static DEFINE_MUTEX(dpaux_lock);
27static LIST_HEAD(dpaux_list);
28
29struct tegra_dpaux {
30	struct drm_dp_aux aux;
31	struct device *dev;
32
33	void __iomem *regs;
34	int irq;
35
36	struct tegra_output *output;
37
38	struct reset_control *rst;
39	struct clk *clk_parent;
40	struct clk *clk;
41
42	struct regulator *vdd;
43
44	struct completion complete;
45	struct work_struct work;
46	struct list_head list;
47};
48
49static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
50{
51	return container_of(aux, struct tegra_dpaux, aux);
52}
53
54static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
55{
56	return container_of(work, struct tegra_dpaux, work);
57}
58
59static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
60					      unsigned long offset)
61{
62	return readl(dpaux->regs + (offset << 2));
63}
64
65static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux,
66				      unsigned long value,
67				      unsigned long offset)
68{
69	writel(value, dpaux->regs + (offset << 2));
70}
71
72static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer,
73				   size_t size)
74{
75	size_t i, j;
76
77	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
78		size_t num = min_t(size_t, size - i * 4, 4);
79		unsigned long value = 0;
80
81		for (j = 0; j < num; j++)
82			value |= buffer[i * 4 + j] << (j * 8);
83
84		tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i));
85	}
86}
87
88static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer,
89				  size_t size)
90{
91	size_t i, j;
92
93	for (i = 0; i < DIV_ROUND_UP(size, 4); i++) {
94		size_t num = min_t(size_t, size - i * 4, 4);
95		unsigned long value;
96
97		value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i));
98
99		for (j = 0; j < num; j++)
100			buffer[i * 4 + j] = value >> (j * 8);
101	}
102}
103
104static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
105				    struct drm_dp_aux_msg *msg)
106{
107	unsigned long timeout = msecs_to_jiffies(250);
108	struct tegra_dpaux *dpaux = to_dpaux(aux);
109	unsigned long status;
110	ssize_t ret = 0;
111	u32 value;
112
113	/* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */
114	if (msg->size > 16)
115		return -EINVAL;
116
117	/*
118	 * Allow zero-sized messages only for I2C, in which case they specify
119	 * address-only transactions.
120	 */
121	if (msg->size < 1) {
122		switch (msg->request & ~DP_AUX_I2C_MOT) {
123		case DP_AUX_I2C_WRITE:
124		case DP_AUX_I2C_READ:
125			value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY;
126			break;
127
128		default:
129			return -EINVAL;
130		}
131	} else {
132		/* For non-zero-sized messages, set the CMDLEN field. */
133		value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1);
134	}
135
136	switch (msg->request & ~DP_AUX_I2C_MOT) {
137	case DP_AUX_I2C_WRITE:
138		if (msg->request & DP_AUX_I2C_MOT)
139			value |= DPAUX_DP_AUXCTL_CMD_MOT_WR;
140		else
141			value |= DPAUX_DP_AUXCTL_CMD_I2C_WR;
142
143		break;
144
145	case DP_AUX_I2C_READ:
146		if (msg->request & DP_AUX_I2C_MOT)
147			value |= DPAUX_DP_AUXCTL_CMD_MOT_RD;
148		else
149			value |= DPAUX_DP_AUXCTL_CMD_I2C_RD;
150
151		break;
152
153	case DP_AUX_I2C_STATUS:
154		if (msg->request & DP_AUX_I2C_MOT)
155			value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ;
156		else
157			value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ;
158
159		break;
160
161	case DP_AUX_NATIVE_WRITE:
162		value |= DPAUX_DP_AUXCTL_CMD_AUX_WR;
163		break;
164
165	case DP_AUX_NATIVE_READ:
166		value |= DPAUX_DP_AUXCTL_CMD_AUX_RD;
167		break;
168
169	default:
170		return -EINVAL;
171	}
172
173	tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR);
174	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
175
176	if ((msg->request & DP_AUX_I2C_READ) == 0) {
177		tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size);
178		ret = msg->size;
179	}
180
181	/* start transaction */
182	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL);
183	value |= DPAUX_DP_AUXCTL_TRANSACTREQ;
184	tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL);
185
186	status = wait_for_completion_timeout(&dpaux->complete, timeout);
187	if (!status)
188		return -ETIMEDOUT;
189
190	/* read status and clear errors */
191	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
192	tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT);
193
194	if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR)
195		return -ETIMEDOUT;
196
197	if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) ||
198	    (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) ||
199	    (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR))
200		return -EIO;
201
202	switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) {
203	case 0x00:
204		msg->reply = DP_AUX_NATIVE_REPLY_ACK;
205		break;
206
207	case 0x01:
208		msg->reply = DP_AUX_NATIVE_REPLY_NACK;
209		break;
210
211	case 0x02:
212		msg->reply = DP_AUX_NATIVE_REPLY_DEFER;
213		break;
214
215	case 0x04:
216		msg->reply = DP_AUX_I2C_REPLY_NACK;
217		break;
218
219	case 0x08:
220		msg->reply = DP_AUX_I2C_REPLY_DEFER;
221		break;
222	}
223
224	if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) {
225		if (msg->request & DP_AUX_I2C_READ) {
226			size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK;
227
228			if (WARN_ON(count != msg->size))
229				count = min_t(size_t, count, msg->size);
230
231			tegra_dpaux_read_fifo(dpaux, msg->buffer, count);
232			ret = count;
233		}
234	}
235
236	return ret;
237}
238
239static void tegra_dpaux_hotplug(struct work_struct *work)
240{
241	struct tegra_dpaux *dpaux = work_to_dpaux(work);
242
243	if (dpaux->output)
244		drm_helper_hpd_irq_event(dpaux->output->connector.dev);
245}
246
247static irqreturn_t tegra_dpaux_irq(int irq, void *data)
248{
249	struct tegra_dpaux *dpaux = data;
250	irqreturn_t ret = IRQ_HANDLED;
251	unsigned long value;
252
253	/* clear interrupts */
254	value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
255	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
256
257	if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
258		schedule_work(&dpaux->work);
259
260	if (value & DPAUX_INTR_IRQ_EVENT) {
261		/* TODO: handle this */
262	}
263
264	if (value & DPAUX_INTR_AUX_DONE)
265		complete(&dpaux->complete);
266
267	return ret;
268}
269
270static int tegra_dpaux_probe(struct platform_device *pdev)
271{
272	struct tegra_dpaux *dpaux;
273	struct resource *regs;
274	unsigned long value;
275	int err;
276
277	dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL);
278	if (!dpaux)
279		return -ENOMEM;
280
281	INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
282	init_completion(&dpaux->complete);
283	INIT_LIST_HEAD(&dpaux->list);
284	dpaux->dev = &pdev->dev;
285
286	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
287	dpaux->regs = devm_ioremap_resource(&pdev->dev, regs);
288	if (IS_ERR(dpaux->regs))
289		return PTR_ERR(dpaux->regs);
290
291	dpaux->irq = platform_get_irq(pdev, 0);
292	if (dpaux->irq < 0) {
293		dev_err(&pdev->dev, "failed to get IRQ\n");
294		return -ENXIO;
295	}
296
297	dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
298	if (IS_ERR(dpaux->rst))
299		return PTR_ERR(dpaux->rst);
300
301	dpaux->clk = devm_clk_get(&pdev->dev, NULL);
302	if (IS_ERR(dpaux->clk))
303		return PTR_ERR(dpaux->clk);
304
305	err = clk_prepare_enable(dpaux->clk);
306	if (err < 0)
307		return err;
308
309	reset_control_deassert(dpaux->rst);
310
311	dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
312	if (IS_ERR(dpaux->clk_parent))
313		return PTR_ERR(dpaux->clk_parent);
314
315	err = clk_prepare_enable(dpaux->clk_parent);
316	if (err < 0)
317		return err;
318
319	err = clk_set_rate(dpaux->clk_parent, 270000000);
320	if (err < 0) {
321		dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n",
322			err);
323		return err;
324	}
325
326	dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
327	if (IS_ERR(dpaux->vdd))
328		return PTR_ERR(dpaux->vdd);
329
330	err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
331			       dev_name(dpaux->dev), dpaux);
332	if (err < 0) {
333		dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n",
334			dpaux->irq, err);
335		return err;
336	}
337
338	dpaux->aux.transfer = tegra_dpaux_transfer;
339	dpaux->aux.dev = &pdev->dev;
340
341	err = drm_dp_aux_register(&dpaux->aux);
342	if (err < 0)
343		return err;
344
345	/* enable and clear all interrupts */
346	value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT |
347		DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT;
348	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX);
349	tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
350
351	mutex_lock(&dpaux_lock);
352	list_add_tail(&dpaux->list, &dpaux_list);
353	mutex_unlock(&dpaux_lock);
354
355	platform_set_drvdata(pdev, dpaux);
356
357	return 0;
358}
359
360static int tegra_dpaux_remove(struct platform_device *pdev)
361{
362	struct tegra_dpaux *dpaux = platform_get_drvdata(pdev);
363
364	drm_dp_aux_unregister(&dpaux->aux);
365
366	mutex_lock(&dpaux_lock);
367	list_del(&dpaux->list);
368	mutex_unlock(&dpaux_lock);
369
370	cancel_work_sync(&dpaux->work);
371
372	clk_disable_unprepare(dpaux->clk_parent);
373	reset_control_assert(dpaux->rst);
374	clk_disable_unprepare(dpaux->clk);
375
376	return 0;
377}
378
379static const struct of_device_id tegra_dpaux_of_match[] = {
380	{ .compatible = "nvidia,tegra124-dpaux", },
381	{ },
382};
383MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match);
384
385struct platform_driver tegra_dpaux_driver = {
386	.driver = {
387		.name = "tegra-dpaux",
388		.of_match_table = tegra_dpaux_of_match,
389	},
390	.probe = tegra_dpaux_probe,
391	.remove = tegra_dpaux_remove,
392};
393
394struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np)
395{
396	struct tegra_dpaux *dpaux;
397
398	mutex_lock(&dpaux_lock);
399
400	list_for_each_entry(dpaux, &dpaux_list, list)
401		if (np == dpaux->dev->of_node) {
402			mutex_unlock(&dpaux_lock);
403			return dpaux;
404		}
405
406	mutex_unlock(&dpaux_lock);
407
408	return NULL;
409}
410
411int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
412{
413	unsigned long timeout;
414	int err;
415
416	output->connector.polled = DRM_CONNECTOR_POLL_HPD;
417	dpaux->output = output;
418
419	err = regulator_enable(dpaux->vdd);
420	if (err < 0)
421		return err;
422
423	timeout = jiffies + msecs_to_jiffies(250);
424
425	while (time_before(jiffies, timeout)) {
426		enum drm_connector_status status;
427
428		status = tegra_dpaux_detect(dpaux);
429		if (status == connector_status_connected)
430			return 0;
431
432		usleep_range(1000, 2000);
433	}
434
435	return -ETIMEDOUT;
436}
437
438int tegra_dpaux_detach(struct tegra_dpaux *dpaux)
439{
440	unsigned long timeout;
441	int err;
442
443	err = regulator_disable(dpaux->vdd);
444	if (err < 0)
445		return err;
446
447	timeout = jiffies + msecs_to_jiffies(250);
448
449	while (time_before(jiffies, timeout)) {
450		enum drm_connector_status status;
451
452		status = tegra_dpaux_detect(dpaux);
453		if (status == connector_status_disconnected) {
454			dpaux->output = NULL;
455			return 0;
456		}
457
458		usleep_range(1000, 2000);
459	}
460
461	return -ETIMEDOUT;
462}
463
464enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux)
465{
466	unsigned long value;
467
468	value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT);
469
470	if (value & DPAUX_DP_AUXSTAT_HPD_STATUS)
471		return connector_status_connected;
472
473	return connector_status_disconnected;
474}
475
476int tegra_dpaux_enable(struct tegra_dpaux *dpaux)
477{
478	unsigned long value;
479
480	value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) |
481		DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) |
482		DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) |
483		DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV |
484		DPAUX_HYBRID_PADCTL_MODE_AUX;
485	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL);
486
487	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
488	value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
489	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
490
491	return 0;
492}
493
494int tegra_dpaux_disable(struct tegra_dpaux *dpaux)
495{
496	unsigned long value;
497
498	value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE);
499	value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN;
500	tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE);
501
502	return 0;
503}
504
505int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding)
506{
507	int err;
508
509	err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,
510				 encoding);
511	if (err < 0)
512		return err;
513
514	return 0;
515}
516
517int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link,
518		      u8 pattern)
519{
520	u8 tp = pattern & DP_TRAINING_PATTERN_MASK;
521	u8 status[DP_LINK_STATUS_SIZE], values[4];
522	unsigned int i;
523	int err;
524
525	err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern);
526	if (err < 0)
527		return err;
528
529	if (tp == DP_TRAINING_PATTERN_DISABLE)
530		return 0;
531
532	for (i = 0; i < link->num_lanes; i++)
533		values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED |
534			    DP_TRAIN_PRE_EMPH_LEVEL_0 |
535			    DP_TRAIN_MAX_SWING_REACHED |
536			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
537
538	err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values,
539				link->num_lanes);
540	if (err < 0)
541		return err;
542
543	usleep_range(500, 1000);
544
545	err = drm_dp_dpcd_read_link_status(&dpaux->aux, status);
546	if (err < 0)
547		return err;
548
549	switch (tp) {
550	case DP_TRAINING_PATTERN_1:
551		if (!drm_dp_clock_recovery_ok(status, link->num_lanes))
552			return -EAGAIN;
553
554		break;
555
556	case DP_TRAINING_PATTERN_2:
557		if (!drm_dp_channel_eq_ok(status, link->num_lanes))
558			return -EAGAIN;
559
560		break;
561
562	default:
563		dev_err(dpaux->dev, "unsupported training pattern %u\n", tp);
564		return -EINVAL;
565	}
566
567	err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0);
568	if (err < 0)
569		return err;
570
571	return 0;
572}
573