1/*
2 * Copyright (c) 2014-2015 Imagination Technologies Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include <linux/iio/buffer.h>
22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include <linux/iio/trigger.h>
25#include <linux/iio/trigger_consumer.h>
26#include <linux/iio/triggered_buffer.h>
27
28/* Registers */
29#define CC10001_ADC_CONFIG		0x00
30#define CC10001_ADC_START_CONV		BIT(4)
31#define CC10001_ADC_MODE_SINGLE_CONV	BIT(5)
32
33#define CC10001_ADC_DDATA_OUT		0x04
34#define CC10001_ADC_EOC			0x08
35#define CC10001_ADC_EOC_SET		BIT(0)
36
37#define CC10001_ADC_CHSEL_SAMPLED	0x0c
38#define CC10001_ADC_POWER_DOWN		0x10
39#define CC10001_ADC_POWER_DOWN_SET	BIT(0)
40
41#define CC10001_ADC_DEBUG		0x14
42#define CC10001_ADC_DATA_COUNT		0x20
43
44#define CC10001_ADC_DATA_MASK		GENMASK(9, 0)
45#define CC10001_ADC_NUM_CHANNELS	8
46#define CC10001_ADC_CH_MASK		GENMASK(2, 0)
47
48#define CC10001_INVALID_SAMPLED		0xffff
49#define CC10001_MAX_POLL_COUNT		20
50
51/*
52 * As per device specification, wait six clock cycles after power-up to
53 * activate START. Since adding two more clock cycles delay does not
54 * impact the performance too much, we are adding two additional cycles delay
55 * intentionally here.
56 */
57#define	CC10001_WAIT_CYCLES		8
58
59struct cc10001_adc_device {
60	void __iomem *reg_base;
61	struct clk *adc_clk;
62	struct regulator *reg;
63	u16 *buf;
64
65	struct mutex lock;
66	unsigned int start_delay_ns;
67	unsigned int eoc_delay_ns;
68};
69
70static inline void cc10001_adc_write_reg(struct cc10001_adc_device *adc_dev,
71					 u32 reg, u32 val)
72{
73	writel(val, adc_dev->reg_base + reg);
74}
75
76static inline u32 cc10001_adc_read_reg(struct cc10001_adc_device *adc_dev,
77				       u32 reg)
78{
79	return readl(adc_dev->reg_base + reg);
80}
81
82static void cc10001_adc_power_up(struct cc10001_adc_device *adc_dev)
83{
84	cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN, 0);
85	ndelay(adc_dev->start_delay_ns);
86}
87
88static void cc10001_adc_power_down(struct cc10001_adc_device *adc_dev)
89{
90	cc10001_adc_write_reg(adc_dev, CC10001_ADC_POWER_DOWN,
91			      CC10001_ADC_POWER_DOWN_SET);
92}
93
94static void cc10001_adc_start(struct cc10001_adc_device *adc_dev,
95			      unsigned int channel)
96{
97	u32 val;
98
99	/* Channel selection and mode of operation */
100	val = (channel & CC10001_ADC_CH_MASK) | CC10001_ADC_MODE_SINGLE_CONV;
101	cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
102
103	udelay(1);
104	val = cc10001_adc_read_reg(adc_dev, CC10001_ADC_CONFIG);
105	val = val | CC10001_ADC_START_CONV;
106	cc10001_adc_write_reg(adc_dev, CC10001_ADC_CONFIG, val);
107}
108
109static u16 cc10001_adc_poll_done(struct iio_dev *indio_dev,
110				 unsigned int channel,
111				 unsigned int delay)
112{
113	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
114	unsigned int poll_count = 0;
115
116	while (!(cc10001_adc_read_reg(adc_dev, CC10001_ADC_EOC) &
117			CC10001_ADC_EOC_SET)) {
118
119		ndelay(delay);
120		if (poll_count++ == CC10001_MAX_POLL_COUNT)
121			return CC10001_INVALID_SAMPLED;
122	}
123
124	poll_count = 0;
125	while ((cc10001_adc_read_reg(adc_dev, CC10001_ADC_CHSEL_SAMPLED) &
126			CC10001_ADC_CH_MASK) != channel) {
127
128		ndelay(delay);
129		if (poll_count++ == CC10001_MAX_POLL_COUNT)
130			return CC10001_INVALID_SAMPLED;
131	}
132
133	/* Read the 10 bit output register */
134	return cc10001_adc_read_reg(adc_dev, CC10001_ADC_DDATA_OUT) &
135			       CC10001_ADC_DATA_MASK;
136}
137
138static irqreturn_t cc10001_adc_trigger_h(int irq, void *p)
139{
140	struct cc10001_adc_device *adc_dev;
141	struct iio_poll_func *pf = p;
142	struct iio_dev *indio_dev;
143	unsigned int delay_ns;
144	unsigned int channel;
145	unsigned int scan_idx;
146	bool sample_invalid;
147	u16 *data;
148	int i;
149
150	indio_dev = pf->indio_dev;
151	adc_dev = iio_priv(indio_dev);
152	data = adc_dev->buf;
153
154	mutex_lock(&adc_dev->lock);
155
156	cc10001_adc_power_up(adc_dev);
157
158	/* Calculate delay step for eoc and sampled data */
159	delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
160
161	i = 0;
162	sample_invalid = false;
163	for_each_set_bit(scan_idx, indio_dev->active_scan_mask,
164				  indio_dev->masklength) {
165
166		channel = indio_dev->channels[scan_idx].channel;
167		cc10001_adc_start(adc_dev, channel);
168
169		data[i] = cc10001_adc_poll_done(indio_dev, channel, delay_ns);
170		if (data[i] == CC10001_INVALID_SAMPLED) {
171			dev_warn(&indio_dev->dev,
172				 "invalid sample on channel %d\n", channel);
173			sample_invalid = true;
174			goto done;
175		}
176		i++;
177	}
178
179done:
180	cc10001_adc_power_down(adc_dev);
181
182	mutex_unlock(&adc_dev->lock);
183
184	if (!sample_invalid)
185		iio_push_to_buffers_with_timestamp(indio_dev, data,
186						   iio_get_time_ns());
187	iio_trigger_notify_done(indio_dev->trig);
188
189	return IRQ_HANDLED;
190}
191
192static u16 cc10001_adc_read_raw_voltage(struct iio_dev *indio_dev,
193					struct iio_chan_spec const *chan)
194{
195	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
196	unsigned int delay_ns;
197	u16 val;
198
199	cc10001_adc_power_up(adc_dev);
200
201	/* Calculate delay step for eoc and sampled data */
202	delay_ns = adc_dev->eoc_delay_ns / CC10001_MAX_POLL_COUNT;
203
204	cc10001_adc_start(adc_dev, chan->channel);
205
206	val = cc10001_adc_poll_done(indio_dev, chan->channel, delay_ns);
207
208	cc10001_adc_power_down(adc_dev);
209
210	return val;
211}
212
213static int cc10001_adc_read_raw(struct iio_dev *indio_dev,
214				 struct iio_chan_spec const *chan,
215				 int *val, int *val2, long mask)
216{
217	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
218	int ret;
219
220	switch (mask) {
221	case IIO_CHAN_INFO_RAW:
222		if (iio_buffer_enabled(indio_dev))
223			return -EBUSY;
224		mutex_lock(&adc_dev->lock);
225		*val = cc10001_adc_read_raw_voltage(indio_dev, chan);
226		mutex_unlock(&adc_dev->lock);
227
228		if (*val == CC10001_INVALID_SAMPLED)
229			return -EIO;
230		return IIO_VAL_INT;
231
232	case IIO_CHAN_INFO_SCALE:
233		ret = regulator_get_voltage(adc_dev->reg);
234		if (ret < 0)
235			return ret;
236
237		*val = ret / 1000;
238		*val2 = chan->scan_type.realbits;
239		return IIO_VAL_FRACTIONAL_LOG2;
240
241	default:
242		return -EINVAL;
243	}
244}
245
246static int cc10001_update_scan_mode(struct iio_dev *indio_dev,
247				    const unsigned long *scan_mask)
248{
249	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
250
251	kfree(adc_dev->buf);
252	adc_dev->buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
253	if (!adc_dev->buf)
254		return -ENOMEM;
255
256	return 0;
257}
258
259static const struct iio_info cc10001_adc_info = {
260	.driver_module = THIS_MODULE,
261	.read_raw = &cc10001_adc_read_raw,
262	.update_scan_mode = &cc10001_update_scan_mode,
263};
264
265static int cc10001_adc_channel_init(struct iio_dev *indio_dev,
266				    unsigned long channel_map)
267{
268	struct iio_chan_spec *chan_array, *timestamp;
269	unsigned int bit, idx = 0;
270
271	indio_dev->num_channels = bitmap_weight(&channel_map,
272						CC10001_ADC_NUM_CHANNELS) + 1;
273
274	chan_array = devm_kcalloc(&indio_dev->dev, indio_dev->num_channels,
275				  sizeof(struct iio_chan_spec),
276				  GFP_KERNEL);
277	if (!chan_array)
278		return -ENOMEM;
279
280	for_each_set_bit(bit, &channel_map, CC10001_ADC_NUM_CHANNELS) {
281		struct iio_chan_spec *chan = &chan_array[idx];
282
283		chan->type = IIO_VOLTAGE;
284		chan->indexed = 1;
285		chan->channel = bit;
286		chan->scan_index = idx;
287		chan->scan_type.sign = 'u';
288		chan->scan_type.realbits = 10;
289		chan->scan_type.storagebits = 16;
290		chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
291		chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
292		idx++;
293	}
294
295	timestamp = &chan_array[idx];
296	timestamp->type = IIO_TIMESTAMP;
297	timestamp->channel = -1;
298	timestamp->scan_index = idx;
299	timestamp->scan_type.sign = 's';
300	timestamp->scan_type.realbits = 64;
301	timestamp->scan_type.storagebits = 64;
302
303	indio_dev->channels = chan_array;
304
305	return 0;
306}
307
308static int cc10001_adc_probe(struct platform_device *pdev)
309{
310	struct device_node *node = pdev->dev.of_node;
311	struct cc10001_adc_device *adc_dev;
312	unsigned long adc_clk_rate;
313	struct resource *res;
314	struct iio_dev *indio_dev;
315	unsigned long channel_map;
316	int ret;
317
318	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
319	if (indio_dev == NULL)
320		return -ENOMEM;
321
322	adc_dev = iio_priv(indio_dev);
323
324	channel_map = GENMASK(CC10001_ADC_NUM_CHANNELS - 1, 0);
325	if (!of_property_read_u32(node, "adc-reserved-channels", &ret))
326		channel_map &= ~ret;
327
328	adc_dev->reg = devm_regulator_get(&pdev->dev, "vref");
329	if (IS_ERR(adc_dev->reg))
330		return PTR_ERR(adc_dev->reg);
331
332	ret = regulator_enable(adc_dev->reg);
333	if (ret)
334		return ret;
335
336	indio_dev->dev.parent = &pdev->dev;
337	indio_dev->name = dev_name(&pdev->dev);
338	indio_dev->info = &cc10001_adc_info;
339	indio_dev->modes = INDIO_DIRECT_MODE;
340
341	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342	adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res);
343	if (IS_ERR(adc_dev->reg_base)) {
344		ret = PTR_ERR(adc_dev->reg_base);
345		goto err_disable_reg;
346	}
347
348	adc_dev->adc_clk = devm_clk_get(&pdev->dev, "adc");
349	if (IS_ERR(adc_dev->adc_clk)) {
350		dev_err(&pdev->dev, "failed to get the clock\n");
351		ret = PTR_ERR(adc_dev->adc_clk);
352		goto err_disable_reg;
353	}
354
355	ret = clk_prepare_enable(adc_dev->adc_clk);
356	if (ret) {
357		dev_err(&pdev->dev, "failed to enable the clock\n");
358		goto err_disable_reg;
359	}
360
361	adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
362	if (!adc_clk_rate) {
363		ret = -EINVAL;
364		dev_err(&pdev->dev, "null clock rate!\n");
365		goto err_disable_clk;
366	}
367
368	adc_dev->eoc_delay_ns = NSEC_PER_SEC / adc_clk_rate;
369	adc_dev->start_delay_ns = adc_dev->eoc_delay_ns * CC10001_WAIT_CYCLES;
370
371	/* Setup the ADC channels available on the device */
372	ret = cc10001_adc_channel_init(indio_dev, channel_map);
373	if (ret < 0)
374		goto err_disable_clk;
375
376	mutex_init(&adc_dev->lock);
377
378	ret = iio_triggered_buffer_setup(indio_dev, NULL,
379					 &cc10001_adc_trigger_h, NULL);
380	if (ret < 0)
381		goto err_disable_clk;
382
383	ret = iio_device_register(indio_dev);
384	if (ret < 0)
385		goto err_cleanup_buffer;
386
387	platform_set_drvdata(pdev, indio_dev);
388
389	return 0;
390
391err_cleanup_buffer:
392	iio_triggered_buffer_cleanup(indio_dev);
393err_disable_clk:
394	clk_disable_unprepare(adc_dev->adc_clk);
395err_disable_reg:
396	regulator_disable(adc_dev->reg);
397	return ret;
398}
399
400static int cc10001_adc_remove(struct platform_device *pdev)
401{
402	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
403	struct cc10001_adc_device *adc_dev = iio_priv(indio_dev);
404
405	iio_device_unregister(indio_dev);
406	iio_triggered_buffer_cleanup(indio_dev);
407	clk_disable_unprepare(adc_dev->adc_clk);
408	regulator_disable(adc_dev->reg);
409
410	return 0;
411}
412
413static const struct of_device_id cc10001_adc_dt_ids[] = {
414	{ .compatible = "cosmic,10001-adc", },
415	{ }
416};
417MODULE_DEVICE_TABLE(of, cc10001_adc_dt_ids);
418
419static struct platform_driver cc10001_adc_driver = {
420	.driver = {
421		.name   = "cc10001-adc",
422		.of_match_table = cc10001_adc_dt_ids,
423	},
424	.probe	= cc10001_adc_probe,
425	.remove	= cc10001_adc_remove,
426};
427module_platform_driver(cc10001_adc_driver);
428
429MODULE_AUTHOR("Phani Movva <Phani.Movva@imgtec.com>");
430MODULE_DESCRIPTION("Cosmic Circuits ADC driver");
431MODULE_LICENSE("GPL v2");
432