1/* 2 * exynos_adc.c - Support for ADC in EXYNOS SoCs 3 * 4 * 8 ~ 10 channel, 10/12-bit ADC 5 * 6 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#include <linux/module.h> 24#include <linux/platform_device.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27#include <linux/errno.h> 28#include <linux/kernel.h> 29#include <linux/slab.h> 30#include <linux/io.h> 31#include <linux/clk.h> 32#include <linux/completion.h> 33#include <linux/of.h> 34#include <linux/of_irq.h> 35#include <linux/regulator/consumer.h> 36#include <linux/of_platform.h> 37#include <linux/err.h> 38 39#include <linux/iio/iio.h> 40#include <linux/iio/machine.h> 41#include <linux/iio/driver.h> 42#include <linux/mfd/syscon.h> 43#include <linux/regmap.h> 44 45/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */ 46#define ADC_V1_CON(x) ((x) + 0x00) 47#define ADC_V1_DLY(x) ((x) + 0x08) 48#define ADC_V1_DATX(x) ((x) + 0x0C) 49#define ADC_V1_INTCLR(x) ((x) + 0x18) 50#define ADC_V1_MUX(x) ((x) + 0x1c) 51 52/* S3C2410 ADC registers definitions */ 53#define ADC_S3C2410_MUX(x) ((x) + 0x18) 54 55/* Future ADC_V2 registers definitions */ 56#define ADC_V2_CON1(x) ((x) + 0x00) 57#define ADC_V2_CON2(x) ((x) + 0x04) 58#define ADC_V2_STAT(x) ((x) + 0x08) 59#define ADC_V2_INT_EN(x) ((x) + 0x10) 60#define ADC_V2_INT_ST(x) ((x) + 0x14) 61#define ADC_V2_VER(x) ((x) + 0x20) 62 63/* Bit definitions for ADC_V1 */ 64#define ADC_V1_CON_RES (1u << 16) 65#define ADC_V1_CON_PRSCEN (1u << 14) 66#define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6) 67#define ADC_V1_CON_STANDBY (1u << 2) 68 69/* Bit definitions for S3C2410 ADC */ 70#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3) 71#define ADC_S3C2410_DATX_MASK 0x3FF 72#define ADC_S3C2416_CON_RES_SEL (1u << 3) 73 74/* Bit definitions for ADC_V2 */ 75#define ADC_V2_CON1_SOFT_RESET (1u << 2) 76 77#define ADC_V2_CON2_OSEL (1u << 10) 78#define ADC_V2_CON2_ESEL (1u << 9) 79#define ADC_V2_CON2_HIGHF (1u << 8) 80#define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4) 81#define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) 82#define ADC_V2_CON2_ACH_MASK 0xF 83 84#define MAX_ADC_V2_CHANNELS 10 85#define MAX_ADC_V1_CHANNELS 8 86#define MAX_EXYNOS3250_ADC_CHANNELS 2 87 88/* Bit definitions common for ADC_V1 and ADC_V2 */ 89#define ADC_CON_EN_START (1u << 0) 90#define ADC_CON_EN_START_MASK (0x3 << 0) 91#define ADC_DATX_MASK 0xFFF 92 93#define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100)) 94 95#define EXYNOS_ADCV1_PHY_OFFSET 0x0718 96#define EXYNOS_ADCV2_PHY_OFFSET 0x0720 97 98struct exynos_adc { 99 struct exynos_adc_data *data; 100 struct device *dev; 101 void __iomem *regs; 102 struct regmap *pmu_map; 103 struct clk *clk; 104 struct clk *sclk; 105 unsigned int irq; 106 struct regulator *vdd; 107 108 struct completion completion; 109 110 u32 value; 111 unsigned int version; 112}; 113 114struct exynos_adc_data { 115 int num_channels; 116 bool needs_sclk; 117 bool needs_adc_phy; 118 int phy_offset; 119 u32 mask; 120 121 void (*init_hw)(struct exynos_adc *info); 122 void (*exit_hw)(struct exynos_adc *info); 123 void (*clear_irq)(struct exynos_adc *info); 124 void (*start_conv)(struct exynos_adc *info, unsigned long addr); 125}; 126 127static void exynos_adc_unprepare_clk(struct exynos_adc *info) 128{ 129 if (info->data->needs_sclk) 130 clk_unprepare(info->sclk); 131 clk_unprepare(info->clk); 132} 133 134static int exynos_adc_prepare_clk(struct exynos_adc *info) 135{ 136 int ret; 137 138 ret = clk_prepare(info->clk); 139 if (ret) { 140 dev_err(info->dev, "failed preparing adc clock: %d\n", ret); 141 return ret; 142 } 143 144 if (info->data->needs_sclk) { 145 ret = clk_prepare(info->sclk); 146 if (ret) { 147 clk_unprepare(info->clk); 148 dev_err(info->dev, 149 "failed preparing sclk_adc clock: %d\n", ret); 150 return ret; 151 } 152 } 153 154 return 0; 155} 156 157static void exynos_adc_disable_clk(struct exynos_adc *info) 158{ 159 if (info->data->needs_sclk) 160 clk_disable(info->sclk); 161 clk_disable(info->clk); 162} 163 164static int exynos_adc_enable_clk(struct exynos_adc *info) 165{ 166 int ret; 167 168 ret = clk_enable(info->clk); 169 if (ret) { 170 dev_err(info->dev, "failed enabling adc clock: %d\n", ret); 171 return ret; 172 } 173 174 if (info->data->needs_sclk) { 175 ret = clk_enable(info->sclk); 176 if (ret) { 177 clk_disable(info->clk); 178 dev_err(info->dev, 179 "failed enabling sclk_adc clock: %d\n", ret); 180 return ret; 181 } 182 } 183 184 return 0; 185} 186 187static void exynos_adc_v1_init_hw(struct exynos_adc *info) 188{ 189 u32 con1; 190 191 if (info->data->needs_adc_phy) 192 regmap_write(info->pmu_map, info->data->phy_offset, 1); 193 194 /* set default prescaler values and Enable prescaler */ 195 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; 196 197 /* Enable 12-bit ADC resolution */ 198 con1 |= ADC_V1_CON_RES; 199 writel(con1, ADC_V1_CON(info->regs)); 200} 201 202static void exynos_adc_v1_exit_hw(struct exynos_adc *info) 203{ 204 u32 con; 205 206 if (info->data->needs_adc_phy) 207 regmap_write(info->pmu_map, info->data->phy_offset, 0); 208 209 con = readl(ADC_V1_CON(info->regs)); 210 con |= ADC_V1_CON_STANDBY; 211 writel(con, ADC_V1_CON(info->regs)); 212} 213 214static void exynos_adc_v1_clear_irq(struct exynos_adc *info) 215{ 216 writel(1, ADC_V1_INTCLR(info->regs)); 217} 218 219static void exynos_adc_v1_start_conv(struct exynos_adc *info, 220 unsigned long addr) 221{ 222 u32 con1; 223 224 writel(addr, ADC_V1_MUX(info->regs)); 225 226 con1 = readl(ADC_V1_CON(info->regs)); 227 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 228} 229 230static const struct exynos_adc_data exynos_adc_v1_data = { 231 .num_channels = MAX_ADC_V1_CHANNELS, 232 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 233 .needs_adc_phy = true, 234 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET, 235 236 .init_hw = exynos_adc_v1_init_hw, 237 .exit_hw = exynos_adc_v1_exit_hw, 238 .clear_irq = exynos_adc_v1_clear_irq, 239 .start_conv = exynos_adc_v1_start_conv, 240}; 241 242static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info, 243 unsigned long addr) 244{ 245 u32 con1; 246 247 /* Enable 12 bit ADC resolution */ 248 con1 = readl(ADC_V1_CON(info->regs)); 249 con1 |= ADC_S3C2416_CON_RES_SEL; 250 writel(con1, ADC_V1_CON(info->regs)); 251 252 /* Select channel for S3C2416 */ 253 writel(addr, ADC_S3C2410_MUX(info->regs)); 254 255 con1 = readl(ADC_V1_CON(info->regs)); 256 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 257} 258 259static struct exynos_adc_data const exynos_adc_s3c2416_data = { 260 .num_channels = MAX_ADC_V1_CHANNELS, 261 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 262 263 .init_hw = exynos_adc_v1_init_hw, 264 .exit_hw = exynos_adc_v1_exit_hw, 265 .start_conv = exynos_adc_s3c2416_start_conv, 266}; 267 268static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info, 269 unsigned long addr) 270{ 271 u32 con1; 272 273 /* Select channel for S3C2433 */ 274 writel(addr, ADC_S3C2410_MUX(info->regs)); 275 276 con1 = readl(ADC_V1_CON(info->regs)); 277 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 278} 279 280static struct exynos_adc_data const exynos_adc_s3c2443_data = { 281 .num_channels = MAX_ADC_V1_CHANNELS, 282 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ 283 284 .init_hw = exynos_adc_v1_init_hw, 285 .exit_hw = exynos_adc_v1_exit_hw, 286 .start_conv = exynos_adc_s3c2443_start_conv, 287}; 288 289static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info, 290 unsigned long addr) 291{ 292 u32 con1; 293 294 con1 = readl(ADC_V1_CON(info->regs)); 295 con1 &= ~ADC_S3C2410_CON_SELMUX(0x7); 296 con1 |= ADC_S3C2410_CON_SELMUX(addr); 297 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 298} 299 300static struct exynos_adc_data const exynos_adc_s3c24xx_data = { 301 .num_channels = MAX_ADC_V1_CHANNELS, 302 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ 303 304 .init_hw = exynos_adc_v1_init_hw, 305 .exit_hw = exynos_adc_v1_exit_hw, 306 .start_conv = exynos_adc_s3c64xx_start_conv, 307}; 308 309static struct exynos_adc_data const exynos_adc_s3c64xx_data = { 310 .num_channels = MAX_ADC_V1_CHANNELS, 311 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 312 313 .init_hw = exynos_adc_v1_init_hw, 314 .exit_hw = exynos_adc_v1_exit_hw, 315 .clear_irq = exynos_adc_v1_clear_irq, 316 .start_conv = exynos_adc_s3c64xx_start_conv, 317}; 318 319static void exynos_adc_v2_init_hw(struct exynos_adc *info) 320{ 321 u32 con1, con2; 322 323 if (info->data->needs_adc_phy) 324 regmap_write(info->pmu_map, info->data->phy_offset, 1); 325 326 con1 = ADC_V2_CON1_SOFT_RESET; 327 writel(con1, ADC_V2_CON1(info->regs)); 328 329 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | 330 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); 331 writel(con2, ADC_V2_CON2(info->regs)); 332 333 /* Enable interrupts */ 334 writel(1, ADC_V2_INT_EN(info->regs)); 335} 336 337static void exynos_adc_v2_exit_hw(struct exynos_adc *info) 338{ 339 u32 con; 340 341 if (info->data->needs_adc_phy) 342 regmap_write(info->pmu_map, info->data->phy_offset, 0); 343 344 con = readl(ADC_V2_CON1(info->regs)); 345 con &= ~ADC_CON_EN_START; 346 writel(con, ADC_V2_CON1(info->regs)); 347} 348 349static void exynos_adc_v2_clear_irq(struct exynos_adc *info) 350{ 351 writel(1, ADC_V2_INT_ST(info->regs)); 352} 353 354static void exynos_adc_v2_start_conv(struct exynos_adc *info, 355 unsigned long addr) 356{ 357 u32 con1, con2; 358 359 con2 = readl(ADC_V2_CON2(info->regs)); 360 con2 &= ~ADC_V2_CON2_ACH_MASK; 361 con2 |= ADC_V2_CON2_ACH_SEL(addr); 362 writel(con2, ADC_V2_CON2(info->regs)); 363 364 con1 = readl(ADC_V2_CON1(info->regs)); 365 writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs)); 366} 367 368static const struct exynos_adc_data exynos_adc_v2_data = { 369 .num_channels = MAX_ADC_V2_CHANNELS, 370 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 371 .needs_adc_phy = true, 372 .phy_offset = EXYNOS_ADCV2_PHY_OFFSET, 373 374 .init_hw = exynos_adc_v2_init_hw, 375 .exit_hw = exynos_adc_v2_exit_hw, 376 .clear_irq = exynos_adc_v2_clear_irq, 377 .start_conv = exynos_adc_v2_start_conv, 378}; 379 380static const struct exynos_adc_data exynos3250_adc_data = { 381 .num_channels = MAX_EXYNOS3250_ADC_CHANNELS, 382 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 383 .needs_sclk = true, 384 .needs_adc_phy = true, 385 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET, 386 387 .init_hw = exynos_adc_v2_init_hw, 388 .exit_hw = exynos_adc_v2_exit_hw, 389 .clear_irq = exynos_adc_v2_clear_irq, 390 .start_conv = exynos_adc_v2_start_conv, 391}; 392 393static void exynos_adc_exynos7_init_hw(struct exynos_adc *info) 394{ 395 u32 con1, con2; 396 397 if (info->data->needs_adc_phy) 398 regmap_write(info->pmu_map, info->data->phy_offset, 1); 399 400 con1 = ADC_V2_CON1_SOFT_RESET; 401 writel(con1, ADC_V2_CON1(info->regs)); 402 403 con2 = readl(ADC_V2_CON2(info->regs)); 404 con2 &= ~ADC_V2_CON2_C_TIME(7); 405 con2 |= ADC_V2_CON2_C_TIME(0); 406 writel(con2, ADC_V2_CON2(info->regs)); 407 408 /* Enable interrupts */ 409 writel(1, ADC_V2_INT_EN(info->regs)); 410} 411 412static const struct exynos_adc_data exynos7_adc_data = { 413 .num_channels = MAX_ADC_V1_CHANNELS, 414 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 415 416 .init_hw = exynos_adc_exynos7_init_hw, 417 .exit_hw = exynos_adc_v2_exit_hw, 418 .clear_irq = exynos_adc_v2_clear_irq, 419 .start_conv = exynos_adc_v2_start_conv, 420}; 421 422static const struct of_device_id exynos_adc_match[] = { 423 { 424 .compatible = "samsung,s3c2410-adc", 425 .data = &exynos_adc_s3c24xx_data, 426 }, { 427 .compatible = "samsung,s3c2416-adc", 428 .data = &exynos_adc_s3c2416_data, 429 }, { 430 .compatible = "samsung,s3c2440-adc", 431 .data = &exynos_adc_s3c24xx_data, 432 }, { 433 .compatible = "samsung,s3c2443-adc", 434 .data = &exynos_adc_s3c2443_data, 435 }, { 436 .compatible = "samsung,s3c6410-adc", 437 .data = &exynos_adc_s3c64xx_data, 438 }, { 439 .compatible = "samsung,exynos-adc-v1", 440 .data = &exynos_adc_v1_data, 441 }, { 442 .compatible = "samsung,exynos-adc-v2", 443 .data = &exynos_adc_v2_data, 444 }, { 445 .compatible = "samsung,exynos3250-adc", 446 .data = &exynos3250_adc_data, 447 }, { 448 .compatible = "samsung,exynos7-adc", 449 .data = &exynos7_adc_data, 450 }, 451 {}, 452}; 453MODULE_DEVICE_TABLE(of, exynos_adc_match); 454 455static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev) 456{ 457 const struct of_device_id *match; 458 459 match = of_match_node(exynos_adc_match, pdev->dev.of_node); 460 return (struct exynos_adc_data *)match->data; 461} 462 463static int exynos_read_raw(struct iio_dev *indio_dev, 464 struct iio_chan_spec const *chan, 465 int *val, 466 int *val2, 467 long mask) 468{ 469 struct exynos_adc *info = iio_priv(indio_dev); 470 unsigned long timeout; 471 int ret; 472 473 if (mask != IIO_CHAN_INFO_RAW) 474 return -EINVAL; 475 476 mutex_lock(&indio_dev->mlock); 477 reinit_completion(&info->completion); 478 479 /* Select the channel to be used and Trigger conversion */ 480 if (info->data->start_conv) 481 info->data->start_conv(info, chan->address); 482 483 timeout = wait_for_completion_timeout 484 (&info->completion, EXYNOS_ADC_TIMEOUT); 485 if (timeout == 0) { 486 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n"); 487 if (info->data->init_hw) 488 info->data->init_hw(info); 489 ret = -ETIMEDOUT; 490 } else { 491 *val = info->value; 492 *val2 = 0; 493 ret = IIO_VAL_INT; 494 } 495 496 mutex_unlock(&indio_dev->mlock); 497 498 return ret; 499} 500 501static irqreturn_t exynos_adc_isr(int irq, void *dev_id) 502{ 503 struct exynos_adc *info = (struct exynos_adc *)dev_id; 504 u32 mask = info->data->mask; 505 506 /* Read value */ 507 info->value = readl(ADC_V1_DATX(info->regs)) & mask; 508 509 /* clear irq */ 510 if (info->data->clear_irq) 511 info->data->clear_irq(info); 512 513 complete(&info->completion); 514 515 return IRQ_HANDLED; 516} 517 518static int exynos_adc_reg_access(struct iio_dev *indio_dev, 519 unsigned reg, unsigned writeval, 520 unsigned *readval) 521{ 522 struct exynos_adc *info = iio_priv(indio_dev); 523 524 if (readval == NULL) 525 return -EINVAL; 526 527 *readval = readl(info->regs + reg); 528 529 return 0; 530} 531 532static const struct iio_info exynos_adc_iio_info = { 533 .read_raw = &exynos_read_raw, 534 .debugfs_reg_access = &exynos_adc_reg_access, 535 .driver_module = THIS_MODULE, 536}; 537 538#define ADC_CHANNEL(_index, _id) { \ 539 .type = IIO_VOLTAGE, \ 540 .indexed = 1, \ 541 .channel = _index, \ 542 .address = _index, \ 543 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 544 .datasheet_name = _id, \ 545} 546 547static const struct iio_chan_spec exynos_adc_iio_channels[] = { 548 ADC_CHANNEL(0, "adc0"), 549 ADC_CHANNEL(1, "adc1"), 550 ADC_CHANNEL(2, "adc2"), 551 ADC_CHANNEL(3, "adc3"), 552 ADC_CHANNEL(4, "adc4"), 553 ADC_CHANNEL(5, "adc5"), 554 ADC_CHANNEL(6, "adc6"), 555 ADC_CHANNEL(7, "adc7"), 556 ADC_CHANNEL(8, "adc8"), 557 ADC_CHANNEL(9, "adc9"), 558}; 559 560static int exynos_adc_remove_devices(struct device *dev, void *c) 561{ 562 struct platform_device *pdev = to_platform_device(dev); 563 564 platform_device_unregister(pdev); 565 566 return 0; 567} 568 569static int exynos_adc_probe(struct platform_device *pdev) 570{ 571 struct exynos_adc *info = NULL; 572 struct device_node *np = pdev->dev.of_node; 573 struct iio_dev *indio_dev = NULL; 574 struct resource *mem; 575 int ret = -ENODEV; 576 int irq; 577 578 if (!np) 579 return ret; 580 581 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc)); 582 if (!indio_dev) { 583 dev_err(&pdev->dev, "failed allocating iio device\n"); 584 return -ENOMEM; 585 } 586 587 info = iio_priv(indio_dev); 588 589 info->data = exynos_adc_get_data(pdev); 590 if (!info->data) { 591 dev_err(&pdev->dev, "failed getting exynos_adc_data\n"); 592 return -EINVAL; 593 } 594 595 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 596 info->regs = devm_ioremap_resource(&pdev->dev, mem); 597 if (IS_ERR(info->regs)) 598 return PTR_ERR(info->regs); 599 600 601 if (info->data->needs_adc_phy) { 602 info->pmu_map = syscon_regmap_lookup_by_phandle( 603 pdev->dev.of_node, 604 "samsung,syscon-phandle"); 605 if (IS_ERR(info->pmu_map)) { 606 dev_err(&pdev->dev, "syscon regmap lookup failed.\n"); 607 return PTR_ERR(info->pmu_map); 608 } 609 } 610 611 irq = platform_get_irq(pdev, 0); 612 if (irq < 0) { 613 dev_err(&pdev->dev, "no irq resource?\n"); 614 return irq; 615 } 616 617 info->irq = irq; 618 info->dev = &pdev->dev; 619 620 init_completion(&info->completion); 621 622 info->clk = devm_clk_get(&pdev->dev, "adc"); 623 if (IS_ERR(info->clk)) { 624 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 625 PTR_ERR(info->clk)); 626 return PTR_ERR(info->clk); 627 } 628 629 if (info->data->needs_sclk) { 630 info->sclk = devm_clk_get(&pdev->dev, "sclk"); 631 if (IS_ERR(info->sclk)) { 632 dev_err(&pdev->dev, 633 "failed getting sclk clock, err = %ld\n", 634 PTR_ERR(info->sclk)); 635 return PTR_ERR(info->sclk); 636 } 637 } 638 639 info->vdd = devm_regulator_get(&pdev->dev, "vdd"); 640 if (IS_ERR(info->vdd)) { 641 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n", 642 PTR_ERR(info->vdd)); 643 return PTR_ERR(info->vdd); 644 } 645 646 ret = regulator_enable(info->vdd); 647 if (ret) 648 return ret; 649 650 ret = exynos_adc_prepare_clk(info); 651 if (ret) 652 goto err_disable_reg; 653 654 ret = exynos_adc_enable_clk(info); 655 if (ret) 656 goto err_unprepare_clk; 657 658 platform_set_drvdata(pdev, indio_dev); 659 660 indio_dev->name = dev_name(&pdev->dev); 661 indio_dev->dev.parent = &pdev->dev; 662 indio_dev->dev.of_node = pdev->dev.of_node; 663 indio_dev->info = &exynos_adc_iio_info; 664 indio_dev->modes = INDIO_DIRECT_MODE; 665 indio_dev->channels = exynos_adc_iio_channels; 666 indio_dev->num_channels = info->data->num_channels; 667 668 ret = request_irq(info->irq, exynos_adc_isr, 669 0, dev_name(&pdev->dev), info); 670 if (ret < 0) { 671 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", 672 info->irq); 673 goto err_disable_clk; 674 } 675 676 ret = iio_device_register(indio_dev); 677 if (ret) 678 goto err_irq; 679 680 if (info->data->init_hw) 681 info->data->init_hw(info); 682 683 ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev); 684 if (ret < 0) { 685 dev_err(&pdev->dev, "failed adding child nodes\n"); 686 goto err_of_populate; 687 } 688 689 return 0; 690 691err_of_populate: 692 device_for_each_child(&indio_dev->dev, NULL, 693 exynos_adc_remove_devices); 694 iio_device_unregister(indio_dev); 695err_irq: 696 free_irq(info->irq, info); 697err_disable_clk: 698 if (info->data->exit_hw) 699 info->data->exit_hw(info); 700 exynos_adc_disable_clk(info); 701err_unprepare_clk: 702 exynos_adc_unprepare_clk(info); 703err_disable_reg: 704 regulator_disable(info->vdd); 705 return ret; 706} 707 708static int exynos_adc_remove(struct platform_device *pdev) 709{ 710 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 711 struct exynos_adc *info = iio_priv(indio_dev); 712 713 device_for_each_child(&indio_dev->dev, NULL, 714 exynos_adc_remove_devices); 715 iio_device_unregister(indio_dev); 716 free_irq(info->irq, info); 717 if (info->data->exit_hw) 718 info->data->exit_hw(info); 719 exynos_adc_disable_clk(info); 720 exynos_adc_unprepare_clk(info); 721 regulator_disable(info->vdd); 722 723 return 0; 724} 725 726#ifdef CONFIG_PM_SLEEP 727static int exynos_adc_suspend(struct device *dev) 728{ 729 struct iio_dev *indio_dev = dev_get_drvdata(dev); 730 struct exynos_adc *info = iio_priv(indio_dev); 731 732 if (info->data->exit_hw) 733 info->data->exit_hw(info); 734 exynos_adc_disable_clk(info); 735 regulator_disable(info->vdd); 736 737 return 0; 738} 739 740static int exynos_adc_resume(struct device *dev) 741{ 742 struct iio_dev *indio_dev = dev_get_drvdata(dev); 743 struct exynos_adc *info = iio_priv(indio_dev); 744 int ret; 745 746 ret = regulator_enable(info->vdd); 747 if (ret) 748 return ret; 749 750 ret = exynos_adc_enable_clk(info); 751 if (ret) 752 return ret; 753 754 if (info->data->init_hw) 755 info->data->init_hw(info); 756 757 return 0; 758} 759#endif 760 761static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops, 762 exynos_adc_suspend, 763 exynos_adc_resume); 764 765static struct platform_driver exynos_adc_driver = { 766 .probe = exynos_adc_probe, 767 .remove = exynos_adc_remove, 768 .driver = { 769 .name = "exynos-adc", 770 .of_match_table = exynos_adc_match, 771 .pm = &exynos_adc_pm_ops, 772 }, 773}; 774 775module_platform_driver(exynos_adc_driver); 776 777MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>"); 778MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver"); 779MODULE_LICENSE("GPL v2"); 780