1/* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7/* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15#include <linux/types.h> 16#include <linux/delay.h> 17#include <linux/module.h> 18#include <linux/interrupt.h> 19#include <linux/ioport.h> 20#include <linux/init.h> 21#include <linux/serio.h> 22#include <linux/err.h> 23#include <linux/rcupdate.h> 24#include <linux/platform_device.h> 25#include <linux/i8042.h> 26#include <linux/slab.h> 27 28#include <asm/io.h> 29 30MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 31MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 32MODULE_LICENSE("GPL"); 33 34static bool i8042_nokbd; 35module_param_named(nokbd, i8042_nokbd, bool, 0); 36MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 37 38static bool i8042_noaux; 39module_param_named(noaux, i8042_noaux, bool, 0); 40MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 41 42static bool i8042_nomux; 43module_param_named(nomux, i8042_nomux, bool, 0); 44MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 45 46static bool i8042_unlock; 47module_param_named(unlock, i8042_unlock, bool, 0); 48MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 49 50static bool i8042_reset; 51module_param_named(reset, i8042_reset, bool, 0); 52MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 53 54static bool i8042_direct; 55module_param_named(direct, i8042_direct, bool, 0); 56MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 57 58static bool i8042_dumbkbd; 59module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 60MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 61 62static bool i8042_noloop; 63module_param_named(noloop, i8042_noloop, bool, 0); 64MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 65 66static bool i8042_notimeout; 67module_param_named(notimeout, i8042_notimeout, bool, 0); 68MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); 69 70static bool i8042_kbdreset; 71module_param_named(kbdreset, i8042_kbdreset, bool, 0); 72MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); 73 74#ifdef CONFIG_X86 75static bool i8042_dritek; 76module_param_named(dritek, i8042_dritek, bool, 0); 77MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 78#endif 79 80#ifdef CONFIG_PNP 81static bool i8042_nopnp; 82module_param_named(nopnp, i8042_nopnp, bool, 0); 83MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 84#endif 85 86#define DEBUG 87#ifdef DEBUG 88static bool i8042_debug; 89module_param_named(debug, i8042_debug, bool, 0600); 90MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 91#endif 92 93static bool i8042_bypass_aux_irq_test; 94static char i8042_kbd_firmware_id[128]; 95static char i8042_aux_firmware_id[128]; 96 97#include "i8042.h" 98 99/* 100 * i8042_lock protects serialization between i8042_command and 101 * the interrupt handler. 102 */ 103static DEFINE_SPINLOCK(i8042_lock); 104 105/* 106 * Writers to AUX and KBD ports as well as users issuing i8042_command 107 * directly should acquire i8042_mutex (by means of calling 108 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 109 * they do not disturb each other (unfortunately in many i8042 110 * implementations write to one of the ports will immediately abort 111 * command that is being processed by another port). 112 */ 113static DEFINE_MUTEX(i8042_mutex); 114 115struct i8042_port { 116 struct serio *serio; 117 int irq; 118 bool exists; 119 signed char mux; 120}; 121 122#define I8042_KBD_PORT_NO 0 123#define I8042_AUX_PORT_NO 1 124#define I8042_MUX_PORT_NO 2 125#define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 126 127static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 128 129static unsigned char i8042_initial_ctr; 130static unsigned char i8042_ctr; 131static bool i8042_mux_present; 132static bool i8042_kbd_irq_registered; 133static bool i8042_aux_irq_registered; 134static unsigned char i8042_suppress_kbd_ack; 135static struct platform_device *i8042_platform_device; 136 137static irqreturn_t i8042_interrupt(int irq, void *dev_id); 138static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 139 struct serio *serio); 140 141void i8042_lock_chip(void) 142{ 143 mutex_lock(&i8042_mutex); 144} 145EXPORT_SYMBOL(i8042_lock_chip); 146 147void i8042_unlock_chip(void) 148{ 149 mutex_unlock(&i8042_mutex); 150} 151EXPORT_SYMBOL(i8042_unlock_chip); 152 153int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 154 struct serio *serio)) 155{ 156 unsigned long flags; 157 int ret = 0; 158 159 spin_lock_irqsave(&i8042_lock, flags); 160 161 if (i8042_platform_filter) { 162 ret = -EBUSY; 163 goto out; 164 } 165 166 i8042_platform_filter = filter; 167 168out: 169 spin_unlock_irqrestore(&i8042_lock, flags); 170 return ret; 171} 172EXPORT_SYMBOL(i8042_install_filter); 173 174int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 175 struct serio *port)) 176{ 177 unsigned long flags; 178 int ret = 0; 179 180 spin_lock_irqsave(&i8042_lock, flags); 181 182 if (i8042_platform_filter != filter) { 183 ret = -EINVAL; 184 goto out; 185 } 186 187 i8042_platform_filter = NULL; 188 189out: 190 spin_unlock_irqrestore(&i8042_lock, flags); 191 return ret; 192} 193EXPORT_SYMBOL(i8042_remove_filter); 194 195/* 196 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 197 * be ready for reading values from it / writing values to it. 198 * Called always with i8042_lock held. 199 */ 200 201static int i8042_wait_read(void) 202{ 203 int i = 0; 204 205 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 206 udelay(50); 207 i++; 208 } 209 return -(i == I8042_CTL_TIMEOUT); 210} 211 212static int i8042_wait_write(void) 213{ 214 int i = 0; 215 216 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 217 udelay(50); 218 i++; 219 } 220 return -(i == I8042_CTL_TIMEOUT); 221} 222 223/* 224 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 225 * of the i8042 down the toilet. 226 */ 227 228static int i8042_flush(void) 229{ 230 unsigned long flags; 231 unsigned char data, str; 232 int count = 0; 233 int retval = 0; 234 235 spin_lock_irqsave(&i8042_lock, flags); 236 237 while ((str = i8042_read_status()) & I8042_STR_OBF) { 238 if (count++ < I8042_BUFFER_SIZE) { 239 udelay(50); 240 data = i8042_read_data(); 241 dbg("%02x <- i8042 (flush, %s)\n", 242 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 243 } else { 244 retval = -EIO; 245 break; 246 } 247 } 248 249 spin_unlock_irqrestore(&i8042_lock, flags); 250 251 return retval; 252} 253 254/* 255 * i8042_command() executes a command on the i8042. It also sends the input 256 * parameter(s) of the commands to it, and receives the output value(s). The 257 * parameters are to be stored in the param array, and the output is placed 258 * into the same array. The number of the parameters and output values is 259 * encoded in bits 8-11 of the command number. 260 */ 261 262static int __i8042_command(unsigned char *param, int command) 263{ 264 int i, error; 265 266 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 267 return -1; 268 269 error = i8042_wait_write(); 270 if (error) 271 return error; 272 273 dbg("%02x -> i8042 (command)\n", command & 0xff); 274 i8042_write_command(command & 0xff); 275 276 for (i = 0; i < ((command >> 12) & 0xf); i++) { 277 error = i8042_wait_write(); 278 if (error) 279 return error; 280 dbg("%02x -> i8042 (parameter)\n", param[i]); 281 i8042_write_data(param[i]); 282 } 283 284 for (i = 0; i < ((command >> 8) & 0xf); i++) { 285 error = i8042_wait_read(); 286 if (error) { 287 dbg(" -- i8042 (timeout)\n"); 288 return error; 289 } 290 291 if (command == I8042_CMD_AUX_LOOP && 292 !(i8042_read_status() & I8042_STR_AUXDATA)) { 293 dbg(" -- i8042 (auxerr)\n"); 294 return -1; 295 } 296 297 param[i] = i8042_read_data(); 298 dbg("%02x <- i8042 (return)\n", param[i]); 299 } 300 301 return 0; 302} 303 304int i8042_command(unsigned char *param, int command) 305{ 306 unsigned long flags; 307 int retval; 308 309 spin_lock_irqsave(&i8042_lock, flags); 310 retval = __i8042_command(param, command); 311 spin_unlock_irqrestore(&i8042_lock, flags); 312 313 return retval; 314} 315EXPORT_SYMBOL(i8042_command); 316 317/* 318 * i8042_kbd_write() sends a byte out through the keyboard interface. 319 */ 320 321static int i8042_kbd_write(struct serio *port, unsigned char c) 322{ 323 unsigned long flags; 324 int retval = 0; 325 326 spin_lock_irqsave(&i8042_lock, flags); 327 328 if (!(retval = i8042_wait_write())) { 329 dbg("%02x -> i8042 (kbd-data)\n", c); 330 i8042_write_data(c); 331 } 332 333 spin_unlock_irqrestore(&i8042_lock, flags); 334 335 return retval; 336} 337 338/* 339 * i8042_aux_write() sends a byte out through the aux interface. 340 */ 341 342static int i8042_aux_write(struct serio *serio, unsigned char c) 343{ 344 struct i8042_port *port = serio->port_data; 345 346 return i8042_command(&c, port->mux == -1 ? 347 I8042_CMD_AUX_SEND : 348 I8042_CMD_MUX_SEND + port->mux); 349} 350 351 352/* 353 * i8042_aux_close attempts to clear AUX or KBD port state by disabling 354 * and then re-enabling it. 355 */ 356 357static void i8042_port_close(struct serio *serio) 358{ 359 int irq_bit; 360 int disable_bit; 361 const char *port_name; 362 363 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 364 irq_bit = I8042_CTR_AUXINT; 365 disable_bit = I8042_CTR_AUXDIS; 366 port_name = "AUX"; 367 } else { 368 irq_bit = I8042_CTR_KBDINT; 369 disable_bit = I8042_CTR_KBDDIS; 370 port_name = "KBD"; 371 } 372 373 i8042_ctr &= ~irq_bit; 374 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 375 pr_warn("Can't write CTR while closing %s port\n", port_name); 376 377 udelay(50); 378 379 i8042_ctr &= ~disable_bit; 380 i8042_ctr |= irq_bit; 381 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 382 pr_err("Can't reactivate %s port\n", port_name); 383 384 /* 385 * See if there is any data appeared while we were messing with 386 * port state. 387 */ 388 i8042_interrupt(0, NULL); 389} 390 391/* 392 * i8042_start() is called by serio core when port is about to finish 393 * registering. It will mark port as existing so i8042_interrupt can 394 * start sending data through it. 395 */ 396static int i8042_start(struct serio *serio) 397{ 398 struct i8042_port *port = serio->port_data; 399 400 port->exists = true; 401 mb(); 402 return 0; 403} 404 405/* 406 * i8042_stop() marks serio port as non-existing so i8042_interrupt 407 * will not try to send data to the port that is about to go away. 408 * The function is called by serio core as part of unregister procedure. 409 */ 410static void i8042_stop(struct serio *serio) 411{ 412 struct i8042_port *port = serio->port_data; 413 414 port->exists = false; 415 416 /* 417 * We synchronize with both AUX and KBD IRQs because there is 418 * a (very unlikely) chance that AUX IRQ is raised for KBD port 419 * and vice versa. 420 */ 421 synchronize_irq(I8042_AUX_IRQ); 422 synchronize_irq(I8042_KBD_IRQ); 423 port->serio = NULL; 424} 425 426/* 427 * i8042_filter() filters out unwanted bytes from the input data stream. 428 * It is called from i8042_interrupt and thus is running with interrupts 429 * off and i8042_lock held. 430 */ 431static bool i8042_filter(unsigned char data, unsigned char str, 432 struct serio *serio) 433{ 434 if (unlikely(i8042_suppress_kbd_ack)) { 435 if ((~str & I8042_STR_AUXDATA) && 436 (data == 0xfa || data == 0xfe)) { 437 i8042_suppress_kbd_ack--; 438 dbg("Extra keyboard ACK - filtered out\n"); 439 return true; 440 } 441 } 442 443 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 444 dbg("Filtered out by platform filter\n"); 445 return true; 446 } 447 448 return false; 449} 450 451/* 452 * i8042_interrupt() is the most important function in this driver - 453 * it handles the interrupts from the i8042, and sends incoming bytes 454 * to the upper layers. 455 */ 456 457static irqreturn_t i8042_interrupt(int irq, void *dev_id) 458{ 459 struct i8042_port *port; 460 struct serio *serio; 461 unsigned long flags; 462 unsigned char str, data; 463 unsigned int dfl; 464 unsigned int port_no; 465 bool filtered; 466 int ret = 1; 467 468 spin_lock_irqsave(&i8042_lock, flags); 469 470 str = i8042_read_status(); 471 if (unlikely(~str & I8042_STR_OBF)) { 472 spin_unlock_irqrestore(&i8042_lock, flags); 473 if (irq) 474 dbg("Interrupt %d, without any data\n", irq); 475 ret = 0; 476 goto out; 477 } 478 479 data = i8042_read_data(); 480 481 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 482 static unsigned long last_transmit; 483 static unsigned char last_str; 484 485 dfl = 0; 486 if (str & I8042_STR_MUXERR) { 487 dbg("MUX error, status is %02x, data is %02x\n", 488 str, data); 489/* 490 * When MUXERR condition is signalled the data register can only contain 491 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 492 * it is not always the case. Some KBCs also report 0xfc when there is 493 * nothing connected to the port while others sometimes get confused which 494 * port the data came from and signal error leaving the data intact. They 495 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 496 * to legacy mode yet, when we see one we'll add proper handling). 497 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 498 * rest assume that the data came from the same serio last byte 499 * was transmitted (if transmission happened not too long ago). 500 */ 501 502 switch (data) { 503 default: 504 if (time_before(jiffies, last_transmit + HZ/10)) { 505 str = last_str; 506 break; 507 } 508 /* fall through - report timeout */ 509 case 0xfc: 510 case 0xfd: 511 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 512 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 513 } 514 } 515 516 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 517 last_str = str; 518 last_transmit = jiffies; 519 } else { 520 521 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 522 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); 523 524 port_no = (str & I8042_STR_AUXDATA) ? 525 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 526 } 527 528 port = &i8042_ports[port_no]; 529 serio = port->exists ? port->serio : NULL; 530 531 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)\n", 532 data, port_no, irq, 533 dfl & SERIO_PARITY ? ", bad parity" : "", 534 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 535 536 filtered = i8042_filter(data, str, serio); 537 538 spin_unlock_irqrestore(&i8042_lock, flags); 539 540 if (likely(port->exists && !filtered)) 541 serio_interrupt(serio, data, dfl); 542 543 out: 544 return IRQ_RETVAL(ret); 545} 546 547/* 548 * i8042_enable_kbd_port enables keyboard port on chip 549 */ 550 551static int i8042_enable_kbd_port(void) 552{ 553 i8042_ctr &= ~I8042_CTR_KBDDIS; 554 i8042_ctr |= I8042_CTR_KBDINT; 555 556 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 557 i8042_ctr &= ~I8042_CTR_KBDINT; 558 i8042_ctr |= I8042_CTR_KBDDIS; 559 pr_err("Failed to enable KBD port\n"); 560 return -EIO; 561 } 562 563 return 0; 564} 565 566/* 567 * i8042_enable_aux_port enables AUX (mouse) port on chip 568 */ 569 570static int i8042_enable_aux_port(void) 571{ 572 i8042_ctr &= ~I8042_CTR_AUXDIS; 573 i8042_ctr |= I8042_CTR_AUXINT; 574 575 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 576 i8042_ctr &= ~I8042_CTR_AUXINT; 577 i8042_ctr |= I8042_CTR_AUXDIS; 578 pr_err("Failed to enable AUX port\n"); 579 return -EIO; 580 } 581 582 return 0; 583} 584 585/* 586 * i8042_enable_mux_ports enables 4 individual AUX ports after 587 * the controller has been switched into Multiplexed mode 588 */ 589 590static int i8042_enable_mux_ports(void) 591{ 592 unsigned char param; 593 int i; 594 595 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 596 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 597 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 598 } 599 600 return i8042_enable_aux_port(); 601} 602 603/* 604 * i8042_set_mux_mode checks whether the controller has an 605 * active multiplexor and puts the chip into Multiplexed (true) 606 * or Legacy (false) mode. 607 */ 608 609static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 610{ 611 612 unsigned char param, val; 613/* 614 * Get rid of bytes in the queue. 615 */ 616 617 i8042_flush(); 618 619/* 620 * Internal loopback test - send three bytes, they should come back from the 621 * mouse interface, the last should be version. 622 */ 623 624 param = val = 0xf0; 625 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 626 return -1; 627 param = val = multiplex ? 0x56 : 0xf6; 628 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 629 return -1; 630 param = val = multiplex ? 0xa4 : 0xa5; 631 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 632 return -1; 633 634/* 635 * Workaround for interference with USB Legacy emulation 636 * that causes a v10.12 MUX to be found. 637 */ 638 if (param == 0xac) 639 return -1; 640 641 if (mux_version) 642 *mux_version = param; 643 644 return 0; 645} 646 647/* 648 * i8042_check_mux() checks whether the controller supports the PS/2 Active 649 * Multiplexing specification by Synaptics, Phoenix, Insyde and 650 * LCS/Telegraphics. 651 */ 652 653static int __init i8042_check_mux(void) 654{ 655 unsigned char mux_version; 656 657 if (i8042_set_mux_mode(true, &mux_version)) 658 return -1; 659 660 pr_info("Detected active multiplexing controller, rev %d.%d\n", 661 (mux_version >> 4) & 0xf, mux_version & 0xf); 662 663/* 664 * Disable all muxed ports by disabling AUX. 665 */ 666 i8042_ctr |= I8042_CTR_AUXDIS; 667 i8042_ctr &= ~I8042_CTR_AUXINT; 668 669 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 670 pr_err("Failed to disable AUX port, can't use MUX\n"); 671 return -EIO; 672 } 673 674 i8042_mux_present = true; 675 676 return 0; 677} 678 679/* 680 * The following is used to test AUX IRQ delivery. 681 */ 682static struct completion i8042_aux_irq_delivered __initdata; 683static bool i8042_irq_being_tested __initdata; 684 685static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 686{ 687 unsigned long flags; 688 unsigned char str, data; 689 int ret = 0; 690 691 spin_lock_irqsave(&i8042_lock, flags); 692 str = i8042_read_status(); 693 if (str & I8042_STR_OBF) { 694 data = i8042_read_data(); 695 dbg("%02x <- i8042 (aux_test_irq, %s)\n", 696 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 697 if (i8042_irq_being_tested && 698 data == 0xa5 && (str & I8042_STR_AUXDATA)) 699 complete(&i8042_aux_irq_delivered); 700 ret = 1; 701 } 702 spin_unlock_irqrestore(&i8042_lock, flags); 703 704 return IRQ_RETVAL(ret); 705} 706 707/* 708 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 709 * verifies success by readinng CTR. Used when testing for presence of AUX 710 * port. 711 */ 712static int __init i8042_toggle_aux(bool on) 713{ 714 unsigned char param; 715 int i; 716 717 if (i8042_command(¶m, 718 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 719 return -1; 720 721 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 722 for (i = 0; i < 100; i++) { 723 udelay(50); 724 725 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 726 return -1; 727 728 if (!(param & I8042_CTR_AUXDIS) == on) 729 return 0; 730 } 731 732 return -1; 733} 734 735/* 736 * i8042_check_aux() applies as much paranoia as it can at detecting 737 * the presence of an AUX interface. 738 */ 739 740static int __init i8042_check_aux(void) 741{ 742 int retval = -1; 743 bool irq_registered = false; 744 bool aux_loop_broken = false; 745 unsigned long flags; 746 unsigned char param; 747 748/* 749 * Get rid of bytes in the queue. 750 */ 751 752 i8042_flush(); 753 754/* 755 * Internal loopback test - filters out AT-type i8042's. Unfortunately 756 * SiS screwed up and their 5597 doesn't support the LOOP command even 757 * though it has an AUX port. 758 */ 759 760 param = 0x5a; 761 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 762 if (retval || param != 0x5a) { 763 764/* 765 * External connection test - filters out AT-soldered PS/2 i8042's 766 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 767 * 0xfa - no error on some notebooks which ignore the spec 768 * Because it's common for chipsets to return error on perfectly functioning 769 * AUX ports, we test for this only when the LOOP command failed. 770 */ 771 772 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 773 (param && param != 0xfa && param != 0xff)) 774 return -1; 775 776/* 777 * If AUX_LOOP completed without error but returned unexpected data 778 * mark it as broken 779 */ 780 if (!retval) 781 aux_loop_broken = true; 782 } 783 784/* 785 * Bit assignment test - filters out PS/2 i8042's in AT mode 786 */ 787 788 if (i8042_toggle_aux(false)) { 789 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 790 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); 791 } 792 793 if (i8042_toggle_aux(true)) 794 return -1; 795 796/* 797 * Reset keyboard (needed on some laptops to successfully detect 798 * touchpad, e.g., some Gigabyte laptop models with Elantech 799 * touchpads). 800 */ 801 if (i8042_kbdreset) { 802 pr_warn("Attempting to reset device connected to KBD port\n"); 803 i8042_kbd_write(NULL, (unsigned char) 0xff); 804 } 805 806/* 807 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 808 * used it for a PCI card or somethig else. 809 */ 810 811 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 812/* 813 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 814 * is working and hope we are right. 815 */ 816 retval = 0; 817 goto out; 818 } 819 820 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 821 "i8042", i8042_platform_device)) 822 goto out; 823 824 irq_registered = true; 825 826 if (i8042_enable_aux_port()) 827 goto out; 828 829 spin_lock_irqsave(&i8042_lock, flags); 830 831 init_completion(&i8042_aux_irq_delivered); 832 i8042_irq_being_tested = true; 833 834 param = 0xa5; 835 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 836 837 spin_unlock_irqrestore(&i8042_lock, flags); 838 839 if (retval) 840 goto out; 841 842 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 843 msecs_to_jiffies(250)) == 0) { 844/* 845 * AUX IRQ was never delivered so we need to flush the controller to 846 * get rid of the byte we put there; otherwise keyboard may not work. 847 */ 848 dbg(" -- i8042 (aux irq test timeout)\n"); 849 i8042_flush(); 850 retval = -1; 851 } 852 853 out: 854 855/* 856 * Disable the interface. 857 */ 858 859 i8042_ctr |= I8042_CTR_AUXDIS; 860 i8042_ctr &= ~I8042_CTR_AUXINT; 861 862 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 863 retval = -1; 864 865 if (irq_registered) 866 free_irq(I8042_AUX_IRQ, i8042_platform_device); 867 868 return retval; 869} 870 871static int i8042_controller_check(void) 872{ 873 if (i8042_flush()) { 874 pr_err("No controller found\n"); 875 return -ENODEV; 876 } 877 878 return 0; 879} 880 881static int i8042_controller_selftest(void) 882{ 883 unsigned char param; 884 int i = 0; 885 886 /* 887 * We try this 5 times; on some really fragile systems this does not 888 * take the first time... 889 */ 890 do { 891 892 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 893 pr_err("i8042 controller selftest timeout\n"); 894 return -ENODEV; 895 } 896 897 if (param == I8042_RET_CTL_TEST) 898 return 0; 899 900 dbg("i8042 controller selftest: %#x != %#x\n", 901 param, I8042_RET_CTL_TEST); 902 msleep(50); 903 } while (i++ < 5); 904 905#ifdef CONFIG_X86 906 /* 907 * On x86, we don't fail entire i8042 initialization if controller 908 * reset fails in hopes that keyboard port will still be functional 909 * and user will still get a working keyboard. This is especially 910 * important on netbooks. On other arches we trust hardware more. 911 */ 912 pr_info("giving up on controller selftest, continuing anyway...\n"); 913 return 0; 914#else 915 pr_err("i8042 controller selftest failed\n"); 916 return -EIO; 917#endif 918} 919 920/* 921 * i8042_controller init initializes the i8042 controller, and, 922 * most importantly, sets it into non-xlated mode if that's 923 * desired. 924 */ 925 926static int i8042_controller_init(void) 927{ 928 unsigned long flags; 929 int n = 0; 930 unsigned char ctr[2]; 931 932/* 933 * Save the CTR for restore on unload / reboot. 934 */ 935 936 do { 937 if (n >= 10) { 938 pr_err("Unable to get stable CTR read\n"); 939 return -EIO; 940 } 941 942 if (n != 0) 943 udelay(50); 944 945 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 946 pr_err("Can't read CTR while initializing i8042\n"); 947 return -EIO; 948 } 949 950 } while (n < 2 || ctr[0] != ctr[1]); 951 952 i8042_initial_ctr = i8042_ctr = ctr[0]; 953 954/* 955 * Disable the keyboard interface and interrupt. 956 */ 957 958 i8042_ctr |= I8042_CTR_KBDDIS; 959 i8042_ctr &= ~I8042_CTR_KBDINT; 960 961/* 962 * Handle keylock. 963 */ 964 965 spin_lock_irqsave(&i8042_lock, flags); 966 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 967 if (i8042_unlock) 968 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 969 else 970 pr_warn("Warning: Keylock active\n"); 971 } 972 spin_unlock_irqrestore(&i8042_lock, flags); 973 974/* 975 * If the chip is configured into nontranslated mode by the BIOS, don't 976 * bother enabling translating and be happy. 977 */ 978 979 if (~i8042_ctr & I8042_CTR_XLATE) 980 i8042_direct = true; 981 982/* 983 * Set nontranslated mode for the kbd interface if requested by an option. 984 * After this the kbd interface becomes a simple serial in/out, like the aux 985 * interface is. We don't do this by default, since it can confuse notebook 986 * BIOSes. 987 */ 988 989 if (i8042_direct) 990 i8042_ctr &= ~I8042_CTR_XLATE; 991 992/* 993 * Write CTR back. 994 */ 995 996 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 997 pr_err("Can't write CTR while initializing i8042\n"); 998 return -EIO; 999 } 1000 1001/* 1002 * Flush whatever accumulated while we were disabling keyboard port. 1003 */ 1004 1005 i8042_flush(); 1006 1007 return 0; 1008} 1009 1010 1011/* 1012 * Reset the controller and reset CRT to the original value set by BIOS. 1013 */ 1014 1015static void i8042_controller_reset(bool force_reset) 1016{ 1017 i8042_flush(); 1018 1019/* 1020 * Disable both KBD and AUX interfaces so they don't get in the way 1021 */ 1022 1023 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1024 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1025 1026 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1027 pr_warn("Can't write CTR while resetting\n"); 1028 1029/* 1030 * Disable MUX mode if present. 1031 */ 1032 1033 if (i8042_mux_present) 1034 i8042_set_mux_mode(false, NULL); 1035 1036/* 1037 * Reset the controller if requested. 1038 */ 1039 1040 if (i8042_reset || force_reset) 1041 i8042_controller_selftest(); 1042 1043/* 1044 * Restore the original control register setting. 1045 */ 1046 1047 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1048 pr_warn("Can't restore CTR\n"); 1049} 1050 1051 1052/* 1053 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1054 * when kernel panics. Flashing LEDs is useful for users running X who may 1055 * not see the console and will help distinguishing panics from "real" 1056 * lockups. 1057 * 1058 * Note that DELAY has a limit of 10ms so we will not get stuck here 1059 * waiting for KBC to free up even if KBD interrupt is off 1060 */ 1061 1062#define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1063 1064static long i8042_panic_blink(int state) 1065{ 1066 long delay = 0; 1067 char led; 1068 1069 led = (state) ? 0x01 | 0x04 : 0; 1070 while (i8042_read_status() & I8042_STR_IBF) 1071 DELAY; 1072 dbg("%02x -> i8042 (panic blink)\n", 0xed); 1073 i8042_suppress_kbd_ack = 2; 1074 i8042_write_data(0xed); /* set leds */ 1075 DELAY; 1076 while (i8042_read_status() & I8042_STR_IBF) 1077 DELAY; 1078 DELAY; 1079 dbg("%02x -> i8042 (panic blink)\n", led); 1080 i8042_write_data(led); 1081 DELAY; 1082 return delay; 1083} 1084 1085#undef DELAY 1086 1087#ifdef CONFIG_X86 1088static void i8042_dritek_enable(void) 1089{ 1090 unsigned char param = 0x90; 1091 int error; 1092 1093 error = i8042_command(¶m, 0x1059); 1094 if (error) 1095 pr_warn("Failed to enable DRITEK extension: %d\n", error); 1096} 1097#endif 1098 1099#ifdef CONFIG_PM 1100 1101/* 1102 * Here we try to reset everything back to a state we had 1103 * before suspending. 1104 */ 1105 1106static int i8042_controller_resume(bool force_reset) 1107{ 1108 int error; 1109 1110 error = i8042_controller_check(); 1111 if (error) 1112 return error; 1113 1114 if (i8042_reset || force_reset) { 1115 error = i8042_controller_selftest(); 1116 if (error) 1117 return error; 1118 } 1119 1120/* 1121 * Restore original CTR value and disable all ports 1122 */ 1123 1124 i8042_ctr = i8042_initial_ctr; 1125 if (i8042_direct) 1126 i8042_ctr &= ~I8042_CTR_XLATE; 1127 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1128 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1129 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1130 pr_warn("Can't write CTR to resume, retrying...\n"); 1131 msleep(50); 1132 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1133 pr_err("CTR write retry failed\n"); 1134 return -EIO; 1135 } 1136 } 1137 1138 1139#ifdef CONFIG_X86 1140 if (i8042_dritek) 1141 i8042_dritek_enable(); 1142#endif 1143 1144 if (i8042_mux_present) { 1145 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1146 pr_warn("failed to resume active multiplexor, mouse won't work\n"); 1147 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1148 i8042_enable_aux_port(); 1149 1150 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1151 i8042_enable_kbd_port(); 1152 1153 i8042_interrupt(0, NULL); 1154 1155 return 0; 1156} 1157 1158/* 1159 * Here we try to restore the original BIOS settings to avoid 1160 * upsetting it. 1161 */ 1162 1163static int i8042_pm_suspend(struct device *dev) 1164{ 1165 int i; 1166 1167 i8042_controller_reset(true); 1168 1169 /* Set up serio interrupts for system wakeup. */ 1170 for (i = 0; i < I8042_NUM_PORTS; i++) { 1171 struct serio *serio = i8042_ports[i].serio; 1172 1173 if (serio && device_may_wakeup(&serio->dev)) 1174 enable_irq_wake(i8042_ports[i].irq); 1175 } 1176 1177 return 0; 1178} 1179 1180static int i8042_pm_resume(struct device *dev) 1181{ 1182 int i; 1183 1184 for (i = 0; i < I8042_NUM_PORTS; i++) { 1185 struct serio *serio = i8042_ports[i].serio; 1186 1187 if (serio && device_may_wakeup(&serio->dev)) 1188 disable_irq_wake(i8042_ports[i].irq); 1189 } 1190 1191 /* 1192 * On resume from S2R we always try to reset the controller 1193 * to bring it in a sane state. (In case of S2D we expect 1194 * BIOS to reset the controller for us.) 1195 */ 1196 return i8042_controller_resume(true); 1197} 1198 1199static int i8042_pm_thaw(struct device *dev) 1200{ 1201 i8042_interrupt(0, NULL); 1202 1203 return 0; 1204} 1205 1206static int i8042_pm_reset(struct device *dev) 1207{ 1208 i8042_controller_reset(false); 1209 1210 return 0; 1211} 1212 1213static int i8042_pm_restore(struct device *dev) 1214{ 1215 return i8042_controller_resume(false); 1216} 1217 1218static const struct dev_pm_ops i8042_pm_ops = { 1219 .suspend = i8042_pm_suspend, 1220 .resume = i8042_pm_resume, 1221 .thaw = i8042_pm_thaw, 1222 .poweroff = i8042_pm_reset, 1223 .restore = i8042_pm_restore, 1224}; 1225 1226#endif /* CONFIG_PM */ 1227 1228/* 1229 * We need to reset the 8042 back to original mode on system shutdown, 1230 * because otherwise BIOSes will be confused. 1231 */ 1232 1233static void i8042_shutdown(struct platform_device *dev) 1234{ 1235 i8042_controller_reset(false); 1236} 1237 1238static int __init i8042_create_kbd_port(void) 1239{ 1240 struct serio *serio; 1241 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1242 1243 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1244 if (!serio) 1245 return -ENOMEM; 1246 1247 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1248 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1249 serio->start = i8042_start; 1250 serio->stop = i8042_stop; 1251 serio->close = i8042_port_close; 1252 serio->port_data = port; 1253 serio->dev.parent = &i8042_platform_device->dev; 1254 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1255 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1256 strlcpy(serio->firmware_id, i8042_kbd_firmware_id, 1257 sizeof(serio->firmware_id)); 1258 1259 port->serio = serio; 1260 port->irq = I8042_KBD_IRQ; 1261 1262 return 0; 1263} 1264 1265static int __init i8042_create_aux_port(int idx) 1266{ 1267 struct serio *serio; 1268 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1269 struct i8042_port *port = &i8042_ports[port_no]; 1270 1271 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1272 if (!serio) 1273 return -ENOMEM; 1274 1275 serio->id.type = SERIO_8042; 1276 serio->write = i8042_aux_write; 1277 serio->start = i8042_start; 1278 serio->stop = i8042_stop; 1279 serio->port_data = port; 1280 serio->dev.parent = &i8042_platform_device->dev; 1281 if (idx < 0) { 1282 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1283 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1284 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1285 sizeof(serio->firmware_id)); 1286 serio->close = i8042_port_close; 1287 } else { 1288 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1289 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1290 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1291 sizeof(serio->firmware_id)); 1292 } 1293 1294 port->serio = serio; 1295 port->mux = idx; 1296 port->irq = I8042_AUX_IRQ; 1297 1298 return 0; 1299} 1300 1301static void __init i8042_free_kbd_port(void) 1302{ 1303 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1304 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1305} 1306 1307static void __init i8042_free_aux_ports(void) 1308{ 1309 int i; 1310 1311 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1312 kfree(i8042_ports[i].serio); 1313 i8042_ports[i].serio = NULL; 1314 } 1315} 1316 1317static void __init i8042_register_ports(void) 1318{ 1319 int i; 1320 1321 for (i = 0; i < I8042_NUM_PORTS; i++) { 1322 struct serio *serio = i8042_ports[i].serio; 1323 1324 if (serio) { 1325 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1326 serio->name, 1327 (unsigned long) I8042_DATA_REG, 1328 (unsigned long) I8042_COMMAND_REG, 1329 i8042_ports[i].irq); 1330 serio_register_port(serio); 1331 device_set_wakeup_capable(&serio->dev, true); 1332 } 1333 } 1334} 1335 1336static void i8042_unregister_ports(void) 1337{ 1338 int i; 1339 1340 for (i = 0; i < I8042_NUM_PORTS; i++) { 1341 if (i8042_ports[i].serio) { 1342 serio_unregister_port(i8042_ports[i].serio); 1343 i8042_ports[i].serio = NULL; 1344 } 1345 } 1346} 1347 1348/* 1349 * Checks whether port belongs to i8042 controller. 1350 */ 1351bool i8042_check_port_owner(const struct serio *port) 1352{ 1353 int i; 1354 1355 for (i = 0; i < I8042_NUM_PORTS; i++) 1356 if (i8042_ports[i].serio == port) 1357 return true; 1358 1359 return false; 1360} 1361EXPORT_SYMBOL(i8042_check_port_owner); 1362 1363static void i8042_free_irqs(void) 1364{ 1365 if (i8042_aux_irq_registered) 1366 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1367 if (i8042_kbd_irq_registered) 1368 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1369 1370 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1371} 1372 1373static int __init i8042_setup_aux(void) 1374{ 1375 int (*aux_enable)(void); 1376 int error; 1377 int i; 1378 1379 if (i8042_check_aux()) 1380 return -ENODEV; 1381 1382 if (i8042_nomux || i8042_check_mux()) { 1383 error = i8042_create_aux_port(-1); 1384 if (error) 1385 goto err_free_ports; 1386 aux_enable = i8042_enable_aux_port; 1387 } else { 1388 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1389 error = i8042_create_aux_port(i); 1390 if (error) 1391 goto err_free_ports; 1392 } 1393 aux_enable = i8042_enable_mux_ports; 1394 } 1395 1396 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1397 "i8042", i8042_platform_device); 1398 if (error) 1399 goto err_free_ports; 1400 1401 if (aux_enable()) 1402 goto err_free_irq; 1403 1404 i8042_aux_irq_registered = true; 1405 return 0; 1406 1407 err_free_irq: 1408 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1409 err_free_ports: 1410 i8042_free_aux_ports(); 1411 return error; 1412} 1413 1414static int __init i8042_setup_kbd(void) 1415{ 1416 int error; 1417 1418 error = i8042_create_kbd_port(); 1419 if (error) 1420 return error; 1421 1422 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1423 "i8042", i8042_platform_device); 1424 if (error) 1425 goto err_free_port; 1426 1427 error = i8042_enable_kbd_port(); 1428 if (error) 1429 goto err_free_irq; 1430 1431 i8042_kbd_irq_registered = true; 1432 return 0; 1433 1434 err_free_irq: 1435 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1436 err_free_port: 1437 i8042_free_kbd_port(); 1438 return error; 1439} 1440 1441static int __init i8042_probe(struct platform_device *dev) 1442{ 1443 int error; 1444 1445 i8042_platform_device = dev; 1446 1447 if (i8042_reset) { 1448 error = i8042_controller_selftest(); 1449 if (error) 1450 return error; 1451 } 1452 1453 error = i8042_controller_init(); 1454 if (error) 1455 return error; 1456 1457#ifdef CONFIG_X86 1458 if (i8042_dritek) 1459 i8042_dritek_enable(); 1460#endif 1461 1462 if (!i8042_noaux) { 1463 error = i8042_setup_aux(); 1464 if (error && error != -ENODEV && error != -EBUSY) 1465 goto out_fail; 1466 } 1467 1468 if (!i8042_nokbd) { 1469 error = i8042_setup_kbd(); 1470 if (error) 1471 goto out_fail; 1472 } 1473/* 1474 * Ok, everything is ready, let's register all serio ports 1475 */ 1476 i8042_register_ports(); 1477 1478 return 0; 1479 1480 out_fail: 1481 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1482 i8042_free_irqs(); 1483 i8042_controller_reset(false); 1484 i8042_platform_device = NULL; 1485 1486 return error; 1487} 1488 1489static int i8042_remove(struct platform_device *dev) 1490{ 1491 i8042_unregister_ports(); 1492 i8042_free_irqs(); 1493 i8042_controller_reset(false); 1494 i8042_platform_device = NULL; 1495 1496 return 0; 1497} 1498 1499static struct platform_driver i8042_driver = { 1500 .driver = { 1501 .name = "i8042", 1502#ifdef CONFIG_PM 1503 .pm = &i8042_pm_ops, 1504#endif 1505 }, 1506 .remove = i8042_remove, 1507 .shutdown = i8042_shutdown, 1508}; 1509 1510static int __init i8042_init(void) 1511{ 1512 struct platform_device *pdev; 1513 int err; 1514 1515 dbg_init(); 1516 1517 err = i8042_platform_init(); 1518 if (err) 1519 return err; 1520 1521 err = i8042_controller_check(); 1522 if (err) 1523 goto err_platform_exit; 1524 1525 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); 1526 if (IS_ERR(pdev)) { 1527 err = PTR_ERR(pdev); 1528 goto err_platform_exit; 1529 } 1530 1531 panic_blink = i8042_panic_blink; 1532 1533 return 0; 1534 1535 err_platform_exit: 1536 i8042_platform_exit(); 1537 return err; 1538} 1539 1540static void __exit i8042_exit(void) 1541{ 1542 platform_device_unregister(i8042_platform_device); 1543 platform_driver_unregister(&i8042_driver); 1544 i8042_platform_exit(); 1545 1546 panic_blink = NULL; 1547} 1548 1549module_init(i8042_init); 1550module_exit(i8042_exit); 1551