1/* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23#include <linux/init.h> 24#include <linux/kernel.h> 25#include <linux/err.h> 26#include <linux/module.h> 27#include <linux/list.h> 28#include <linux/smp.h> 29#include <linux/cpu.h> 30#include <linux/cpu_pm.h> 31#include <linux/cpumask.h> 32#include <linux/io.h> 33#include <linux/of.h> 34#include <linux/of_address.h> 35#include <linux/of_irq.h> 36#include <linux/acpi.h> 37#include <linux/irqdomain.h> 38#include <linux/interrupt.h> 39#include <linux/percpu.h> 40#include <linux/slab.h> 41#include <linux/irqchip/chained_irq.h> 42#include <linux/irqchip/arm-gic.h> 43#include <linux/irqchip/arm-gic-acpi.h> 44 45#include <asm/cputype.h> 46#include <asm/irq.h> 47#include <asm/exception.h> 48#include <asm/smp_plat.h> 49 50#include "irq-gic-common.h" 51#include "irqchip.h" 52 53union gic_base { 54 void __iomem *common_base; 55 void __percpu * __iomem *percpu_base; 56}; 57 58struct gic_chip_data { 59 union gic_base dist_base; 60 union gic_base cpu_base; 61#ifdef CONFIG_CPU_PM 62 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 63 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 64 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 65 u32 __percpu *saved_ppi_enable; 66 u32 __percpu *saved_ppi_conf; 67#endif 68 struct irq_domain *domain; 69 unsigned int gic_irqs; 70#ifdef CONFIG_GIC_NON_BANKED 71 void __iomem *(*get_base)(union gic_base *); 72#endif 73}; 74 75static DEFINE_RAW_SPINLOCK(irq_controller_lock); 76 77/* 78 * The GIC mapping of CPU interfaces does not necessarily match 79 * the logical CPU numbering. Let's use a mapping as returned 80 * by the GIC itself. 81 */ 82#define NR_GIC_CPU_IF 8 83static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 84 85#ifndef MAX_GIC_NR 86#define MAX_GIC_NR 1 87#endif 88 89static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; 90 91#ifdef CONFIG_GIC_NON_BANKED 92static void __iomem *gic_get_percpu_base(union gic_base *base) 93{ 94 return raw_cpu_read(*base->percpu_base); 95} 96 97static void __iomem *gic_get_common_base(union gic_base *base) 98{ 99 return base->common_base; 100} 101 102static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 103{ 104 return data->get_base(&data->dist_base); 105} 106 107static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 108{ 109 return data->get_base(&data->cpu_base); 110} 111 112static inline void gic_set_base_accessor(struct gic_chip_data *data, 113 void __iomem *(*f)(union gic_base *)) 114{ 115 data->get_base = f; 116} 117#else 118#define gic_data_dist_base(d) ((d)->dist_base.common_base) 119#define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 120#define gic_set_base_accessor(d, f) 121#endif 122 123static inline void __iomem *gic_dist_base(struct irq_data *d) 124{ 125 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 126 return gic_data_dist_base(gic_data); 127} 128 129static inline void __iomem *gic_cpu_base(struct irq_data *d) 130{ 131 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 132 return gic_data_cpu_base(gic_data); 133} 134 135static inline unsigned int gic_irq(struct irq_data *d) 136{ 137 return d->hwirq; 138} 139 140/* 141 * Routines to acknowledge, disable and enable interrupts 142 */ 143static void gic_poke_irq(struct irq_data *d, u32 offset) 144{ 145 u32 mask = 1 << (gic_irq(d) % 32); 146 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 147} 148 149static int gic_peek_irq(struct irq_data *d, u32 offset) 150{ 151 u32 mask = 1 << (gic_irq(d) % 32); 152 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 153} 154 155static void gic_mask_irq(struct irq_data *d) 156{ 157 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 158} 159 160static void gic_unmask_irq(struct irq_data *d) 161{ 162 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 163} 164 165static void gic_eoi_irq(struct irq_data *d) 166{ 167 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 168} 169 170static int gic_irq_set_irqchip_state(struct irq_data *d, 171 enum irqchip_irq_state which, bool val) 172{ 173 u32 reg; 174 175 switch (which) { 176 case IRQCHIP_STATE_PENDING: 177 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 178 break; 179 180 case IRQCHIP_STATE_ACTIVE: 181 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 182 break; 183 184 case IRQCHIP_STATE_MASKED: 185 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 186 break; 187 188 default: 189 return -EINVAL; 190 } 191 192 gic_poke_irq(d, reg); 193 return 0; 194} 195 196static int gic_irq_get_irqchip_state(struct irq_data *d, 197 enum irqchip_irq_state which, bool *val) 198{ 199 switch (which) { 200 case IRQCHIP_STATE_PENDING: 201 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 202 break; 203 204 case IRQCHIP_STATE_ACTIVE: 205 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 206 break; 207 208 case IRQCHIP_STATE_MASKED: 209 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 210 break; 211 212 default: 213 return -EINVAL; 214 } 215 216 return 0; 217} 218 219static int gic_set_type(struct irq_data *d, unsigned int type) 220{ 221 void __iomem *base = gic_dist_base(d); 222 unsigned int gicirq = gic_irq(d); 223 224 /* Interrupt configuration for SGIs can't be changed */ 225 if (gicirq < 16) 226 return -EINVAL; 227 228 /* SPIs have restrictions on the supported types */ 229 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 230 type != IRQ_TYPE_EDGE_RISING) 231 return -EINVAL; 232 233 return gic_configure_irq(gicirq, type, base, NULL); 234} 235 236#ifdef CONFIG_SMP 237static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 238 bool force) 239{ 240 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 241 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 242 u32 val, mask, bit; 243 unsigned long flags; 244 245 if (!force) 246 cpu = cpumask_any_and(mask_val, cpu_online_mask); 247 else 248 cpu = cpumask_first(mask_val); 249 250 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 251 return -EINVAL; 252 253 raw_spin_lock_irqsave(&irq_controller_lock, flags); 254 mask = 0xff << shift; 255 bit = gic_cpu_map[cpu] << shift; 256 val = readl_relaxed(reg) & ~mask; 257 writel_relaxed(val | bit, reg); 258 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 259 260 return IRQ_SET_MASK_OK; 261} 262#endif 263 264static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 265{ 266 u32 irqstat, irqnr; 267 struct gic_chip_data *gic = &gic_data[0]; 268 void __iomem *cpu_base = gic_data_cpu_base(gic); 269 270 do { 271 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 272 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 273 274 if (likely(irqnr > 15 && irqnr < 1021)) { 275 handle_domain_irq(gic->domain, irqnr, regs); 276 continue; 277 } 278 if (irqnr < 16) { 279 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 280#ifdef CONFIG_SMP 281 /* 282 * Ensure any shared data written by the CPU sending 283 * the IPI is read after we've read the ACK register 284 * on the GIC. 285 * 286 * Pairs with the write barrier in gic_raise_softirq 287 */ 288 smp_rmb(); 289 handle_IPI(irqnr, regs); 290#endif 291 continue; 292 } 293 break; 294 } while (1); 295} 296 297static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 298{ 299 struct gic_chip_data *chip_data = irq_get_handler_data(irq); 300 struct irq_chip *chip = irq_get_chip(irq); 301 unsigned int cascade_irq, gic_irq; 302 unsigned long status; 303 304 chained_irq_enter(chip, desc); 305 306 raw_spin_lock(&irq_controller_lock); 307 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 308 raw_spin_unlock(&irq_controller_lock); 309 310 gic_irq = (status & GICC_IAR_INT_ID_MASK); 311 if (gic_irq == GICC_INT_SPURIOUS) 312 goto out; 313 314 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 315 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 316 handle_bad_irq(cascade_irq, desc); 317 else 318 generic_handle_irq(cascade_irq); 319 320 out: 321 chained_irq_exit(chip, desc); 322} 323 324static struct irq_chip gic_chip = { 325 .name = "GIC", 326 .irq_mask = gic_mask_irq, 327 .irq_unmask = gic_unmask_irq, 328 .irq_eoi = gic_eoi_irq, 329 .irq_set_type = gic_set_type, 330#ifdef CONFIG_SMP 331 .irq_set_affinity = gic_set_affinity, 332#endif 333 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 334 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 335}; 336 337void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 338{ 339 if (gic_nr >= MAX_GIC_NR) 340 BUG(); 341 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) 342 BUG(); 343 irq_set_chained_handler(irq, gic_handle_cascade_irq); 344} 345 346static u8 gic_get_cpumask(struct gic_chip_data *gic) 347{ 348 void __iomem *base = gic_data_dist_base(gic); 349 u32 mask, i; 350 351 for (i = mask = 0; i < 32; i += 4) { 352 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 353 mask |= mask >> 16; 354 mask |= mask >> 8; 355 if (mask) 356 break; 357 } 358 359 if (!mask && num_possible_cpus() > 1) 360 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 361 362 return mask; 363} 364 365static void gic_cpu_if_up(void) 366{ 367 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 368 u32 bypass = 0; 369 370 /* 371 * Preserve bypass disable bits to be written back later 372 */ 373 bypass = readl(cpu_base + GIC_CPU_CTRL); 374 bypass &= GICC_DIS_BYPASS_MASK; 375 376 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 377} 378 379 380static void __init gic_dist_init(struct gic_chip_data *gic) 381{ 382 unsigned int i; 383 u32 cpumask; 384 unsigned int gic_irqs = gic->gic_irqs; 385 void __iomem *base = gic_data_dist_base(gic); 386 387 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 388 389 /* 390 * Set all global interrupts to this CPU only. 391 */ 392 cpumask = gic_get_cpumask(gic); 393 cpumask |= cpumask << 8; 394 cpumask |= cpumask << 16; 395 for (i = 32; i < gic_irqs; i += 4) 396 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 397 398 gic_dist_config(base, gic_irqs, NULL); 399 400 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 401} 402 403static void gic_cpu_init(struct gic_chip_data *gic) 404{ 405 void __iomem *dist_base = gic_data_dist_base(gic); 406 void __iomem *base = gic_data_cpu_base(gic); 407 unsigned int cpu_mask, cpu = smp_processor_id(); 408 int i; 409 410 /* 411 * Get what the GIC says our CPU mask is. 412 */ 413 BUG_ON(cpu >= NR_GIC_CPU_IF); 414 cpu_mask = gic_get_cpumask(gic); 415 gic_cpu_map[cpu] = cpu_mask; 416 417 /* 418 * Clear our mask from the other map entries in case they're 419 * still undefined. 420 */ 421 for (i = 0; i < NR_GIC_CPU_IF; i++) 422 if (i != cpu) 423 gic_cpu_map[i] &= ~cpu_mask; 424 425 gic_cpu_config(dist_base, NULL); 426 427 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 428 gic_cpu_if_up(); 429} 430 431void gic_cpu_if_down(void) 432{ 433 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 434 u32 val = 0; 435 436 val = readl(cpu_base + GIC_CPU_CTRL); 437 val &= ~GICC_ENABLE; 438 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 439} 440 441#ifdef CONFIG_CPU_PM 442/* 443 * Saves the GIC distributor registers during suspend or idle. Must be called 444 * with interrupts disabled but before powering down the GIC. After calling 445 * this function, no interrupts will be delivered by the GIC, and another 446 * platform-specific wakeup source must be enabled. 447 */ 448static void gic_dist_save(unsigned int gic_nr) 449{ 450 unsigned int gic_irqs; 451 void __iomem *dist_base; 452 int i; 453 454 if (gic_nr >= MAX_GIC_NR) 455 BUG(); 456 457 gic_irqs = gic_data[gic_nr].gic_irqs; 458 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 459 460 if (!dist_base) 461 return; 462 463 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 464 gic_data[gic_nr].saved_spi_conf[i] = 465 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 466 467 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 468 gic_data[gic_nr].saved_spi_target[i] = 469 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 470 471 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 472 gic_data[gic_nr].saved_spi_enable[i] = 473 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 474} 475 476/* 477 * Restores the GIC distributor registers during resume or when coming out of 478 * idle. Must be called before enabling interrupts. If a level interrupt 479 * that occured while the GIC was suspended is still present, it will be 480 * handled normally, but any edge interrupts that occured will not be seen by 481 * the GIC and need to be handled by the platform-specific wakeup source. 482 */ 483static void gic_dist_restore(unsigned int gic_nr) 484{ 485 unsigned int gic_irqs; 486 unsigned int i; 487 void __iomem *dist_base; 488 489 if (gic_nr >= MAX_GIC_NR) 490 BUG(); 491 492 gic_irqs = gic_data[gic_nr].gic_irqs; 493 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 494 495 if (!dist_base) 496 return; 497 498 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 499 500 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 501 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], 502 dist_base + GIC_DIST_CONFIG + i * 4); 503 504 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 505 writel_relaxed(GICD_INT_DEF_PRI_X4, 506 dist_base + GIC_DIST_PRI + i * 4); 507 508 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 509 writel_relaxed(gic_data[gic_nr].saved_spi_target[i], 510 dist_base + GIC_DIST_TARGET + i * 4); 511 512 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 513 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], 514 dist_base + GIC_DIST_ENABLE_SET + i * 4); 515 516 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 517} 518 519static void gic_cpu_save(unsigned int gic_nr) 520{ 521 int i; 522 u32 *ptr; 523 void __iomem *dist_base; 524 void __iomem *cpu_base; 525 526 if (gic_nr >= MAX_GIC_NR) 527 BUG(); 528 529 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 530 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 531 532 if (!dist_base || !cpu_base) 533 return; 534 535 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 536 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 537 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 538 539 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 540 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 541 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 542 543} 544 545static void gic_cpu_restore(unsigned int gic_nr) 546{ 547 int i; 548 u32 *ptr; 549 void __iomem *dist_base; 550 void __iomem *cpu_base; 551 552 if (gic_nr >= MAX_GIC_NR) 553 BUG(); 554 555 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 556 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 557 558 if (!dist_base || !cpu_base) 559 return; 560 561 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 562 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 563 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 564 565 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 566 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 567 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 568 569 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 570 writel_relaxed(GICD_INT_DEF_PRI_X4, 571 dist_base + GIC_DIST_PRI + i * 4); 572 573 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 574 gic_cpu_if_up(); 575} 576 577static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 578{ 579 int i; 580 581 for (i = 0; i < MAX_GIC_NR; i++) { 582#ifdef CONFIG_GIC_NON_BANKED 583 /* Skip over unused GICs */ 584 if (!gic_data[i].get_base) 585 continue; 586#endif 587 switch (cmd) { 588 case CPU_PM_ENTER: 589 gic_cpu_save(i); 590 break; 591 case CPU_PM_ENTER_FAILED: 592 case CPU_PM_EXIT: 593 gic_cpu_restore(i); 594 break; 595 case CPU_CLUSTER_PM_ENTER: 596 gic_dist_save(i); 597 break; 598 case CPU_CLUSTER_PM_ENTER_FAILED: 599 case CPU_CLUSTER_PM_EXIT: 600 gic_dist_restore(i); 601 break; 602 } 603 } 604 605 return NOTIFY_OK; 606} 607 608static struct notifier_block gic_notifier_block = { 609 .notifier_call = gic_notifier, 610}; 611 612static void __init gic_pm_init(struct gic_chip_data *gic) 613{ 614 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 615 sizeof(u32)); 616 BUG_ON(!gic->saved_ppi_enable); 617 618 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 619 sizeof(u32)); 620 BUG_ON(!gic->saved_ppi_conf); 621 622 if (gic == &gic_data[0]) 623 cpu_pm_register_notifier(&gic_notifier_block); 624} 625#else 626static void __init gic_pm_init(struct gic_chip_data *gic) 627{ 628} 629#endif 630 631#ifdef CONFIG_SMP 632static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 633{ 634 int cpu; 635 unsigned long flags, map = 0; 636 637 raw_spin_lock_irqsave(&irq_controller_lock, flags); 638 639 /* Convert our logical CPU mask into a physical one. */ 640 for_each_cpu(cpu, mask) 641 map |= gic_cpu_map[cpu]; 642 643 /* 644 * Ensure that stores to Normal memory are visible to the 645 * other CPUs before they observe us issuing the IPI. 646 */ 647 dmb(ishst); 648 649 /* this always happens on GIC0 */ 650 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 651 652 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 653} 654#endif 655 656#ifdef CONFIG_BL_SWITCHER 657/* 658 * gic_send_sgi - send a SGI directly to given CPU interface number 659 * 660 * cpu_id: the ID for the destination CPU interface 661 * irq: the IPI number to send a SGI for 662 */ 663void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 664{ 665 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 666 cpu_id = 1 << cpu_id; 667 /* this always happens on GIC0 */ 668 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 669} 670 671/* 672 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 673 * 674 * @cpu: the logical CPU number to get the GIC ID for. 675 * 676 * Return the CPU interface ID for the given logical CPU number, 677 * or -1 if the CPU number is too large or the interface ID is 678 * unknown (more than one bit set). 679 */ 680int gic_get_cpu_id(unsigned int cpu) 681{ 682 unsigned int cpu_bit; 683 684 if (cpu >= NR_GIC_CPU_IF) 685 return -1; 686 cpu_bit = gic_cpu_map[cpu]; 687 if (cpu_bit & (cpu_bit - 1)) 688 return -1; 689 return __ffs(cpu_bit); 690} 691 692/* 693 * gic_migrate_target - migrate IRQs to another CPU interface 694 * 695 * @new_cpu_id: the CPU target ID to migrate IRQs to 696 * 697 * Migrate all peripheral interrupts with a target matching the current CPU 698 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 699 * is also updated. Targets to other CPU interfaces are unchanged. 700 * This must be called with IRQs locally disabled. 701 */ 702void gic_migrate_target(unsigned int new_cpu_id) 703{ 704 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 705 void __iomem *dist_base; 706 int i, ror_val, cpu = smp_processor_id(); 707 u32 val, cur_target_mask, active_mask; 708 709 if (gic_nr >= MAX_GIC_NR) 710 BUG(); 711 712 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 713 if (!dist_base) 714 return; 715 gic_irqs = gic_data[gic_nr].gic_irqs; 716 717 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 718 cur_target_mask = 0x01010101 << cur_cpu_id; 719 ror_val = (cur_cpu_id - new_cpu_id) & 31; 720 721 raw_spin_lock(&irq_controller_lock); 722 723 /* Update the target interface for this logical CPU */ 724 gic_cpu_map[cpu] = 1 << new_cpu_id; 725 726 /* 727 * Find all the peripheral interrupts targetting the current 728 * CPU interface and migrate them to the new CPU interface. 729 * We skip DIST_TARGET 0 to 7 as they are read-only. 730 */ 731 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 732 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 733 active_mask = val & cur_target_mask; 734 if (active_mask) { 735 val &= ~active_mask; 736 val |= ror32(active_mask, ror_val); 737 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 738 } 739 } 740 741 raw_spin_unlock(&irq_controller_lock); 742 743 /* 744 * Now let's migrate and clear any potential SGIs that might be 745 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 746 * is a banked register, we can only forward the SGI using 747 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 748 * doesn't use that information anyway. 749 * 750 * For the same reason we do not adjust SGI source information 751 * for previously sent SGIs by us to other CPUs either. 752 */ 753 for (i = 0; i < 16; i += 4) { 754 int j; 755 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 756 if (!val) 757 continue; 758 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 759 for (j = i; j < i + 4; j++) { 760 if (val & 0xff) 761 writel_relaxed((1 << (new_cpu_id + 16)) | j, 762 dist_base + GIC_DIST_SOFTINT); 763 val >>= 8; 764 } 765 } 766} 767 768/* 769 * gic_get_sgir_physaddr - get the physical address for the SGI register 770 * 771 * REturn the physical address of the SGI register to be used 772 * by some early assembly code when the kernel is not yet available. 773 */ 774static unsigned long gic_dist_physaddr; 775 776unsigned long gic_get_sgir_physaddr(void) 777{ 778 if (!gic_dist_physaddr) 779 return 0; 780 return gic_dist_physaddr + GIC_DIST_SOFTINT; 781} 782 783void __init gic_init_physaddr(struct device_node *node) 784{ 785 struct resource res; 786 if (of_address_to_resource(node, 0, &res) == 0) { 787 gic_dist_physaddr = res.start; 788 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 789 } 790} 791 792#else 793#define gic_init_physaddr(node) do { } while (0) 794#endif 795 796static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 797 irq_hw_number_t hw) 798{ 799 if (hw < 32) { 800 irq_set_percpu_devid(irq); 801 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 802 handle_percpu_devid_irq, NULL, NULL); 803 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 804 } else { 805 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 806 handle_fasteoi_irq, NULL, NULL); 807 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 808 } 809 return 0; 810} 811 812static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 813{ 814} 815 816static int gic_irq_domain_xlate(struct irq_domain *d, 817 struct device_node *controller, 818 const u32 *intspec, unsigned int intsize, 819 unsigned long *out_hwirq, unsigned int *out_type) 820{ 821 unsigned long ret = 0; 822 823 if (d->of_node != controller) 824 return -EINVAL; 825 if (intsize < 3) 826 return -EINVAL; 827 828 /* Get the interrupt number and add 16 to skip over SGIs */ 829 *out_hwirq = intspec[1] + 16; 830 831 /* For SPIs, we need to add 16 more to get the GIC irq ID number */ 832 if (!intspec[0]) 833 *out_hwirq += 16; 834 835 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 836 837 return ret; 838} 839 840#ifdef CONFIG_SMP 841static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 842 void *hcpu) 843{ 844 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 845 gic_cpu_init(&gic_data[0]); 846 return NOTIFY_OK; 847} 848 849/* 850 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 851 * priority because the GIC needs to be up before the ARM generic timers. 852 */ 853static struct notifier_block gic_cpu_notifier = { 854 .notifier_call = gic_secondary_init, 855 .priority = 100, 856}; 857#endif 858 859static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 860 unsigned int nr_irqs, void *arg) 861{ 862 int i, ret; 863 irq_hw_number_t hwirq; 864 unsigned int type = IRQ_TYPE_NONE; 865 struct of_phandle_args *irq_data = arg; 866 867 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 868 irq_data->args_count, &hwirq, &type); 869 if (ret) 870 return ret; 871 872 for (i = 0; i < nr_irqs; i++) 873 gic_irq_domain_map(domain, virq + i, hwirq + i); 874 875 return 0; 876} 877 878static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 879 .xlate = gic_irq_domain_xlate, 880 .alloc = gic_irq_domain_alloc, 881 .free = irq_domain_free_irqs_top, 882}; 883 884static const struct irq_domain_ops gic_irq_domain_ops = { 885 .map = gic_irq_domain_map, 886 .unmap = gic_irq_domain_unmap, 887 .xlate = gic_irq_domain_xlate, 888}; 889 890void gic_set_irqchip_flags(unsigned long flags) 891{ 892 gic_chip.flags |= flags; 893} 894 895void __init gic_init_bases(unsigned int gic_nr, int irq_start, 896 void __iomem *dist_base, void __iomem *cpu_base, 897 u32 percpu_offset, struct device_node *node) 898{ 899 irq_hw_number_t hwirq_base; 900 struct gic_chip_data *gic; 901 int gic_irqs, irq_base, i; 902 903 BUG_ON(gic_nr >= MAX_GIC_NR); 904 905 gic = &gic_data[gic_nr]; 906#ifdef CONFIG_GIC_NON_BANKED 907 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 908 unsigned int cpu; 909 910 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 911 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 912 if (WARN_ON(!gic->dist_base.percpu_base || 913 !gic->cpu_base.percpu_base)) { 914 free_percpu(gic->dist_base.percpu_base); 915 free_percpu(gic->cpu_base.percpu_base); 916 return; 917 } 918 919 for_each_possible_cpu(cpu) { 920 u32 mpidr = cpu_logical_map(cpu); 921 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 922 unsigned long offset = percpu_offset * core_id; 923 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; 924 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; 925 } 926 927 gic_set_base_accessor(gic, gic_get_percpu_base); 928 } else 929#endif 930 { /* Normal, sane GIC... */ 931 WARN(percpu_offset, 932 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 933 percpu_offset); 934 gic->dist_base.common_base = dist_base; 935 gic->cpu_base.common_base = cpu_base; 936 gic_set_base_accessor(gic, gic_get_common_base); 937 } 938 939 /* 940 * Initialize the CPU interface map to all CPUs. 941 * It will be refined as each CPU probes its ID. 942 */ 943 for (i = 0; i < NR_GIC_CPU_IF; i++) 944 gic_cpu_map[i] = 0xff; 945 946 /* 947 * Find out how many interrupts are supported. 948 * The GIC only supports up to 1020 interrupt sources. 949 */ 950 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 951 gic_irqs = (gic_irqs + 1) * 32; 952 if (gic_irqs > 1020) 953 gic_irqs = 1020; 954 gic->gic_irqs = gic_irqs; 955 956 if (node) { /* DT case */ 957 gic->domain = irq_domain_add_linear(node, gic_irqs, 958 &gic_irq_domain_hierarchy_ops, 959 gic); 960 } else { /* Non-DT case */ 961 /* 962 * For primary GICs, skip over SGIs. 963 * For secondary GICs, skip over PPIs, too. 964 */ 965 if (gic_nr == 0 && (irq_start & 31) > 0) { 966 hwirq_base = 16; 967 if (irq_start != -1) 968 irq_start = (irq_start & ~31) + 16; 969 } else { 970 hwirq_base = 32; 971 } 972 973 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 974 975 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 976 numa_node_id()); 977 if (IS_ERR_VALUE(irq_base)) { 978 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 979 irq_start); 980 irq_base = irq_start; 981 } 982 983 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, 984 hwirq_base, &gic_irq_domain_ops, gic); 985 } 986 987 if (WARN_ON(!gic->domain)) 988 return; 989 990 if (gic_nr == 0) { 991#ifdef CONFIG_SMP 992 set_smp_cross_call(gic_raise_softirq); 993 register_cpu_notifier(&gic_cpu_notifier); 994#endif 995 set_handle_irq(gic_handle_irq); 996 } 997 998 gic_dist_init(gic); 999 gic_cpu_init(gic); 1000 gic_pm_init(gic); 1001} 1002 1003#ifdef CONFIG_OF 1004static int gic_cnt __initdata; 1005 1006static int __init 1007gic_of_init(struct device_node *node, struct device_node *parent) 1008{ 1009 void __iomem *cpu_base; 1010 void __iomem *dist_base; 1011 u32 percpu_offset; 1012 int irq; 1013 1014 if (WARN_ON(!node)) 1015 return -ENODEV; 1016 1017 dist_base = of_iomap(node, 0); 1018 WARN(!dist_base, "unable to map gic dist registers\n"); 1019 1020 cpu_base = of_iomap(node, 1); 1021 WARN(!cpu_base, "unable to map gic cpu registers\n"); 1022 1023 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 1024 percpu_offset = 0; 1025 1026 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); 1027 if (!gic_cnt) 1028 gic_init_physaddr(node); 1029 1030 if (parent) { 1031 irq = irq_of_parse_and_map(node, 0); 1032 gic_cascade_irq(gic_cnt, irq); 1033 } 1034 1035 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1036 gicv2m_of_init(node, gic_data[gic_cnt].domain); 1037 1038 gic_cnt++; 1039 return 0; 1040} 1041IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1042IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1043IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1044IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1045IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1046IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1047IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1048IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1049 1050#endif 1051 1052#ifdef CONFIG_ACPI 1053static phys_addr_t dist_phy_base, cpu_phy_base __initdata; 1054 1055static int __init 1056gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, 1057 const unsigned long end) 1058{ 1059 struct acpi_madt_generic_interrupt *processor; 1060 phys_addr_t gic_cpu_base; 1061 static int cpu_base_assigned; 1062 1063 processor = (struct acpi_madt_generic_interrupt *)header; 1064 1065 if (BAD_MADT_ENTRY(processor, end)) 1066 return -EINVAL; 1067 1068 /* 1069 * There is no support for non-banked GICv1/2 register in ACPI spec. 1070 * All CPU interface addresses have to be the same. 1071 */ 1072 gic_cpu_base = processor->base_address; 1073 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) 1074 return -EINVAL; 1075 1076 cpu_phy_base = gic_cpu_base; 1077 cpu_base_assigned = 1; 1078 return 0; 1079} 1080 1081static int __init 1082gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, 1083 const unsigned long end) 1084{ 1085 struct acpi_madt_generic_distributor *dist; 1086 1087 dist = (struct acpi_madt_generic_distributor *)header; 1088 1089 if (BAD_MADT_ENTRY(dist, end)) 1090 return -EINVAL; 1091 1092 dist_phy_base = dist->base_address; 1093 return 0; 1094} 1095 1096int __init 1097gic_v2_acpi_init(struct acpi_table_header *table) 1098{ 1099 void __iomem *cpu_base, *dist_base; 1100 int count; 1101 1102 /* Collect CPU base addresses */ 1103 count = acpi_parse_entries(ACPI_SIG_MADT, 1104 sizeof(struct acpi_table_madt), 1105 gic_acpi_parse_madt_cpu, table, 1106 ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); 1107 if (count <= 0) { 1108 pr_err("No valid GICC entries exist\n"); 1109 return -EINVAL; 1110 } 1111 1112 /* 1113 * Find distributor base address. We expect one distributor entry since 1114 * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. 1115 */ 1116 count = acpi_parse_entries(ACPI_SIG_MADT, 1117 sizeof(struct acpi_table_madt), 1118 gic_acpi_parse_madt_distributor, table, 1119 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); 1120 if (count <= 0) { 1121 pr_err("No valid GICD entries exist\n"); 1122 return -EINVAL; 1123 } else if (count > 1) { 1124 pr_err("More than one GICD entry detected\n"); 1125 return -EINVAL; 1126 } 1127 1128 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1129 if (!cpu_base) { 1130 pr_err("Unable to map GICC registers\n"); 1131 return -ENOMEM; 1132 } 1133 1134 dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); 1135 if (!dist_base) { 1136 pr_err("Unable to map GICD registers\n"); 1137 iounmap(cpu_base); 1138 return -ENOMEM; 1139 } 1140 1141 /* 1142 * Initialize zero GIC instance (no multi-GIC support). Also, set GIC 1143 * as default IRQ domain to allow for GSI registration and GSI to IRQ 1144 * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). 1145 */ 1146 gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); 1147 irq_set_default_host(gic_data[0].domain); 1148 1149 acpi_irq_model = ACPI_IRQ_MODEL_GIC; 1150 return 0; 1151} 1152#endif 1153