1/* saa711x - Philips SAA711x video decoder register specifications
2 *
3 * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@infradead.org>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 * GNU General Public License for more details.
14 */
15
16#define R_00_CHIP_VERSION                             0x00
17/* Video Decoder */
18	/* Video Decoder - Frontend part */
19#define R_01_INC_DELAY                                0x01
20#define R_02_INPUT_CNTL_1                             0x02
21#define R_03_INPUT_CNTL_2                             0x03
22#define R_04_INPUT_CNTL_3                             0x04
23#define R_05_INPUT_CNTL_4                             0x05
24	/* Video Decoder - Decoder part */
25#define R_06_H_SYNC_START                             0x06
26#define R_07_H_SYNC_STOP                              0x07
27#define R_08_SYNC_CNTL                                0x08
28#define R_09_LUMA_CNTL                                0x09
29#define R_0A_LUMA_BRIGHT_CNTL                         0x0a
30#define R_0B_LUMA_CONTRAST_CNTL                       0x0b
31#define R_0C_CHROMA_SAT_CNTL                          0x0c
32#define R_0D_CHROMA_HUE_CNTL                          0x0d
33#define R_0E_CHROMA_CNTL_1                            0x0e
34#define R_0F_CHROMA_GAIN_CNTL                         0x0f
35#define R_10_CHROMA_CNTL_2                            0x10
36#define R_11_MODE_DELAY_CNTL                          0x11
37#define R_12_RT_SIGNAL_CNTL                           0x12
38#define R_13_RT_X_PORT_OUT_CNTL                       0x13
39#define R_14_ANAL_ADC_COMPAT_CNTL                     0x14
40#define R_15_VGATE_START_FID_CHG                      0x15
41#define R_16_VGATE_STOP                               0x16
42#define R_17_MISC_VGATE_CONF_AND_MSB                  0x17
43#define R_18_RAW_DATA_GAIN_CNTL                       0x18
44#define R_19_RAW_DATA_OFF_CNTL                        0x19
45#define R_1A_COLOR_KILL_LVL_CNTL                      0x1a
46#define R_1B_MISC_TVVCRDET                            0x1b
47#define R_1C_ENHAN_COMB_CTRL1                         0x1c
48#define R_1D_ENHAN_COMB_CTRL2                         0x1d
49#define R_1E_STATUS_BYTE_1_VD_DEC                     0x1e
50#define R_1F_STATUS_BYTE_2_VD_DEC                     0x1f
51
52/* Component processing and interrupt masking part */
53#define R_23_INPUT_CNTL_5                             0x23
54#define R_24_INPUT_CNTL_6                             0x24
55#define R_25_INPUT_CNTL_7                             0x25
56#define R_29_COMP_DELAY                               0x29
57#define R_2A_COMP_BRIGHT_CNTL                         0x2a
58#define R_2B_COMP_CONTRAST_CNTL                       0x2b
59#define R_2C_COMP_SAT_CNTL                            0x2c
60#define R_2D_INTERRUPT_MASK_1                         0x2d
61#define R_2E_INTERRUPT_MASK_2                         0x2e
62#define R_2F_INTERRUPT_MASK_3                         0x2f
63
64/* Audio clock generator part */
65#define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD            0x30
66#define R_34_AUD_MAST_CLK_NOMINAL_INC                 0x34
67#define R_38_CLK_RATIO_AMXCLK_TO_ASCLK                0x38
68#define R_39_CLK_RATIO_ASCLK_TO_ALRCLK                0x39
69#define R_3A_AUD_CLK_GEN_BASIC_SETUP                  0x3a
70
71/* General purpose VBI data slicer part */
72#define R_40_SLICER_CNTL_1                            0x40
73#define R_41_LCR_BASE                                 0x41
74#define R_58_PROGRAM_FRAMING_CODE                     0x58
75#define R_59_H_OFF_FOR_SLICER                         0x59
76#define R_5A_V_OFF_FOR_SLICER                         0x5a
77#define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF          0x5b
78#define R_5D_DID                                      0x5d
79#define R_5E_SDID                                     0x5e
80#define R_60_SLICER_STATUS_BYTE_0                     0x60
81#define R_61_SLICER_STATUS_BYTE_1                     0x61
82#define R_62_SLICER_STATUS_BYTE_2                     0x62
83
84/* X port, I port and the scaler part */
85	/* Task independent global settings */
86#define R_80_GLOBAL_CNTL_1                            0x80
87#define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F    0x81
88#define R_83_X_PORT_I_O_ENA_AND_OUT_CLK               0x83
89#define R_84_I_PORT_SIGNAL_DEF                        0x84
90#define R_85_I_PORT_SIGNAL_POLAR                      0x85
91#define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT          0x86
92#define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED         0x87
93#define R_88_POWER_SAVE_ADC_PORT_CNTL                 0x88
94#define R_8F_STATUS_INFO_SCALER                       0x8f
95	/* Task A definition */
96		/* Basic settings and acquisition window definition */
97#define R_90_A_TASK_HANDLING_CNTL                     0x90
98#define R_91_A_X_PORT_FORMATS_AND_CONF                0x91
99#define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL          0x92
100#define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF         0x93
101#define R_94_A_HORIZ_INPUT_WINDOW_START               0x94
102#define R_95_A_HORIZ_INPUT_WINDOW_START_MSB           0x95
103#define R_96_A_HORIZ_INPUT_WINDOW_LENGTH              0x96
104#define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB          0x97
105#define R_98_A_VERT_INPUT_WINDOW_START                0x98
106#define R_99_A_VERT_INPUT_WINDOW_START_MSB            0x99
107#define R_9A_A_VERT_INPUT_WINDOW_LENGTH               0x9a
108#define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB           0x9b
109#define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH             0x9c
110#define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0x9d
111#define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH              0x9e
112#define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB          0x9f
113		/* FIR filtering and prescaling */
114#define R_A0_A_HORIZ_PRESCALING                       0xa0
115#define R_A1_A_ACCUMULATION_LENGTH                    0xa1
116#define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xa2
117#define R_A4_A_LUMA_BRIGHTNESS_CNTL                   0xa4
118#define R_A5_A_LUMA_CONTRAST_CNTL                     0xa5
119#define R_A6_A_CHROMA_SATURATION_CNTL                 0xa6
120		/* Horizontal phase scaling */
121#define R_A8_A_HORIZ_LUMA_SCALING_INC                 0xa8
122#define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB             0xa9
123#define R_AA_A_HORIZ_LUMA_PHASE_OFF                   0xaa
124#define R_AC_A_HORIZ_CHROMA_SCALING_INC               0xac
125#define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB           0xad
126#define R_AE_A_HORIZ_CHROMA_PHASE_OFF                 0xae
127#define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB             0xaf
128		/* Vertical scaling */
129#define R_B0_A_VERT_LUMA_SCALING_INC                  0xb0
130#define R_B1_A_VERT_LUMA_SCALING_INC_MSB              0xb1
131#define R_B2_A_VERT_CHROMA_SCALING_INC                0xb2
132#define R_B3_A_VERT_CHROMA_SCALING_INC_MSB            0xb3
133#define R_B4_A_VERT_SCALING_MODE_CNTL                 0xb4
134#define R_B8_A_VERT_CHROMA_PHASE_OFF_00               0xb8
135#define R_B9_A_VERT_CHROMA_PHASE_OFF_01               0xb9
136#define R_BA_A_VERT_CHROMA_PHASE_OFF_10               0xba
137#define R_BB_A_VERT_CHROMA_PHASE_OFF_11               0xbb
138#define R_BC_A_VERT_LUMA_PHASE_OFF_00                 0xbc
139#define R_BD_A_VERT_LUMA_PHASE_OFF_01                 0xbd
140#define R_BE_A_VERT_LUMA_PHASE_OFF_10                 0xbe
141#define R_BF_A_VERT_LUMA_PHASE_OFF_11                 0xbf
142	/* Task B definition */
143		/* Basic settings and acquisition window definition */
144#define R_C0_B_TASK_HANDLING_CNTL                     0xc0
145#define R_C1_B_X_PORT_FORMATS_AND_CONF                0xc1
146#define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION      0xc2
147#define R_C3_B_I_PORT_FORMATS_AND_CONF                0xc3
148#define R_C4_B_HORIZ_INPUT_WINDOW_START               0xc4
149#define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB           0xc5
150#define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH              0xc6
151#define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB          0xc7
152#define R_C8_B_VERT_INPUT_WINDOW_START                0xc8
153#define R_C9_B_VERT_INPUT_WINDOW_START_MSB            0xc9
154#define R_CA_B_VERT_INPUT_WINDOW_LENGTH               0xca
155#define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB           0xcb
156#define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH             0xcc
157#define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB         0xcd
158#define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH              0xce
159#define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB          0xcf
160		/* FIR filtering and prescaling */
161#define R_D0_B_HORIZ_PRESCALING                       0xd0
162#define R_D1_B_ACCUMULATION_LENGTH                    0xd1
163#define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER    0xd2
164#define R_D4_B_LUMA_BRIGHTNESS_CNTL                   0xd4
165#define R_D5_B_LUMA_CONTRAST_CNTL                     0xd5
166#define R_D6_B_CHROMA_SATURATION_CNTL                 0xd6
167		/* Horizontal phase scaling */
168#define R_D8_B_HORIZ_LUMA_SCALING_INC                 0xd8
169#define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB             0xd9
170#define R_DA_B_HORIZ_LUMA_PHASE_OFF                   0xda
171#define R_DC_B_HORIZ_CHROMA_SCALING                   0xdc
172#define R_DD_B_HORIZ_CHROMA_SCALING_MSB               0xdd
173#define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA              0xde
174		/* Vertical scaling */
175#define R_E0_B_VERT_LUMA_SCALING_INC                  0xe0
176#define R_E1_B_VERT_LUMA_SCALING_INC_MSB              0xe1
177#define R_E2_B_VERT_CHROMA_SCALING_INC                0xe2
178#define R_E3_B_VERT_CHROMA_SCALING_INC_MSB            0xe3
179#define R_E4_B_VERT_SCALING_MODE_CNTL                 0xe4
180#define R_E8_B_VERT_CHROMA_PHASE_OFF_00               0xe8
181#define R_E9_B_VERT_CHROMA_PHASE_OFF_01               0xe9
182#define R_EA_B_VERT_CHROMA_PHASE_OFF_10               0xea
183#define R_EB_B_VERT_CHROMA_PHASE_OFF_11               0xeb
184#define R_EC_B_VERT_LUMA_PHASE_OFF_00                 0xec
185#define R_ED_B_VERT_LUMA_PHASE_OFF_01                 0xed
186#define R_EE_B_VERT_LUMA_PHASE_OFF_10                 0xee
187#define R_EF_B_VERT_LUMA_PHASE_OFF_11                 0xef
188
189/* second PLL (PLL2) and Pulsegenerator Programming */
190#define R_F0_LFCO_PER_LINE                            0xf0
191#define R_F1_P_I_PARAM_SELECT                         0xf1
192#define R_F2_NOMINAL_PLL2_DTO                         0xf2
193#define R_F3_PLL_INCREMENT                            0xf3
194#define R_F4_PLL2_STATUS                              0xf4
195#define R_F5_PULSGEN_LINE_LENGTH                      0xf5
196#define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG      0xf6
197#define R_F7_PULSE_A_POS_MSB                          0xf7
198#define R_F8_PULSE_B_POS                              0xf8
199#define R_F9_PULSE_B_POS_MSB                          0xf9
200#define R_FA_PULSE_C_POS                              0xfa
201#define R_FB_PULSE_C_POS_MSB                          0xfb
202#define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES     0xff
203
204/* SAA7113 bit-masks */
205#define SAA7113_R_08_HTC_OFFSET 3
206#define SAA7113_R_08_HTC_MASK (0x3 << SAA7113_R_08_HTC_OFFSET)
207#define SAA7113_R_08_FSEL 0x40
208#define SAA7113_R_08_AUFD 0x80
209
210#define SAA7113_R_10_VRLN_OFFSET 3
211#define SAA7113_R_10_VRLN_MASK (0x1 << SAA7113_R_10_VRLN_OFFSET)
212#define SAA7113_R_10_OFTS_OFFSET 6
213#define SAA7113_R_10_OFTS_MASK (0x3 << SAA7113_R_10_OFTS_OFFSET)
214
215#define SAA7113_R_12_RTS0_OFFSET 0
216#define SAA7113_R_12_RTS0_MASK (0xf << SAA7113_R_12_RTS0_OFFSET)
217#define SAA7113_R_12_RTS1_OFFSET 4
218#define SAA7113_R_12_RTS1_MASK (0xf << SAA7113_R_12_RTS1_OFFSET)
219
220#define SAA7113_R_13_ADLSB_OFFSET 7
221#define SAA7113_R_13_ADLSB_MASK (0x1 << SAA7113_R_13_ADLSB_OFFSET)
222
223#if 0
224/* Those structs will be used in the future for debug purposes */
225struct saa711x_reg_descr {
226	u8 reg;
227	int count;
228	char *name;
229};
230
231struct saa711x_reg_descr saa711x_regs[] = {
232	/* REG COUNT NAME */
233	{R_00_CHIP_VERSION,1,
234	 "Chip version"},
235
236	/* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */
237
238	/* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
239	{R_01_INC_DELAY,1,
240	 "Increment delay"},
241	{R_02_INPUT_CNTL_1,1,
242	 "Analog input control 1"},
243	{R_03_INPUT_CNTL_2,1,
244	 "Analog input control 2"},
245	{R_04_INPUT_CNTL_3,1,
246	 "Analog input control 3"},
247	{R_05_INPUT_CNTL_4,1,
248	 "Analog input control 4"},
249
250	/* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
251	{R_06_H_SYNC_START,1,
252	 "Horizontal sync start"},
253	{R_07_H_SYNC_STOP,1,
254	 "Horizontal sync stop"},
255	{R_08_SYNC_CNTL,1,
256	 "Sync control"},
257	{R_09_LUMA_CNTL,1,
258	 "Luminance control"},
259	{R_0A_LUMA_BRIGHT_CNTL,1,
260	 "Luminance brightness control"},
261	{R_0B_LUMA_CONTRAST_CNTL,1,
262	 "Luminance contrast control"},
263	{R_0C_CHROMA_SAT_CNTL,1,
264	 "Chrominance saturation control"},
265	{R_0D_CHROMA_HUE_CNTL,1,
266	 "Chrominance hue control"},
267	{R_0E_CHROMA_CNTL_1,1,
268	 "Chrominance control 1"},
269	{R_0F_CHROMA_GAIN_CNTL,1,
270	 "Chrominance gain control"},
271	{R_10_CHROMA_CNTL_2,1,
272	 "Chrominance control 2"},
273	{R_11_MODE_DELAY_CNTL,1,
274	 "Mode/delay control"},
275	{R_12_RT_SIGNAL_CNTL,1,
276	 "RT signal control"},
277	{R_13_RT_X_PORT_OUT_CNTL,1,
278	 "RT/X port output control"},
279	{R_14_ANAL_ADC_COMPAT_CNTL,1,
280	 "Analog/ADC/compatibility control"},
281	{R_15_VGATE_START_FID_CHG,  1,
282	 "VGATE start FID change"},
283	{R_16_VGATE_STOP,1,
284	 "VGATE stop"},
285	{R_17_MISC_VGATE_CONF_AND_MSB,  1,
286	 "Miscellaneous VGATE configuration and MSBs"},
287	{R_18_RAW_DATA_GAIN_CNTL,1,
288	 "Raw data gain control",},
289	{R_19_RAW_DATA_OFF_CNTL,1,
290	 "Raw data offset control",},
291	{R_1A_COLOR_KILL_LVL_CNTL,1,
292	 "Color Killer Level Control"},
293	{ R_1B_MISC_TVVCRDET, 1,
294	  "MISC /TVVCRDET"},
295	{ R_1C_ENHAN_COMB_CTRL1, 1,
296	 "Enhanced comb ctrl1"},
297	{ R_1D_ENHAN_COMB_CTRL2, 1,
298	 "Enhanced comb ctrl1"},
299	{R_1E_STATUS_BYTE_1_VD_DEC,1,
300	 "Status byte 1 video decoder"},
301	{R_1F_STATUS_BYTE_2_VD_DEC,1,
302	 "Status byte 2 video decoder"},
303
304	/* Component processing and interrupt masking part:  0x20h to R_2F_INTERRUPT_MASK_3 */
305	/* 0x20 to 0x22 - Reserved */
306	{R_23_INPUT_CNTL_5,1,
307	 "Analog input control 5"},
308	{R_24_INPUT_CNTL_6,1,
309	 "Analog input control 6"},
310	{R_25_INPUT_CNTL_7,1,
311	 "Analog input control 7"},
312	/* 0x26 to 0x28 - Reserved */
313	{R_29_COMP_DELAY,1,
314	 "Component delay"},
315	{R_2A_COMP_BRIGHT_CNTL,1,
316	 "Component brightness control"},
317	{R_2B_COMP_CONTRAST_CNTL,1,
318	 "Component contrast control"},
319	{R_2C_COMP_SAT_CNTL,1,
320	 "Component saturation control"},
321	{R_2D_INTERRUPT_MASK_1,1,
322	 "Interrupt mask 1"},
323	{R_2E_INTERRUPT_MASK_2,1,
324	 "Interrupt mask 2"},
325	{R_2F_INTERRUPT_MASK_3,1,
326	 "Interrupt mask 3"},
327
328	/* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
329	{R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
330	 "Audio master clock cycles per field"},
331	/* 0x33 - Reserved */
332	{R_34_AUD_MAST_CLK_NOMINAL_INC,3,
333	 "Audio master clock nominal increment"},
334	/* 0x37 - Reserved */
335	{R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
336	 "Clock ratio AMXCLK to ASCLK"},
337	{R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
338	 "Clock ratio ASCLK to ALRCLK"},
339	{R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
340	 "Audio clock generator basic setup"},
341	/* 0x3b-0x3f - Reserved */
342
343	/* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
344	{R_40_SLICER_CNTL_1,1,
345	 "Slicer control 1"},
346	{R_41_LCR,23,
347	 "R_41_LCR"},
348	{R_58_PROGRAM_FRAMING_CODE,1,
349	 "Programmable framing code"},
350	{R_59_H_OFF_FOR_SLICER,1,
351	 "Horizontal offset for slicer"},
352	{R_5A_V_OFF_FOR_SLICER,1,
353	 "Vertical offset for slicer"},
354	{R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
355	 "Field offset and MSBs for horizontal and vertical offset"},
356	{R_5D_DID,1,
357	 "Header and data identification (R_5D_DID)"},
358	{R_5E_SDID,1,
359	 "Sliced data identification (R_5E_SDID) code"},
360	{R_60_SLICER_STATUS_BYTE_0,1,
361	 "Slicer status byte 0"},
362	{R_61_SLICER_STATUS_BYTE_1,1,
363	 "Slicer status byte 1"},
364	{R_62_SLICER_STATUS_BYTE_2,1,
365	 "Slicer status byte 2"},
366	/* 0x63-0x7f - Reserved */
367
368	/* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
369	/* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
370	{R_80_GLOBAL_CNTL_1,1,
371	 "Global control 1"},
372	{R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
373	 "Vertical sync and Field ID source selection, retimed V and F signals"},
374	/* 0x82 - Reserved */
375	{R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
376	 "X port I/O enable and output clock"},
377	{R_84_I_PORT_SIGNAL_DEF,1,
378	 "I port signal definitions"},
379	{R_85_I_PORT_SIGNAL_POLAR,1,
380	 "I port signal polarities"},
381	{R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
382	 "I port FIFO flag control and arbitration"},
383	{R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED,  1,
384	 "I port I/O enable output clock and gated"},
385	{R_88_POWER_SAVE_ADC_PORT_CNTL,1,
386	 "Power save/ADC port control"},
387	/* 089-0x8e - Reserved */
388	{R_8F_STATUS_INFO_SCALER,1,
389	 "Status information scaler part"},
390
391	/* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
392	/* Task A: Basic settings and acquisition window definition */
393	{R_90_A_TASK_HANDLING_CNTL,1,
394	 "Task A: Task handling control"},
395	{R_91_A_X_PORT_FORMATS_AND_CONF,1,
396	 "Task A: X port formats and configuration"},
397	{R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
398	 "Task A: X port input reference signal definition"},
399	{R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
400	 "Task A: I port output formats and configuration"},
401	{R_94_A_HORIZ_INPUT_WINDOW_START,2,
402	 "Task A: Horizontal input window start"},
403	{R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
404	 "Task A: Horizontal input window length"},
405	{R_98_A_VERT_INPUT_WINDOW_START,2,
406	 "Task A: Vertical input window start"},
407	{R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
408	 "Task A: Vertical input window length"},
409	{R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
410	 "Task A: Horizontal output window length"},
411	{R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
412	 "Task A: Vertical output window length"},
413
414	/* Task A: FIR filtering and prescaling */
415	{R_A0_A_HORIZ_PRESCALING,1,
416	 "Task A: Horizontal prescaling"},
417	{R_A1_A_ACCUMULATION_LENGTH,1,
418	 "Task A: Accumulation length"},
419	{R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
420	 "Task A: Prescaler DC gain and FIR prefilter"},
421	/* 0xa3 - Reserved */
422	{R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
423	 "Task A: Luminance brightness control"},
424	{R_A5_A_LUMA_CONTRAST_CNTL,1,
425	 "Task A: Luminance contrast control"},
426	{R_A6_A_CHROMA_SATURATION_CNTL,1,
427	 "Task A: Chrominance saturation control"},
428	/* 0xa7 - Reserved */
429
430	/* Task A: Horizontal phase scaling */
431	{R_A8_A_HORIZ_LUMA_SCALING_INC,2,
432	 "Task A: Horizontal luminance scaling increment"},
433	{R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
434	 "Task A: Horizontal luminance phase offset"},
435	/* 0xab - Reserved */
436	{R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
437	 "Task A: Horizontal chrominance scaling increment"},
438	{R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
439	 "Task A: Horizontal chrominance phase offset"},
440	/* 0xaf - Reserved */
441
442	/* Task A: Vertical scaling */
443	{R_B0_A_VERT_LUMA_SCALING_INC,2,
444	 "Task A: Vertical luminance scaling increment"},
445	{R_B2_A_VERT_CHROMA_SCALING_INC,2,
446	 "Task A: Vertical chrominance scaling increment"},
447	{R_B4_A_VERT_SCALING_MODE_CNTL,1,
448	 "Task A: Vertical scaling mode control"},
449	/* 0xb5-0xb7 - Reserved */
450	{R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
451	 "Task A: Vertical chrominance phase offset '00'"},
452	{R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
453	 "Task A: Vertical chrominance phase offset '01'"},
454	{R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
455	 "Task A: Vertical chrominance phase offset '10'"},
456	{R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
457	 "Task A: Vertical chrominance phase offset '11'"},
458	{R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
459	 "Task A: Vertical luminance phase offset '00'"},
460	{R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
461	 "Task A: Vertical luminance phase offset '01'"},
462	{R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
463	 "Task A: Vertical luminance phase offset '10'"},
464	{R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
465	 "Task A: Vertical luminance phase offset '11'"},
466
467	/* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
468	/* Task B: Basic settings and acquisition window definition */
469	{R_C0_B_TASK_HANDLING_CNTL,1,
470	 "Task B: Task handling control"},
471	{R_C1_B_X_PORT_FORMATS_AND_CONF,1,
472	 "Task B: X port formats and configuration"},
473	{R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
474	 "Task B: Input reference signal definition"},
475	{R_C3_B_I_PORT_FORMATS_AND_CONF,1,
476	 "Task B: I port formats and configuration"},
477	{R_C4_B_HORIZ_INPUT_WINDOW_START,2,
478	 "Task B: Horizontal input window start"},
479	{R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
480	 "Task B: Horizontal input window length"},
481	{R_C8_B_VERT_INPUT_WINDOW_START,2,
482	 "Task B: Vertical input window start"},
483	{R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
484	 "Task B: Vertical input window length"},
485	{R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
486	 "Task B: Horizontal output window length"},
487	{R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
488	 "Task B: Vertical output window length"},
489
490	/* Task B: FIR filtering and prescaling */
491	{R_D0_B_HORIZ_PRESCALING,1,
492	 "Task B: Horizontal prescaling"},
493	{R_D1_B_ACCUMULATION_LENGTH,1,
494	 "Task B: Accumulation length"},
495	{R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
496	 "Task B: Prescaler DC gain and FIR prefilter"},
497	/* 0xd3 - Reserved */
498	{R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
499	 "Task B: Luminance brightness control"},
500	{R_D5_B_LUMA_CONTRAST_CNTL,1,
501	 "Task B: Luminance contrast control"},
502	{R_D6_B_CHROMA_SATURATION_CNTL,1,
503	 "Task B: Chrominance saturation control"},
504	/* 0xd7 - Reserved */
505
506	/* Task B: Horizontal phase scaling */
507	{R_D8_B_HORIZ_LUMA_SCALING_INC,2,
508	 "Task B: Horizontal luminance scaling increment"},
509	{R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
510	 "Task B: Horizontal luminance phase offset"},
511	/* 0xdb - Reserved */
512	{R_DC_B_HORIZ_CHROMA_SCALING,2,
513	 "Task B: Horizontal chrominance scaling"},
514	{R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
515	 "Task B: Horizontal Phase Offset Chroma"},
516	/* 0xdf - Reserved */
517
518	/* Task B: Vertical scaling */
519	{R_E0_B_VERT_LUMA_SCALING_INC,2,
520	 "Task B: Vertical luminance scaling increment"},
521	{R_E2_B_VERT_CHROMA_SCALING_INC,2,
522	 "Task B: Vertical chrominance scaling increment"},
523	{R_E4_B_VERT_SCALING_MODE_CNTL,1,
524	 "Task B: Vertical scaling mode control"},
525	/* 0xe5-0xe7 - Reserved */
526	{R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
527	 "Task B: Vertical chrominance phase offset '00'"},
528	{R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
529	 "Task B: Vertical chrominance phase offset '01'"},
530	{R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
531	 "Task B: Vertical chrominance phase offset '10'"},
532	{R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
533	 "Task B: Vertical chrominance phase offset '11'"},
534	{R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
535	 "Task B: Vertical luminance phase offset '00'"},
536	{R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
537	 "Task B: Vertical luminance phase offset '01'"},
538	{R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
539	 "Task B: Vertical luminance phase offset '10'"},
540	{R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
541	 "Task B: Vertical luminance phase offset '11'"},
542
543	/* second PLL (PLL2) and Pulsegenerator Programming */
544	{ R_F0_LFCO_PER_LINE, 1,
545	  "LFCO's per line"},
546	{ R_F1_P_I_PARAM_SELECT,1,
547	  "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
548	{ R_F2_NOMINAL_PLL2_DTO,1,
549	 "Nominal PLL2 DTO"},
550	{R_F3_PLL_INCREMENT,1,
551	 "PLL2 Increment"},
552	{R_F4_PLL2_STATUS,1,
553	 "PLL2 Status"},
554	{R_F5_PULSGEN_LINE_LENGTH,1,
555	 "Pulsgen. line length"},
556	{R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
557	 "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
558	{R_F7_PULSE_A_POS_MSB,1,
559	 "Pulse A Position"},
560	{R_F8_PULSE_B_POS,2,
561	 "Pulse B Position"},
562	{R_FA_PULSE_C_POS,2,
563	 "Pulse C Position"},
564	/* 0xfc to 0xfe - Reserved */
565	{R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
566	 "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
567};
568#endif
569