1/* 2 * Driver for the Conexant CX25821 PCIe bridge 3 * 4 * Copyright (C) 2009 Conexant Systems Inc. 5 * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 24 25#include "cx25821-video.h" 26#include "cx25821-video-upstream.h" 27 28#include <linux/errno.h> 29#include <linux/kernel.h> 30#include <linux/init.h> 31#include <linux/module.h> 32#include <linux/slab.h> 33 34MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); 35MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); 36MODULE_LICENSE("GPL"); 37 38static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | 39 FLD_VID_SRC_OPC_ERR; 40 41int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev, 42 const struct sram_channel *ch, 43 unsigned int bpl, u32 risc) 44{ 45 unsigned int i, lines; 46 u32 cdt; 47 48 if (ch->cmds_start == 0) { 49 cx_write(ch->ptr1_reg, 0); 50 cx_write(ch->ptr2_reg, 0); 51 cx_write(ch->cnt2_reg, 0); 52 cx_write(ch->cnt1_reg, 0); 53 return 0; 54 } 55 56 bpl = (bpl + 7) & ~7; /* alignment */ 57 cdt = ch->cdt; 58 lines = ch->fifo_size / bpl; 59 60 if (lines > 4) 61 lines = 4; 62 63 BUG_ON(lines < 2); 64 65 /* write CDT */ 66 for (i = 0; i < lines; i++) { 67 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i); 68 cx_write(cdt + 16 * i + 4, 0); 69 cx_write(cdt + 16 * i + 8, 0); 70 cx_write(cdt + 16 * i + 12, 0); 71 } 72 73 /* write CMDS */ 74 cx_write(ch->cmds_start + 0, risc); 75 76 cx_write(ch->cmds_start + 4, 0); 77 cx_write(ch->cmds_start + 8, cdt); 78 cx_write(ch->cmds_start + 12, (lines * 16) >> 3); 79 cx_write(ch->cmds_start + 16, ch->ctrl_start); 80 81 cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW); 82 83 for (i = 24; i < 80; i += 4) 84 cx_write(ch->cmds_start + i, 0); 85 86 /* fill registers */ 87 cx_write(ch->ptr1_reg, ch->fifo_start); 88 cx_write(ch->ptr2_reg, cdt); 89 cx_write(ch->cnt2_reg, (lines * 16) >> 3); 90 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); 91 92 return 0; 93} 94 95static __le32 *cx25821_update_riscprogram(struct cx25821_channel *chan, 96 __le32 *rp, unsigned int offset, 97 unsigned int bpl, u32 sync_line, 98 unsigned int lines, int fifo_enable, 99 int field_type) 100{ 101 struct cx25821_video_out_data *out = chan->out; 102 unsigned int line, i; 103 int dist_betwn_starts = bpl * 2; 104 105 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 106 107 if (USE_RISC_NOOP_VIDEO) { 108 for (i = 0; i < NUM_NO_OPS; i++) 109 *(rp++) = cpu_to_le32(RISC_NOOP); 110 } 111 112 /* scan lines */ 113 for (line = 0; line < lines; line++) { 114 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); 115 *(rp++) = cpu_to_le32(out->_data_buf_phys_addr + offset); 116 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 117 118 if ((lines <= NTSC_FIELD_HEIGHT) 119 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(out->is_60hz)) { 120 offset += dist_betwn_starts; 121 } 122 } 123 124 return rp; 125} 126 127static __le32 *cx25821_risc_field_upstream(struct cx25821_channel *chan, __le32 *rp, 128 dma_addr_t databuf_phys_addr, 129 unsigned int offset, u32 sync_line, 130 unsigned int bpl, unsigned int lines, 131 int fifo_enable, int field_type) 132{ 133 struct cx25821_video_out_data *out = chan->out; 134 unsigned int line, i; 135 const struct sram_channel *sram_ch = chan->sram_channels; 136 int dist_betwn_starts = bpl * 2; 137 138 /* sync instruction */ 139 if (sync_line != NO_SYNC_LINE) 140 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 141 142 if (USE_RISC_NOOP_VIDEO) { 143 for (i = 0; i < NUM_NO_OPS; i++) 144 *(rp++) = cpu_to_le32(RISC_NOOP); 145 } 146 147 /* scan lines */ 148 for (line = 0; line < lines; line++) { 149 *(rp++) = cpu_to_le32(RISC_READ | RISC_SOL | RISC_EOL | bpl); 150 *(rp++) = cpu_to_le32(databuf_phys_addr + offset); 151 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ 152 153 if ((lines <= NTSC_FIELD_HEIGHT) 154 || (line < (NTSC_FIELD_HEIGHT - 1)) || !(out->is_60hz)) 155 /* to skip the other field line */ 156 offset += dist_betwn_starts; 157 158 /* check if we need to enable the FIFO after the first 4 lines 159 * For the upstream video channel, the risc engine will enable 160 * the FIFO. */ 161 if (fifo_enable && line == 3) { 162 *(rp++) = cpu_to_le32(RISC_WRITECR); 163 *(rp++) = cpu_to_le32(sram_ch->dma_ctl); 164 *(rp++) = cpu_to_le32(FLD_VID_FIFO_EN); 165 *(rp++) = cpu_to_le32(0x00000001); 166 } 167 } 168 169 return rp; 170} 171 172static int cx25821_risc_buffer_upstream(struct cx25821_channel *chan, 173 struct pci_dev *pci, 174 unsigned int top_offset, 175 unsigned int bpl, unsigned int lines) 176{ 177 struct cx25821_video_out_data *out = chan->out; 178 __le32 *rp; 179 int fifo_enable = 0; 180 /* get line count for single field */ 181 int singlefield_lines = lines >> 1; 182 int odd_num_lines = singlefield_lines; 183 int frame = 0; 184 int frame_size = 0; 185 int databuf_offset = 0; 186 int risc_program_size = 0; 187 int risc_flag = RISC_CNT_RESET; 188 unsigned int bottom_offset = bpl; 189 dma_addr_t risc_phys_jump_addr; 190 191 if (out->is_60hz) { 192 odd_num_lines = singlefield_lines + 1; 193 risc_program_size = FRAME1_VID_PROG_SIZE; 194 frame_size = (bpl == Y411_LINE_SZ) ? 195 FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422; 196 } else { 197 risc_program_size = PAL_VID_PROG_SIZE; 198 frame_size = (bpl == Y411_LINE_SZ) ? 199 FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 200 } 201 202 /* Virtual address of Risc buffer program */ 203 rp = out->_dma_virt_addr; 204 205 for (frame = 0; frame < NUM_FRAMES; frame++) { 206 databuf_offset = frame_size * frame; 207 208 if (UNSET != top_offset) { 209 fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE; 210 rp = cx25821_risc_field_upstream(chan, rp, 211 out->_data_buf_phys_addr + 212 databuf_offset, top_offset, 0, bpl, 213 odd_num_lines, fifo_enable, ODD_FIELD); 214 } 215 216 fifo_enable = FIFO_DISABLE; 217 218 /* Even Field */ 219 rp = cx25821_risc_field_upstream(chan, rp, 220 out->_data_buf_phys_addr + 221 databuf_offset, bottom_offset, 222 0x200, bpl, singlefield_lines, 223 fifo_enable, EVEN_FIELD); 224 225 if (frame == 0) { 226 risc_flag = RISC_CNT_RESET; 227 risc_phys_jump_addr = out->_dma_phys_start_addr + 228 risc_program_size; 229 } else { 230 risc_phys_jump_addr = out->_dma_phys_start_addr; 231 risc_flag = RISC_CNT_INC; 232 } 233 234 /* Loop to 2ndFrameRISC or to Start of Risc 235 * program & generate IRQ 236 */ 237 *(rp++) = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | risc_flag); 238 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 239 *(rp++) = cpu_to_le32(0); 240 } 241 242 return 0; 243} 244 245void cx25821_stop_upstream_video(struct cx25821_channel *chan) 246{ 247 struct cx25821_video_out_data *out = chan->out; 248 struct cx25821_dev *dev = chan->dev; 249 const struct sram_channel *sram_ch = chan->sram_channels; 250 u32 tmp = 0; 251 252 if (!out->_is_running) { 253 pr_info("No video file is currently running so return!\n"); 254 return; 255 } 256 257 /* Set the interrupt mask register, disable irq. */ 258 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) & ~(1 << sram_ch->irq_bit)); 259 260 /* Disable RISC interrupts */ 261 tmp = cx_read(sram_ch->int_msk); 262 cx_write(sram_ch->int_msk, tmp & ~_intr_msk); 263 264 /* Turn OFF risc and fifo enable */ 265 tmp = cx_read(sram_ch->dma_ctl); 266 cx_write(sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN)); 267 268 free_irq(dev->pci->irq, chan); 269 270 /* Clear data buffer memory */ 271 if (out->_data_buf_virt_addr) 272 memset(out->_data_buf_virt_addr, 0, out->_data_buf_size); 273 274 out->_is_running = 0; 275 out->_is_first_frame = 0; 276 out->_frame_count = 0; 277 out->_file_status = END_OF_FILE; 278 279 tmp = cx_read(VID_CH_MODE_SEL); 280 cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); 281} 282 283void cx25821_free_mem_upstream(struct cx25821_channel *chan) 284{ 285 struct cx25821_video_out_data *out = chan->out; 286 struct cx25821_dev *dev = chan->dev; 287 288 if (out->_is_running) 289 cx25821_stop_upstream_video(chan); 290 291 if (out->_dma_virt_addr) { 292 pci_free_consistent(dev->pci, out->_risc_size, 293 out->_dma_virt_addr, out->_dma_phys_addr); 294 out->_dma_virt_addr = NULL; 295 } 296 297 if (out->_data_buf_virt_addr) { 298 pci_free_consistent(dev->pci, out->_data_buf_size, 299 out->_data_buf_virt_addr, 300 out->_data_buf_phys_addr); 301 out->_data_buf_virt_addr = NULL; 302 } 303} 304 305int cx25821_write_frame(struct cx25821_channel *chan, 306 const char __user *data, size_t count) 307{ 308 struct cx25821_video_out_data *out = chan->out; 309 int line_size = (out->_pixel_format == PIXEL_FRMT_411) ? 310 Y411_LINE_SZ : Y422_LINE_SZ; 311 int frame_size = 0; 312 int frame_offset = 0; 313 int curpos = out->curpos; 314 315 if (out->is_60hz) 316 frame_size = (line_size == Y411_LINE_SZ) ? 317 FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422; 318 else 319 frame_size = (line_size == Y411_LINE_SZ) ? 320 FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422; 321 322 if (curpos == 0) { 323 out->cur_frame_index = out->_frame_index; 324 if (wait_event_interruptible(out->waitq, out->cur_frame_index != out->_frame_index)) 325 return -EINTR; 326 out->cur_frame_index = out->_frame_index; 327 } 328 329 frame_offset = out->cur_frame_index ? frame_size : 0; 330 331 if (frame_size - curpos < count) 332 count = frame_size - curpos; 333 if (copy_from_user((__force char *)out->_data_buf_virt_addr + frame_offset + curpos, 334 data, count)) 335 return -EFAULT; 336 curpos += count; 337 if (curpos == frame_size) { 338 out->_frame_count++; 339 curpos = 0; 340 } 341 out->curpos = curpos; 342 343 return count; 344} 345 346static int cx25821_upstream_buffer_prepare(struct cx25821_channel *chan, 347 const struct sram_channel *sram_ch, 348 int bpl) 349{ 350 struct cx25821_video_out_data *out = chan->out; 351 struct cx25821_dev *dev = chan->dev; 352 int ret = 0; 353 dma_addr_t dma_addr; 354 dma_addr_t data_dma_addr; 355 356 if (out->_dma_virt_addr != NULL) 357 pci_free_consistent(dev->pci, out->upstream_riscbuf_size, 358 out->_dma_virt_addr, out->_dma_phys_addr); 359 360 out->_dma_virt_addr = pci_alloc_consistent(dev->pci, 361 out->upstream_riscbuf_size, &dma_addr); 362 out->_dma_virt_start_addr = out->_dma_virt_addr; 363 out->_dma_phys_start_addr = dma_addr; 364 out->_dma_phys_addr = dma_addr; 365 out->_risc_size = out->upstream_riscbuf_size; 366 367 if (!out->_dma_virt_addr) { 368 pr_err("FAILED to allocate memory for Risc buffer! Returning\n"); 369 return -ENOMEM; 370 } 371 372 /* Clear memory at address */ 373 memset(out->_dma_virt_addr, 0, out->_risc_size); 374 375 if (out->_data_buf_virt_addr != NULL) 376 pci_free_consistent(dev->pci, out->upstream_databuf_size, 377 out->_data_buf_virt_addr, 378 out->_data_buf_phys_addr); 379 /* For Video Data buffer allocation */ 380 out->_data_buf_virt_addr = pci_alloc_consistent(dev->pci, 381 out->upstream_databuf_size, &data_dma_addr); 382 out->_data_buf_phys_addr = data_dma_addr; 383 out->_data_buf_size = out->upstream_databuf_size; 384 385 if (!out->_data_buf_virt_addr) { 386 pr_err("FAILED to allocate memory for data buffer! Returning\n"); 387 return -ENOMEM; 388 } 389 390 /* Clear memory at address */ 391 memset(out->_data_buf_virt_addr, 0, out->_data_buf_size); 392 393 /* Create RISC programs */ 394 ret = cx25821_risc_buffer_upstream(chan, dev->pci, 0, bpl, 395 out->_lines_count); 396 if (ret < 0) { 397 pr_info("Failed creating Video Upstream Risc programs!\n"); 398 goto error; 399 } 400 401 return 0; 402 403error: 404 return ret; 405} 406 407static int cx25821_video_upstream_irq(struct cx25821_channel *chan, u32 status) 408{ 409 struct cx25821_video_out_data *out = chan->out; 410 struct cx25821_dev *dev = chan->dev; 411 u32 int_msk_tmp; 412 const struct sram_channel *channel = chan->sram_channels; 413 int singlefield_lines = NTSC_FIELD_HEIGHT; 414 int line_size_in_bytes = Y422_LINE_SZ; 415 int odd_risc_prog_size = 0; 416 dma_addr_t risc_phys_jump_addr; 417 __le32 *rp; 418 419 if (status & FLD_VID_SRC_RISC1) { 420 /* We should only process one program per call */ 421 u32 prog_cnt = cx_read(channel->gpcnt); 422 423 /* Since we've identified our IRQ, clear our bits from the 424 * interrupt mask and interrupt status registers */ 425 int_msk_tmp = cx_read(channel->int_msk); 426 cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk); 427 cx_write(channel->int_stat, _intr_msk); 428 429 wake_up(&out->waitq); 430 431 spin_lock(&dev->slock); 432 433 out->_frame_index = prog_cnt; 434 435 if (out->_is_first_frame) { 436 out->_is_first_frame = 0; 437 438 if (out->is_60hz) { 439 singlefield_lines += 1; 440 odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE; 441 } else { 442 singlefield_lines = PAL_FIELD_HEIGHT; 443 odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE; 444 } 445 446 if (out->_dma_virt_start_addr != NULL) { 447 line_size_in_bytes = 448 (out->_pixel_format == 449 PIXEL_FRMT_411) ? Y411_LINE_SZ : 450 Y422_LINE_SZ; 451 risc_phys_jump_addr = 452 out->_dma_phys_start_addr + 453 odd_risc_prog_size; 454 455 rp = cx25821_update_riscprogram(chan, 456 out->_dma_virt_start_addr, TOP_OFFSET, 457 line_size_in_bytes, 0x0, 458 singlefield_lines, FIFO_DISABLE, 459 ODD_FIELD); 460 461 /* Jump to Even Risc program of 1st Frame */ 462 *(rp++) = cpu_to_le32(RISC_JUMP); 463 *(rp++) = cpu_to_le32(risc_phys_jump_addr); 464 *(rp++) = cpu_to_le32(0); 465 } 466 } 467 468 spin_unlock(&dev->slock); 469 } else { 470 if (status & FLD_VID_SRC_UF) 471 pr_err("%s(): Video Received Underflow Error Interrupt!\n", 472 __func__); 473 474 if (status & FLD_VID_SRC_SYNC) 475 pr_err("%s(): Video Received Sync Error Interrupt!\n", 476 __func__); 477 478 if (status & FLD_VID_SRC_OPC_ERR) 479 pr_err("%s(): Video Received OpCode Error Interrupt!\n", 480 __func__); 481 } 482 483 if (out->_file_status == END_OF_FILE) { 484 pr_err("EOF Channel 1 Framecount = %d\n", out->_frame_count); 485 return -1; 486 } 487 /* ElSE, set the interrupt mask register, re-enable irq. */ 488 int_msk_tmp = cx_read(channel->int_msk); 489 cx_write(channel->int_msk, int_msk_tmp |= _intr_msk); 490 491 return 0; 492} 493 494static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id) 495{ 496 struct cx25821_channel *chan = dev_id; 497 struct cx25821_dev *dev = chan->dev; 498 u32 vid_status; 499 int handled = 0; 500 const struct sram_channel *sram_ch; 501 502 if (!dev) 503 return -1; 504 505 sram_ch = chan->sram_channels; 506 507 vid_status = cx_read(sram_ch->int_stat); 508 509 /* Only deal with our interrupt */ 510 if (vid_status) 511 handled = cx25821_video_upstream_irq(chan, vid_status); 512 513 return IRQ_RETVAL(handled); 514} 515 516static void cx25821_set_pixelengine(struct cx25821_channel *chan, 517 const struct sram_channel *ch, 518 int pix_format) 519{ 520 struct cx25821_video_out_data *out = chan->out; 521 struct cx25821_dev *dev = chan->dev; 522 int width = WIDTH_D1; 523 int height = out->_lines_count; 524 int num_lines, odd_num_lines; 525 u32 value; 526 int vip_mode = OUTPUT_FRMT_656; 527 528 value = ((pix_format & 0x3) << 12) | (vip_mode & 0x7); 529 value &= 0xFFFFFFEF; 530 value |= out->is_60hz ? 0 : 0x10; 531 cx_write(ch->vid_fmt_ctl, value); 532 533 /* set number of active pixels in each line. 534 * Default is 720 pixels in both NTSC and PAL format */ 535 cx_write(ch->vid_active_ctl1, width); 536 537 num_lines = (height / 2) & 0x3FF; 538 odd_num_lines = num_lines; 539 540 if (out->is_60hz) 541 odd_num_lines += 1; 542 543 value = (num_lines << 16) | odd_num_lines; 544 545 /* set number of active lines in field 0 (top) and field 1 (bottom) */ 546 cx_write(ch->vid_active_ctl2, value); 547 548 cx_write(ch->vid_cdt_size, VID_CDT_SIZE >> 3); 549} 550 551static int cx25821_start_video_dma_upstream(struct cx25821_channel *chan, 552 const struct sram_channel *sram_ch) 553{ 554 struct cx25821_video_out_data *out = chan->out; 555 struct cx25821_dev *dev = chan->dev; 556 u32 tmp = 0; 557 int err = 0; 558 559 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for 560 * channel A-C 561 */ 562 tmp = cx_read(VID_CH_MODE_SEL); 563 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); 564 565 /* Set the physical start address of the RISC program in the initial 566 * program counter(IPC) member of the cmds. 567 */ 568 cx_write(sram_ch->cmds_start + 0, out->_dma_phys_addr); 569 /* Risc IPC High 64 bits 63-32 */ 570 cx_write(sram_ch->cmds_start + 4, 0); 571 572 /* reset counter */ 573 cx_write(sram_ch->gpcnt_ctl, 3); 574 575 /* Clear our bits from the interrupt status register. */ 576 cx_write(sram_ch->int_stat, _intr_msk); 577 578 /* Set the interrupt mask register, enable irq. */ 579 cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit)); 580 tmp = cx_read(sram_ch->int_msk); 581 cx_write(sram_ch->int_msk, tmp |= _intr_msk); 582 583 err = request_irq(dev->pci->irq, cx25821_upstream_irq, 584 IRQF_SHARED, dev->name, chan); 585 if (err < 0) { 586 pr_err("%s: can't get upstream IRQ %d\n", 587 dev->name, dev->pci->irq); 588 goto fail_irq; 589 } 590 591 /* Start the DMA engine */ 592 tmp = cx_read(sram_ch->dma_ctl); 593 cx_set(sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN); 594 595 out->_is_running = 1; 596 out->_is_first_frame = 1; 597 598 return 0; 599 600fail_irq: 601 cx25821_dev_unregister(dev); 602 return err; 603} 604 605int cx25821_vidupstream_init(struct cx25821_channel *chan, 606 int pixel_format) 607{ 608 struct cx25821_video_out_data *out = chan->out; 609 struct cx25821_dev *dev = chan->dev; 610 const struct sram_channel *sram_ch; 611 u32 tmp; 612 int err = 0; 613 int data_frame_size = 0; 614 int risc_buffer_size = 0; 615 616 if (out->_is_running) { 617 pr_info("Video Channel is still running so return!\n"); 618 return 0; 619 } 620 621 sram_ch = chan->sram_channels; 622 623 out->is_60hz = dev->tvnorm & V4L2_STD_525_60; 624 625 /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for 626 * channel A-C 627 */ 628 tmp = cx_read(VID_CH_MODE_SEL); 629 cx_write(VID_CH_MODE_SEL, tmp | 0x1B0001FF); 630 631 out->_is_running = 0; 632 out->_frame_count = 0; 633 out->_file_status = RESET_STATUS; 634 out->_lines_count = out->is_60hz ? 480 : 576; 635 out->_pixel_format = pixel_format; 636 out->_line_size = (out->_pixel_format == PIXEL_FRMT_422) ? 637 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; 638 data_frame_size = out->is_60hz ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ; 639 risc_buffer_size = out->is_60hz ? 640 NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE; 641 642 out->_is_running = 0; 643 out->_frame_count = 0; 644 out->_file_status = RESET_STATUS; 645 out->_lines_count = out->is_60hz ? 480 : 576; 646 out->_pixel_format = pixel_format; 647 out->_line_size = (out->_pixel_format == PIXEL_FRMT_422) ? 648 (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2; 649 out->curpos = 0; 650 init_waitqueue_head(&out->waitq); 651 652 err = cx25821_sram_channel_setup_upstream(dev, sram_ch, 653 out->_line_size, 0); 654 655 /* setup fifo + format */ 656 cx25821_set_pixelengine(chan, sram_ch, out->_pixel_format); 657 658 out->upstream_riscbuf_size = risc_buffer_size * 2; 659 out->upstream_databuf_size = data_frame_size * 2; 660 661 /* Allocating buffers and prepare RISC program */ 662 err = cx25821_upstream_buffer_prepare(chan, sram_ch, out->_line_size); 663 if (err < 0) { 664 pr_err("%s: Failed to set up Video upstream buffers!\n", 665 dev->name); 666 goto error; 667 } 668 669 cx25821_start_video_dma_upstream(chan, sram_ch); 670 671 return 0; 672 673error: 674 cx25821_dev_unregister(dev); 675 676 return err; 677} 678