1/* 2 * 3 * device driver for Conexant 2388x based TV cards 4 * driver core 5 * 6 * (c) 2003 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs] 7 * 8 * (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org> 9 * - Multituner support 10 * - video_ioctl2 conversion 11 * - PAL/M fixes 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 26 */ 27 28#include <linux/init.h> 29#include <linux/list.h> 30#include <linux/module.h> 31#include <linux/kernel.h> 32#include <linux/slab.h> 33#include <linux/kmod.h> 34#include <linux/sound.h> 35#include <linux/interrupt.h> 36#include <linux/pci.h> 37#include <linux/delay.h> 38#include <linux/videodev2.h> 39#include <linux/mutex.h> 40 41#include "cx88.h" 42#include <media/v4l2-common.h> 43#include <media/v4l2-ioctl.h> 44 45MODULE_DESCRIPTION("v4l2 driver module for cx2388x based TV cards"); 46MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]"); 47MODULE_LICENSE("GPL"); 48 49/* ------------------------------------------------------------------ */ 50 51unsigned int cx88_core_debug; 52module_param_named(core_debug, cx88_core_debug, int, 0644); 53MODULE_PARM_DESC(core_debug, "enable debug messages [core]"); 54 55static unsigned int nicam; 56module_param(nicam,int,0644); 57MODULE_PARM_DESC(nicam,"tv audio is nicam"); 58 59static unsigned int nocomb; 60module_param(nocomb,int,0644); 61MODULE_PARM_DESC(nocomb,"disable comb filter"); 62 63#define dprintk(level,fmt, arg...) do { \ 64 if (cx88_core_debug >= level) \ 65 printk(KERN_DEBUG "%s: " fmt, core->name , ## arg); \ 66 } while(0) 67 68static unsigned int cx88_devcount; 69static LIST_HEAD(cx88_devlist); 70static DEFINE_MUTEX(devlist); 71 72#define NO_SYNC_LINE (-1U) 73 74/* @lpi: lines per IRQ, or 0 to not generate irqs. Note: IRQ to be 75 generated _after_ lpi lines are transferred. */ 76static __le32* cx88_risc_field(__le32 *rp, struct scatterlist *sglist, 77 unsigned int offset, u32 sync_line, 78 unsigned int bpl, unsigned int padding, 79 unsigned int lines, unsigned int lpi, bool jump) 80{ 81 struct scatterlist *sg; 82 unsigned int line,todo,sol; 83 84 if (jump) { 85 (*rp++) = cpu_to_le32(RISC_JUMP); 86 (*rp++) = 0; 87 } 88 89 /* sync instruction */ 90 if (sync_line != NO_SYNC_LINE) 91 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line); 92 93 /* scan lines */ 94 sg = sglist; 95 for (line = 0; line < lines; line++) { 96 while (offset && offset >= sg_dma_len(sg)) { 97 offset -= sg_dma_len(sg); 98 sg = sg_next(sg); 99 } 100 if (lpi && line>0 && !(line % lpi)) 101 sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC; 102 else 103 sol = RISC_SOL; 104 if (bpl <= sg_dma_len(sg)-offset) { 105 /* fits into current chunk */ 106 *(rp++)=cpu_to_le32(RISC_WRITE|sol|RISC_EOL|bpl); 107 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); 108 offset+=bpl; 109 } else { 110 /* scanline needs to be split */ 111 todo = bpl; 112 *(rp++)=cpu_to_le32(RISC_WRITE|sol| 113 (sg_dma_len(sg)-offset)); 114 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset); 115 todo -= (sg_dma_len(sg)-offset); 116 offset = 0; 117 sg = sg_next(sg); 118 while (todo > sg_dma_len(sg)) { 119 *(rp++)=cpu_to_le32(RISC_WRITE| 120 sg_dma_len(sg)); 121 *(rp++)=cpu_to_le32(sg_dma_address(sg)); 122 todo -= sg_dma_len(sg); 123 sg = sg_next(sg); 124 } 125 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo); 126 *(rp++)=cpu_to_le32(sg_dma_address(sg)); 127 offset += todo; 128 } 129 offset += padding; 130 } 131 132 return rp; 133} 134 135int cx88_risc_buffer(struct pci_dev *pci, struct cx88_riscmem *risc, 136 struct scatterlist *sglist, 137 unsigned int top_offset, unsigned int bottom_offset, 138 unsigned int bpl, unsigned int padding, unsigned int lines) 139{ 140 u32 instructions,fields; 141 __le32 *rp; 142 143 fields = 0; 144 if (UNSET != top_offset) 145 fields++; 146 if (UNSET != bottom_offset) 147 fields++; 148 149 /* estimate risc mem: worst case is one write per page border + 150 one write per scan line + syncs + jump (all 2 dwords). Padding 151 can cause next bpl to start close to a page border. First DMA 152 region may be smaller than PAGE_SIZE */ 153 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines); 154 instructions += 4; 155 risc->size = instructions * 8; 156 risc->dma = 0; 157 risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma); 158 if (NULL == risc->cpu) 159 return -ENOMEM; 160 161 /* write risc instructions */ 162 rp = risc->cpu; 163 if (UNSET != top_offset) 164 rp = cx88_risc_field(rp, sglist, top_offset, 0, 165 bpl, padding, lines, 0, true); 166 if (UNSET != bottom_offset) 167 rp = cx88_risc_field(rp, sglist, bottom_offset, 0x200, 168 bpl, padding, lines, 0, top_offset == UNSET); 169 170 /* save pointer to jmp instruction address */ 171 risc->jmp = rp; 172 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size); 173 return 0; 174} 175 176int cx88_risc_databuffer(struct pci_dev *pci, struct cx88_riscmem *risc, 177 struct scatterlist *sglist, unsigned int bpl, 178 unsigned int lines, unsigned int lpi) 179{ 180 u32 instructions; 181 __le32 *rp; 182 183 /* estimate risc mem: worst case is one write per page border + 184 one write per scan line + syncs + jump (all 2 dwords). Here 185 there is no padding and no sync. First DMA region may be smaller 186 than PAGE_SIZE */ 187 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines; 188 instructions += 3; 189 risc->size = instructions * 8; 190 risc->dma = 0; 191 risc->cpu = pci_zalloc_consistent(pci, risc->size, &risc->dma); 192 if (NULL == risc->cpu) 193 return -ENOMEM; 194 195 /* write risc instructions */ 196 rp = risc->cpu; 197 rp = cx88_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines, lpi, !lpi); 198 199 /* save pointer to jmp instruction address */ 200 risc->jmp = rp; 201 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size); 202 return 0; 203} 204 205/* ------------------------------------------------------------------ */ 206/* our SRAM memory layout */ 207 208/* we are going to put all thr risc programs into host memory, so we 209 * can use the whole SDRAM for the DMA fifos. To simplify things, we 210 * use a static memory layout. That surely will waste memory in case 211 * we don't use all DMA channels at the same time (which will be the 212 * case most of the time). But that still gives us enough FIFO space 213 * to be able to deal with insane long pci latencies ... 214 * 215 * FIFO space allocations: 216 * channel 21 (y video) - 10.0k 217 * channel 22 (u video) - 2.0k 218 * channel 23 (v video) - 2.0k 219 * channel 24 (vbi) - 4.0k 220 * channels 25+26 (audio) - 4.0k 221 * channel 28 (mpeg) - 4.0k 222 * channel 27 (audio rds)- 3.0k 223 * TOTAL = 29.0k 224 * 225 * Every channel has 160 bytes control data (64 bytes instruction 226 * queue and 6 CDT entries), which is close to 2k total. 227 * 228 * Address layout: 229 * 0x0000 - 0x03ff CMDs / reserved 230 * 0x0400 - 0x0bff instruction queues + CDs 231 * 0x0c00 - FIFOs 232 */ 233 234const struct sram_channel cx88_sram_channels[] = { 235 [SRAM_CH21] = { 236 .name = "video y / packed", 237 .cmds_start = 0x180040, 238 .ctrl_start = 0x180400, 239 .cdt = 0x180400 + 64, 240 .fifo_start = 0x180c00, 241 .fifo_size = 0x002800, 242 .ptr1_reg = MO_DMA21_PTR1, 243 .ptr2_reg = MO_DMA21_PTR2, 244 .cnt1_reg = MO_DMA21_CNT1, 245 .cnt2_reg = MO_DMA21_CNT2, 246 }, 247 [SRAM_CH22] = { 248 .name = "video u", 249 .cmds_start = 0x180080, 250 .ctrl_start = 0x1804a0, 251 .cdt = 0x1804a0 + 64, 252 .fifo_start = 0x183400, 253 .fifo_size = 0x000800, 254 .ptr1_reg = MO_DMA22_PTR1, 255 .ptr2_reg = MO_DMA22_PTR2, 256 .cnt1_reg = MO_DMA22_CNT1, 257 .cnt2_reg = MO_DMA22_CNT2, 258 }, 259 [SRAM_CH23] = { 260 .name = "video v", 261 .cmds_start = 0x1800c0, 262 .ctrl_start = 0x180540, 263 .cdt = 0x180540 + 64, 264 .fifo_start = 0x183c00, 265 .fifo_size = 0x000800, 266 .ptr1_reg = MO_DMA23_PTR1, 267 .ptr2_reg = MO_DMA23_PTR2, 268 .cnt1_reg = MO_DMA23_CNT1, 269 .cnt2_reg = MO_DMA23_CNT2, 270 }, 271 [SRAM_CH24] = { 272 .name = "vbi", 273 .cmds_start = 0x180100, 274 .ctrl_start = 0x1805e0, 275 .cdt = 0x1805e0 + 64, 276 .fifo_start = 0x184400, 277 .fifo_size = 0x001000, 278 .ptr1_reg = MO_DMA24_PTR1, 279 .ptr2_reg = MO_DMA24_PTR2, 280 .cnt1_reg = MO_DMA24_CNT1, 281 .cnt2_reg = MO_DMA24_CNT2, 282 }, 283 [SRAM_CH25] = { 284 .name = "audio from", 285 .cmds_start = 0x180140, 286 .ctrl_start = 0x180680, 287 .cdt = 0x180680 + 64, 288 .fifo_start = 0x185400, 289 .fifo_size = 0x001000, 290 .ptr1_reg = MO_DMA25_PTR1, 291 .ptr2_reg = MO_DMA25_PTR2, 292 .cnt1_reg = MO_DMA25_CNT1, 293 .cnt2_reg = MO_DMA25_CNT2, 294 }, 295 [SRAM_CH26] = { 296 .name = "audio to", 297 .cmds_start = 0x180180, 298 .ctrl_start = 0x180720, 299 .cdt = 0x180680 + 64, /* same as audio IN */ 300 .fifo_start = 0x185400, /* same as audio IN */ 301 .fifo_size = 0x001000, /* same as audio IN */ 302 .ptr1_reg = MO_DMA26_PTR1, 303 .ptr2_reg = MO_DMA26_PTR2, 304 .cnt1_reg = MO_DMA26_CNT1, 305 .cnt2_reg = MO_DMA26_CNT2, 306 }, 307 [SRAM_CH28] = { 308 .name = "mpeg", 309 .cmds_start = 0x180200, 310 .ctrl_start = 0x1807C0, 311 .cdt = 0x1807C0 + 64, 312 .fifo_start = 0x186400, 313 .fifo_size = 0x001000, 314 .ptr1_reg = MO_DMA28_PTR1, 315 .ptr2_reg = MO_DMA28_PTR2, 316 .cnt1_reg = MO_DMA28_CNT1, 317 .cnt2_reg = MO_DMA28_CNT2, 318 }, 319 [SRAM_CH27] = { 320 .name = "audio rds", 321 .cmds_start = 0x1801C0, 322 .ctrl_start = 0x180860, 323 .cdt = 0x180860 + 64, 324 .fifo_start = 0x187400, 325 .fifo_size = 0x000C00, 326 .ptr1_reg = MO_DMA27_PTR1, 327 .ptr2_reg = MO_DMA27_PTR2, 328 .cnt1_reg = MO_DMA27_CNT1, 329 .cnt2_reg = MO_DMA27_CNT2, 330 }, 331}; 332 333int cx88_sram_channel_setup(struct cx88_core *core, 334 const struct sram_channel *ch, 335 unsigned int bpl, u32 risc) 336{ 337 unsigned int i,lines; 338 u32 cdt; 339 340 bpl = (bpl + 7) & ~7; /* alignment */ 341 cdt = ch->cdt; 342 lines = ch->fifo_size / bpl; 343 if (lines > 6) 344 lines = 6; 345 BUG_ON(lines < 2); 346 347 /* write CDT */ 348 for (i = 0; i < lines; i++) 349 cx_write(cdt + 16*i, ch->fifo_start + bpl*i); 350 351 /* write CMDS */ 352 cx_write(ch->cmds_start + 0, risc); 353 cx_write(ch->cmds_start + 4, cdt); 354 cx_write(ch->cmds_start + 8, (lines*16) >> 3); 355 cx_write(ch->cmds_start + 12, ch->ctrl_start); 356 cx_write(ch->cmds_start + 16, 64 >> 2); 357 for (i = 20; i < 64; i += 4) 358 cx_write(ch->cmds_start + i, 0); 359 360 /* fill registers */ 361 cx_write(ch->ptr1_reg, ch->fifo_start); 362 cx_write(ch->ptr2_reg, cdt); 363 cx_write(ch->cnt1_reg, (bpl >> 3) -1); 364 cx_write(ch->cnt2_reg, (lines*16) >> 3); 365 366 dprintk(2,"sram setup %s: bpl=%d lines=%d\n", ch->name, bpl, lines); 367 return 0; 368} 369 370/* ------------------------------------------------------------------ */ 371/* debug helper code */ 372 373static int cx88_risc_decode(u32 risc) 374{ 375 static const char * const instr[16] = { 376 [ RISC_SYNC >> 28 ] = "sync", 377 [ RISC_WRITE >> 28 ] = "write", 378 [ RISC_WRITEC >> 28 ] = "writec", 379 [ RISC_READ >> 28 ] = "read", 380 [ RISC_READC >> 28 ] = "readc", 381 [ RISC_JUMP >> 28 ] = "jump", 382 [ RISC_SKIP >> 28 ] = "skip", 383 [ RISC_WRITERM >> 28 ] = "writerm", 384 [ RISC_WRITECM >> 28 ] = "writecm", 385 [ RISC_WRITECR >> 28 ] = "writecr", 386 }; 387 static int const incr[16] = { 388 [ RISC_WRITE >> 28 ] = 2, 389 [ RISC_JUMP >> 28 ] = 2, 390 [ RISC_WRITERM >> 28 ] = 3, 391 [ RISC_WRITECM >> 28 ] = 3, 392 [ RISC_WRITECR >> 28 ] = 4, 393 }; 394 static const char * const bits[] = { 395 "12", "13", "14", "resync", 396 "cnt0", "cnt1", "18", "19", 397 "20", "21", "22", "23", 398 "irq1", "irq2", "eol", "sol", 399 }; 400 int i; 401 402 printk("0x%08x [ %s", risc, 403 instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); 404 for (i = ARRAY_SIZE(bits)-1; i >= 0; i--) 405 if (risc & (1 << (i + 12))) 406 printk(" %s",bits[i]); 407 printk(" count=%d ]\n", risc & 0xfff); 408 return incr[risc >> 28] ? incr[risc >> 28] : 1; 409} 410 411 412void cx88_sram_channel_dump(struct cx88_core *core, 413 const struct sram_channel *ch) 414{ 415 static const char * const name[] = { 416 "initial risc", 417 "cdt base", 418 "cdt size", 419 "iq base", 420 "iq size", 421 "risc pc", 422 "iq wr ptr", 423 "iq rd ptr", 424 "cdt current", 425 "pci target", 426 "line / byte", 427 }; 428 u32 risc; 429 unsigned int i,j,n; 430 431 printk("%s: %s - dma channel status dump\n", 432 core->name,ch->name); 433 for (i = 0; i < ARRAY_SIZE(name); i++) 434 printk("%s: cmds: %-12s: 0x%08x\n", 435 core->name,name[i], 436 cx_read(ch->cmds_start + 4*i)); 437 for (n = 1, i = 0; i < 4; i++) { 438 risc = cx_read(ch->cmds_start + 4 * (i+11)); 439 printk("%s: risc%d: ", core->name, i); 440 if (--n) 441 printk("0x%08x [ arg #%d ]\n", risc, n); 442 else 443 n = cx88_risc_decode(risc); 444 } 445 for (i = 0; i < 16; i += n) { 446 risc = cx_read(ch->ctrl_start + 4 * i); 447 printk("%s: iq %x: ", core->name, i); 448 n = cx88_risc_decode(risc); 449 for (j = 1; j < n; j++) { 450 risc = cx_read(ch->ctrl_start + 4 * (i+j)); 451 printk("%s: iq %x: 0x%08x [ arg #%d ]\n", 452 core->name, i+j, risc, j); 453 } 454 } 455 456 printk("%s: fifo: 0x%08x -> 0x%x\n", 457 core->name, ch->fifo_start, ch->fifo_start+ch->fifo_size); 458 printk("%s: ctrl: 0x%08x -> 0x%x\n", 459 core->name, ch->ctrl_start, ch->ctrl_start+6*16); 460 printk("%s: ptr1_reg: 0x%08x\n", 461 core->name,cx_read(ch->ptr1_reg)); 462 printk("%s: ptr2_reg: 0x%08x\n", 463 core->name,cx_read(ch->ptr2_reg)); 464 printk("%s: cnt1_reg: 0x%08x\n", 465 core->name,cx_read(ch->cnt1_reg)); 466 printk("%s: cnt2_reg: 0x%08x\n", 467 core->name,cx_read(ch->cnt2_reg)); 468} 469 470static const char *cx88_pci_irqs[32] = { 471 "vid", "aud", "ts", "vip", "hst", "5", "6", "tm1", 472 "src_dma", "dst_dma", "risc_rd_err", "risc_wr_err", 473 "brdg_err", "src_dma_err", "dst_dma_err", "ipb_dma_err", 474 "i2c", "i2c_rack", "ir_smp", "gpio0", "gpio1" 475}; 476 477void cx88_print_irqbits(const char *name, const char *tag, const char *strings[], 478 int len, u32 bits, u32 mask) 479{ 480 unsigned int i; 481 482 printk(KERN_DEBUG "%s: %s [0x%x]", name, tag, bits); 483 for (i = 0; i < len; i++) { 484 if (!(bits & (1 << i))) 485 continue; 486 if (strings[i]) 487 printk(" %s", strings[i]); 488 else 489 printk(" %d", i); 490 if (!(mask & (1 << i))) 491 continue; 492 printk("*"); 493 } 494 printk("\n"); 495} 496 497/* ------------------------------------------------------------------ */ 498 499int cx88_core_irq(struct cx88_core *core, u32 status) 500{ 501 int handled = 0; 502 503 if (status & PCI_INT_IR_SMPINT) { 504 cx88_ir_irq(core); 505 handled++; 506 } 507 if (!handled) 508 cx88_print_irqbits(core->name, "irq pci", 509 cx88_pci_irqs, ARRAY_SIZE(cx88_pci_irqs), 510 status, core->pci_irqmask); 511 return handled; 512} 513 514void cx88_wakeup(struct cx88_core *core, 515 struct cx88_dmaqueue *q, u32 count) 516{ 517 struct cx88_buffer *buf; 518 519 buf = list_entry(q->active.next, 520 struct cx88_buffer, list); 521 v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); 522 list_del(&buf->list); 523 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); 524} 525 526void cx88_shutdown(struct cx88_core *core) 527{ 528 /* disable RISC controller + IRQs */ 529 cx_write(MO_DEV_CNTRL2, 0); 530 531 /* stop dma transfers */ 532 cx_write(MO_VID_DMACNTRL, 0x0); 533 cx_write(MO_AUD_DMACNTRL, 0x0); 534 cx_write(MO_TS_DMACNTRL, 0x0); 535 cx_write(MO_VIP_DMACNTRL, 0x0); 536 cx_write(MO_GPHST_DMACNTRL, 0x0); 537 538 /* stop interrupts */ 539 cx_write(MO_PCI_INTMSK, 0x0); 540 cx_write(MO_VID_INTMSK, 0x0); 541 cx_write(MO_AUD_INTMSK, 0x0); 542 cx_write(MO_TS_INTMSK, 0x0); 543 cx_write(MO_VIP_INTMSK, 0x0); 544 cx_write(MO_GPHST_INTMSK, 0x0); 545 546 /* stop capturing */ 547 cx_write(VID_CAPTURE_CONTROL, 0); 548} 549 550int cx88_reset(struct cx88_core *core) 551{ 552 dprintk(1,"%s\n",__func__); 553 cx88_shutdown(core); 554 555 /* clear irq status */ 556 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int 557 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int 558 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int 559 560 /* wait a bit */ 561 msleep(100); 562 563 /* init sram */ 564 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], 720*4, 0); 565 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH22], 128, 0); 566 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH23], 128, 0); 567 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH24], 128, 0); 568 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], 128, 0); 569 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], 128, 0); 570 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28], 188*4, 0); 571 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 128, 0); 572 573 /* misc init ... */ 574 cx_write(MO_INPUT_FORMAT, ((1 << 13) | // agc enable 575 (1 << 12) | // agc gain 576 (1 << 11) | // adaptibe agc 577 (0 << 10) | // chroma agc 578 (0 << 9) | // ckillen 579 (7))); 580 581 /* setup image format */ 582 cx_andor(MO_COLOR_CTRL, 0x4000, 0x4000); 583 584 /* setup FIFO Thresholds */ 585 cx_write(MO_PDMA_STHRSH, 0x0807); 586 cx_write(MO_PDMA_DTHRSH, 0x0807); 587 588 /* fixes flashing of image */ 589 cx_write(MO_AGC_SYNC_TIP1, 0x0380000F); 590 cx_write(MO_AGC_BACK_VBI, 0x00E00555); 591 592 cx_write(MO_VID_INTSTAT, 0xFFFFFFFF); // Clear PIV int 593 cx_write(MO_PCI_INTSTAT, 0xFFFFFFFF); // Clear PCI int 594 cx_write(MO_INT1_STAT, 0xFFFFFFFF); // Clear RISC int 595 596 /* Reset on-board parts */ 597 cx_write(MO_SRST_IO, 0); 598 msleep(10); 599 cx_write(MO_SRST_IO, 1); 600 601 return 0; 602} 603 604/* ------------------------------------------------------------------ */ 605 606static inline unsigned int norm_swidth(v4l2_std_id norm) 607{ 608 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922; 609} 610 611static inline unsigned int norm_hdelay(v4l2_std_id norm) 612{ 613 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 135 : 186; 614} 615 616static inline unsigned int norm_vdelay(v4l2_std_id norm) 617{ 618 return (norm & V4L2_STD_625_50) ? 0x24 : 0x18; 619} 620 621static inline unsigned int norm_fsc8(v4l2_std_id norm) 622{ 623 if (norm & V4L2_STD_PAL_M) 624 return 28604892; // 3.575611 MHz 625 626 if (norm & (V4L2_STD_PAL_Nc)) 627 return 28656448; // 3.582056 MHz 628 629 if (norm & V4L2_STD_NTSC) // All NTSC/M and variants 630 return 28636360; // 3.57954545 MHz +/- 10 Hz 631 632 /* SECAM have also different sub carrier for chroma, 633 but step_db and step_dr, at cx88_set_tvnorm already handles that. 634 635 The same FSC applies to PAL/BGDKIH, PAL/60, NTSC/4.43 and PAL/N 636 */ 637 638 return 35468950; // 4.43361875 MHz +/- 5 Hz 639} 640 641static inline unsigned int norm_htotal(v4l2_std_id norm) 642{ 643 644 unsigned int fsc4=norm_fsc8(norm)/2; 645 646 /* returns 4*FSC / vtotal / frames per seconds */ 647 return (norm & V4L2_STD_625_50) ? 648 ((fsc4+312)/625+12)/25 : 649 ((fsc4+262)/525*1001+15000)/30000; 650} 651 652static inline unsigned int norm_vbipack(v4l2_std_id norm) 653{ 654 return (norm & V4L2_STD_625_50) ? 511 : 400; 655} 656 657int cx88_set_scale(struct cx88_core *core, unsigned int width, unsigned int height, 658 enum v4l2_field field) 659{ 660 unsigned int swidth = norm_swidth(core->tvnorm); 661 unsigned int sheight = norm_maxh(core->tvnorm); 662 u32 value; 663 664 dprintk(1,"set_scale: %dx%d [%s%s,%s]\n", width, height, 665 V4L2_FIELD_HAS_TOP(field) ? "T" : "", 666 V4L2_FIELD_HAS_BOTTOM(field) ? "B" : "", 667 v4l2_norm_to_name(core->tvnorm)); 668 if (!V4L2_FIELD_HAS_BOTH(field)) 669 height *= 2; 670 671 // recalc H delay and scale registers 672 value = (width * norm_hdelay(core->tvnorm)) / swidth; 673 value &= 0x3fe; 674 cx_write(MO_HDELAY_EVEN, value); 675 cx_write(MO_HDELAY_ODD, value); 676 dprintk(1,"set_scale: hdelay 0x%04x (width %d)\n", value,swidth); 677 678 value = (swidth * 4096 / width) - 4096; 679 cx_write(MO_HSCALE_EVEN, value); 680 cx_write(MO_HSCALE_ODD, value); 681 dprintk(1,"set_scale: hscale 0x%04x\n", value); 682 683 cx_write(MO_HACTIVE_EVEN, width); 684 cx_write(MO_HACTIVE_ODD, width); 685 dprintk(1,"set_scale: hactive 0x%04x\n", width); 686 687 // recalc V scale Register (delay is constant) 688 cx_write(MO_VDELAY_EVEN, norm_vdelay(core->tvnorm)); 689 cx_write(MO_VDELAY_ODD, norm_vdelay(core->tvnorm)); 690 dprintk(1,"set_scale: vdelay 0x%04x\n", norm_vdelay(core->tvnorm)); 691 692 value = (0x10000 - (sheight * 512 / height - 512)) & 0x1fff; 693 cx_write(MO_VSCALE_EVEN, value); 694 cx_write(MO_VSCALE_ODD, value); 695 dprintk(1,"set_scale: vscale 0x%04x\n", value); 696 697 cx_write(MO_VACTIVE_EVEN, sheight); 698 cx_write(MO_VACTIVE_ODD, sheight); 699 dprintk(1,"set_scale: vactive 0x%04x\n", sheight); 700 701 // setup filters 702 value = 0; 703 value |= (1 << 19); // CFILT (default) 704 if (core->tvnorm & V4L2_STD_SECAM) { 705 value |= (1 << 15); 706 value |= (1 << 16); 707 } 708 if (INPUT(core->input).type == CX88_VMUX_SVIDEO) 709 value |= (1 << 13) | (1 << 5); 710 if (V4L2_FIELD_INTERLACED == field) 711 value |= (1 << 3); // VINT (interlaced vertical scaling) 712 if (width < 385) 713 value |= (1 << 0); // 3-tap interpolation 714 if (width < 193) 715 value |= (1 << 1); // 5-tap interpolation 716 if (nocomb) 717 value |= (3 << 5); // disable comb filter 718 719 cx_andor(MO_FILTER_EVEN, 0x7ffc7f, value); /* preserve PEAKEN, PSEL */ 720 cx_andor(MO_FILTER_ODD, 0x7ffc7f, value); 721 dprintk(1,"set_scale: filter 0x%04x\n", value); 722 723 return 0; 724} 725 726static const u32 xtal = 28636363; 727 728static int set_pll(struct cx88_core *core, int prescale, u32 ofreq) 729{ 730 static const u32 pre[] = { 0, 0, 0, 3, 2, 1 }; 731 u64 pll; 732 u32 reg; 733 int i; 734 735 if (prescale < 2) 736 prescale = 2; 737 if (prescale > 5) 738 prescale = 5; 739 740 pll = ofreq * 8 * prescale * (u64)(1 << 20); 741 do_div(pll,xtal); 742 reg = (pll & 0x3ffffff) | (pre[prescale] << 26); 743 if (((reg >> 20) & 0x3f) < 14) { 744 printk("%s/0: pll out of range\n",core->name); 745 return -1; 746 } 747 748 dprintk(1,"set_pll: MO_PLL_REG 0x%08x [old=0x%08x,freq=%d]\n", 749 reg, cx_read(MO_PLL_REG), ofreq); 750 cx_write(MO_PLL_REG, reg); 751 for (i = 0; i < 100; i++) { 752 reg = cx_read(MO_DEVICE_STATUS); 753 if (reg & (1<<2)) { 754 dprintk(1,"pll locked [pre=%d,ofreq=%d]\n", 755 prescale,ofreq); 756 return 0; 757 } 758 dprintk(1,"pll not locked yet, waiting ...\n"); 759 msleep(10); 760 } 761 dprintk(1,"pll NOT locked [pre=%d,ofreq=%d]\n",prescale,ofreq); 762 return -1; 763} 764 765int cx88_start_audio_dma(struct cx88_core *core) 766{ 767 /* constant 128 made buzz in analog Nicam-stereo for bigger fifo_size */ 768 int bpl = cx88_sram_channels[SRAM_CH25].fifo_size/4; 769 770 int rds_bpl = cx88_sram_channels[SRAM_CH27].fifo_size/AUD_RDS_LINES; 771 772 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */ 773 if (cx_read(MO_AUD_DMACNTRL) & 0x10) 774 return 0; 775 776 /* setup fifo + format */ 777 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH25], bpl, 0); 778 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH26], bpl, 0); 779 cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH27], 780 rds_bpl, 0); 781 782 cx_write(MO_AUDD_LNGTH, bpl); /* fifo bpl size */ 783 cx_write(MO_AUDR_LNGTH, rds_bpl); /* fifo bpl size */ 784 785 /* enable Up, Down and Audio RDS fifo */ 786 cx_write(MO_AUD_DMACNTRL, 0x0007); 787 788 return 0; 789} 790 791int cx88_stop_audio_dma(struct cx88_core *core) 792{ 793 /* If downstream RISC is enabled, bail out; ALSA is managing DMA */ 794 if (cx_read(MO_AUD_DMACNTRL) & 0x10) 795 return 0; 796 797 /* stop dma */ 798 cx_write(MO_AUD_DMACNTRL, 0x0000); 799 800 return 0; 801} 802 803static int set_tvaudio(struct cx88_core *core) 804{ 805 v4l2_std_id norm = core->tvnorm; 806 807 if (CX88_VMUX_TELEVISION != INPUT(core->input).type && 808 CX88_VMUX_CABLE != INPUT(core->input).type) 809 return 0; 810 811 if (V4L2_STD_PAL_BG & norm) { 812 core->tvaudio = WW_BG; 813 814 } else if (V4L2_STD_PAL_DK & norm) { 815 core->tvaudio = WW_DK; 816 817 } else if (V4L2_STD_PAL_I & norm) { 818 core->tvaudio = WW_I; 819 820 } else if (V4L2_STD_SECAM_L & norm) { 821 core->tvaudio = WW_L; 822 823 } else if ((V4L2_STD_SECAM_B | V4L2_STD_SECAM_G | V4L2_STD_SECAM_H) & norm) { 824 core->tvaudio = WW_BG; 825 826 } else if (V4L2_STD_SECAM_DK & norm) { 827 core->tvaudio = WW_DK; 828 829 } else if ((V4L2_STD_NTSC_M & norm) || 830 (V4L2_STD_PAL_M & norm)) { 831 core->tvaudio = WW_BTSC; 832 833 } else if (V4L2_STD_NTSC_M_JP & norm) { 834 core->tvaudio = WW_EIAJ; 835 836 } else { 837 printk("%s/0: tvaudio support needs work for this tv norm [%s], sorry\n", 838 core->name, v4l2_norm_to_name(core->tvnorm)); 839 core->tvaudio = WW_NONE; 840 return 0; 841 } 842 843 cx_andor(MO_AFECFG_IO, 0x1f, 0x0); 844 cx88_set_tvaudio(core); 845 /* cx88_set_stereo(dev,V4L2_TUNER_MODE_STEREO); */ 846 847/* 848 This should be needed only on cx88-alsa. It seems that some cx88 chips have 849 bugs and does require DMA enabled for it to work. 850 */ 851 cx88_start_audio_dma(core); 852 return 0; 853} 854 855 856 857int cx88_set_tvnorm(struct cx88_core *core, v4l2_std_id norm) 858{ 859 u32 fsc8; 860 u32 adc_clock; 861 u32 vdec_clock; 862 u32 step_db,step_dr; 863 u64 tmp64; 864 u32 bdelay,agcdelay,htotal; 865 u32 cxiformat, cxoformat; 866 867 if (norm == core->tvnorm) 868 return 0; 869 if (core->v4ldev && (vb2_is_busy(&core->v4ldev->vb2_vidq) || 870 vb2_is_busy(&core->v4ldev->vb2_vbiq))) 871 return -EBUSY; 872 if (core->dvbdev && vb2_is_busy(&core->dvbdev->vb2_mpegq)) 873 return -EBUSY; 874 core->tvnorm = norm; 875 fsc8 = norm_fsc8(norm); 876 adc_clock = xtal; 877 vdec_clock = fsc8; 878 step_db = fsc8; 879 step_dr = fsc8; 880 881 if (norm & V4L2_STD_NTSC_M_JP) { 882 cxiformat = VideoFormatNTSCJapan; 883 cxoformat = 0x181f0008; 884 } else if (norm & V4L2_STD_NTSC_443) { 885 cxiformat = VideoFormatNTSC443; 886 cxoformat = 0x181f0008; 887 } else if (norm & V4L2_STD_PAL_M) { 888 cxiformat = VideoFormatPALM; 889 cxoformat = 0x1c1f0008; 890 } else if (norm & V4L2_STD_PAL_N) { 891 cxiformat = VideoFormatPALN; 892 cxoformat = 0x1c1f0008; 893 } else if (norm & V4L2_STD_PAL_Nc) { 894 cxiformat = VideoFormatPALNC; 895 cxoformat = 0x1c1f0008; 896 } else if (norm & V4L2_STD_PAL_60) { 897 cxiformat = VideoFormatPAL60; 898 cxoformat = 0x181f0008; 899 } else if (norm & V4L2_STD_NTSC) { 900 cxiformat = VideoFormatNTSC; 901 cxoformat = 0x181f0008; 902 } else if (norm & V4L2_STD_SECAM) { 903 step_db = 4250000 * 8; 904 step_dr = 4406250 * 8; 905 906 cxiformat = VideoFormatSECAM; 907 cxoformat = 0x181f0008; 908 } else { /* PAL */ 909 cxiformat = VideoFormatPAL; 910 cxoformat = 0x181f0008; 911 } 912 913 dprintk(1,"set_tvnorm: \"%s\" fsc8=%d adc=%d vdec=%d db/dr=%d/%d\n", 914 v4l2_norm_to_name(core->tvnorm), fsc8, adc_clock, vdec_clock, 915 step_db, step_dr); 916 set_pll(core,2,vdec_clock); 917 918 dprintk(1,"set_tvnorm: MO_INPUT_FORMAT 0x%08x [old=0x%08x]\n", 919 cxiformat, cx_read(MO_INPUT_FORMAT) & 0x0f); 920 /* Chroma AGC must be disabled if SECAM is used, we enable it 921 by default on PAL and NTSC */ 922 cx_andor(MO_INPUT_FORMAT, 0x40f, 923 norm & V4L2_STD_SECAM ? cxiformat : cxiformat | 0x400); 924 925 // FIXME: as-is from DScaler 926 dprintk(1,"set_tvnorm: MO_OUTPUT_FORMAT 0x%08x [old=0x%08x]\n", 927 cxoformat, cx_read(MO_OUTPUT_FORMAT)); 928 cx_write(MO_OUTPUT_FORMAT, cxoformat); 929 930 // MO_SCONV_REG = adc clock / video dec clock * 2^17 931 tmp64 = adc_clock * (u64)(1 << 17); 932 do_div(tmp64, vdec_clock); 933 dprintk(1,"set_tvnorm: MO_SCONV_REG 0x%08x [old=0x%08x]\n", 934 (u32)tmp64, cx_read(MO_SCONV_REG)); 935 cx_write(MO_SCONV_REG, (u32)tmp64); 936 937 // MO_SUB_STEP = 8 * fsc / video dec clock * 2^22 938 tmp64 = step_db * (u64)(1 << 22); 939 do_div(tmp64, vdec_clock); 940 dprintk(1,"set_tvnorm: MO_SUB_STEP 0x%08x [old=0x%08x]\n", 941 (u32)tmp64, cx_read(MO_SUB_STEP)); 942 cx_write(MO_SUB_STEP, (u32)tmp64); 943 944 // MO_SUB_STEP_DR = 8 * 4406250 / video dec clock * 2^22 945 tmp64 = step_dr * (u64)(1 << 22); 946 do_div(tmp64, vdec_clock); 947 dprintk(1,"set_tvnorm: MO_SUB_STEP_DR 0x%08x [old=0x%08x]\n", 948 (u32)tmp64, cx_read(MO_SUB_STEP_DR)); 949 cx_write(MO_SUB_STEP_DR, (u32)tmp64); 950 951 // bdelay + agcdelay 952 bdelay = vdec_clock * 65 / 20000000 + 21; 953 agcdelay = vdec_clock * 68 / 20000000 + 15; 954 dprintk(1,"set_tvnorm: MO_AGC_BURST 0x%08x [old=0x%08x,bdelay=%d,agcdelay=%d]\n", 955 (bdelay << 8) | agcdelay, cx_read(MO_AGC_BURST), bdelay, agcdelay); 956 cx_write(MO_AGC_BURST, (bdelay << 8) | agcdelay); 957 958 // htotal 959 tmp64 = norm_htotal(norm) * (u64)vdec_clock; 960 do_div(tmp64, fsc8); 961 htotal = (u32)tmp64; 962 dprintk(1,"set_tvnorm: MO_HTOTAL 0x%08x [old=0x%08x,htotal=%d]\n", 963 htotal, cx_read(MO_HTOTAL), (u32)tmp64); 964 cx_andor(MO_HTOTAL, 0x07ff, htotal); 965 966 // vbi stuff, set vbi offset to 10 (for 20 Clk*2 pixels), this makes 967 // the effective vbi offset ~244 samples, the same as the Bt8x8 968 cx_write(MO_VBI_PACKET, (10<<11) | norm_vbipack(norm)); 969 970 // this is needed as well to set all tvnorm parameter 971 cx88_set_scale(core, 320, 240, V4L2_FIELD_INTERLACED); 972 973 // audio 974 set_tvaudio(core); 975 976 // tell i2c chips 977 call_all(core, video, s_std, norm); 978 979 /* The chroma_agc control should be inaccessible if the video format is SECAM */ 980 v4l2_ctrl_grab(core->chroma_agc, cxiformat == VideoFormatSECAM); 981 982 // done 983 return 0; 984} 985 986/* ------------------------------------------------------------------ */ 987 988void cx88_vdev_init(struct cx88_core *core, 989 struct pci_dev *pci, 990 struct video_device *vfd, 991 const struct video_device *template_, 992 const char *type) 993{ 994 *vfd = *template_; 995 996 /* 997 * The dev pointer of v4l2_device is NULL, instead we set the 998 * video_device dev_parent pointer to the correct PCI bus device. 999 * This driver is a rare example where there is one v4l2_device, 1000 * but the video nodes have different parent (PCI) devices. 1001 */ 1002 vfd->v4l2_dev = &core->v4l2_dev; 1003 vfd->dev_parent = &pci->dev; 1004 vfd->release = video_device_release_empty; 1005 vfd->lock = &core->lock; 1006 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", 1007 core->name, type, core->board.name); 1008} 1009 1010struct cx88_core* cx88_core_get(struct pci_dev *pci) 1011{ 1012 struct cx88_core *core; 1013 1014 mutex_lock(&devlist); 1015 list_for_each_entry(core, &cx88_devlist, devlist) { 1016 if (pci->bus->number != core->pci_bus) 1017 continue; 1018 if (PCI_SLOT(pci->devfn) != core->pci_slot) 1019 continue; 1020 1021 if (0 != cx88_get_resources(core, pci)) { 1022 mutex_unlock(&devlist); 1023 return NULL; 1024 } 1025 atomic_inc(&core->refcount); 1026 mutex_unlock(&devlist); 1027 return core; 1028 } 1029 1030 core = cx88_core_create(pci, cx88_devcount); 1031 if (NULL != core) { 1032 cx88_devcount++; 1033 list_add_tail(&core->devlist, &cx88_devlist); 1034 } 1035 1036 mutex_unlock(&devlist); 1037 return core; 1038} 1039 1040void cx88_core_put(struct cx88_core *core, struct pci_dev *pci) 1041{ 1042 release_mem_region(pci_resource_start(pci,0), 1043 pci_resource_len(pci,0)); 1044 1045 if (!atomic_dec_and_test(&core->refcount)) 1046 return; 1047 1048 mutex_lock(&devlist); 1049 cx88_ir_fini(core); 1050 if (0 == core->i2c_rc) { 1051 if (core->i2c_rtc) 1052 i2c_unregister_device(core->i2c_rtc); 1053 i2c_del_adapter(&core->i2c_adap); 1054 } 1055 list_del(&core->devlist); 1056 iounmap(core->lmmio); 1057 cx88_devcount--; 1058 mutex_unlock(&devlist); 1059 v4l2_ctrl_handler_free(&core->video_hdl); 1060 v4l2_ctrl_handler_free(&core->audio_hdl); 1061 v4l2_device_unregister(&core->v4l2_dev); 1062 kfree(core); 1063} 1064 1065/* ------------------------------------------------------------------ */ 1066 1067EXPORT_SYMBOL(cx88_print_irqbits); 1068 1069EXPORT_SYMBOL(cx88_core_irq); 1070EXPORT_SYMBOL(cx88_wakeup); 1071EXPORT_SYMBOL(cx88_reset); 1072EXPORT_SYMBOL(cx88_shutdown); 1073 1074EXPORT_SYMBOL(cx88_risc_buffer); 1075EXPORT_SYMBOL(cx88_risc_databuffer); 1076 1077EXPORT_SYMBOL(cx88_sram_channels); 1078EXPORT_SYMBOL(cx88_sram_channel_setup); 1079EXPORT_SYMBOL(cx88_sram_channel_dump); 1080 1081EXPORT_SYMBOL(cx88_set_tvnorm); 1082EXPORT_SYMBOL(cx88_set_scale); 1083 1084EXPORT_SYMBOL(cx88_vdev_init); 1085EXPORT_SYMBOL(cx88_core_get); 1086EXPORT_SYMBOL(cx88_core_put); 1087 1088EXPORT_SYMBOL(cx88_ir_start); 1089EXPORT_SYMBOL(cx88_ir_stop); 1090