1/* 2 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#ifndef FIMC_LITE_REG_H_ 10#define FIMC_LITE_REG_H_ 11 12#include "fimc-lite.h" 13 14/* Camera Source size */ 15#define FLITE_REG_CISRCSIZE 0x00 16#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14) 17#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14) 18#define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14) 19#define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14) 20#define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14) 21#define FLITE_REG_CISRCSIZE_SIZE_CAM_MASK (0x3fff << 16 | 0x3fff) 22 23/* Global control */ 24#define FLITE_REG_CIGCTRL 0x04 25#define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24) 26#define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24) 27#define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24) 28#define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24) 29#define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24) 30/* User defined formats. x = 0...15 */ 31#define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24) 32#define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24) 33#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE (1 << 21) 34#define FLITE_REG_CIGCTRL_ODMA_DISABLE (1 << 20) 35#define FLITE_REG_CIGCTRL_SWRST_REQ (1 << 19) 36#define FLITE_REG_CIGCTRL_SWRST_RDY (1 << 18) 37#define FLITE_REG_CIGCTRL_SWRST (1 << 17) 38#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR (1 << 15) 39#define FLITE_REG_CIGCTRL_INVPOLPCLK (1 << 14) 40#define FLITE_REG_CIGCTRL_INVPOLVSYNC (1 << 13) 41#define FLITE_REG_CIGCTRL_INVPOLHREF (1 << 12) 42/* Interrupts mask bits (1 disables an interrupt) */ 43#define FLITE_REG_CIGCTRL_IRQ_LASTEN (1 << 8) 44#define FLITE_REG_CIGCTRL_IRQ_ENDEN (1 << 7) 45#define FLITE_REG_CIGCTRL_IRQ_STARTEN (1 << 6) 46#define FLITE_REG_CIGCTRL_IRQ_OVFEN (1 << 5) 47#define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5) 48#define FLITE_REG_CIGCTRL_SELCAM_MIPI (1 << 3) 49 50/* Image Capture Enable */ 51#define FLITE_REG_CIIMGCPT 0x08 52#define FLITE_REG_CIIMGCPT_IMGCPTEN (1 << 31) 53#define FLITE_REG_CIIMGCPT_CPT_FREN (1 << 25) 54#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18) 55#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18) 56 57/* Capture Sequence */ 58#define FLITE_REG_CICPTSEQ 0x0c 59 60/* Camera Window Offset */ 61#define FLITE_REG_CIWDOFST 0x10 62#define FLITE_REG_CIWDOFST_WINOFSEN (1 << 31) 63#define FLITE_REG_CIWDOFST_CLROVIY (1 << 31) 64#define FLITE_REG_CIWDOFST_CLROVFICB (1 << 15) 65#define FLITE_REG_CIWDOFST_CLROVFICR (1 << 14) 66#define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff) 67 68/* Camera Window Offset2 */ 69#define FLITE_REG_CIWDOFST2 0x14 70 71/* Camera Output DMA Format */ 72#define FLITE_REG_CIODMAFMT 0x18 73#define FLITE_REG_CIODMAFMT_RAW_CON (1 << 15) 74#define FLITE_REG_CIODMAFMT_PACK12 (1 << 14) 75#define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4) 76#define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4) 77#define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4) 78#define FLITE_REG_CIODMAFMT_CRYCBY (3 << 4) 79#define FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK (0x3 << 4) 80 81/* Camera Output Canvas */ 82#define FLITE_REG_CIOCAN 0x20 83#define FLITE_REG_CIOCAN_MASK ((0x3fff << 16) | 0x3fff) 84 85/* Camera Output DMA Offset */ 86#define FLITE_REG_CIOOFF 0x24 87#define FLITE_REG_CIOOFF_MASK ((0x3fff << 16) | 0x3fff) 88 89/* Camera Output DMA Start Address */ 90#define FLITE_REG_CIOSA 0x30 91 92/* Camera Status */ 93#define FLITE_REG_CISTATUS 0x40 94#define FLITE_REG_CISTATUS_MIPI_VVALID (1 << 22) 95#define FLITE_REG_CISTATUS_MIPI_HVALID (1 << 21) 96#define FLITE_REG_CISTATUS_MIPI_DVALID (1 << 20) 97#define FLITE_REG_CISTATUS_ITU_VSYNC (1 << 14) 98#define FLITE_REG_CISTATUS_ITU_HREFF (1 << 13) 99#define FLITE_REG_CISTATUS_OVFIY (1 << 10) 100#define FLITE_REG_CISTATUS_OVFICB (1 << 9) 101#define FLITE_REG_CISTATUS_OVFICR (1 << 8) 102#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW (1 << 7) 103#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND (1 << 6) 104#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART (1 << 5) 105#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND (1 << 4) 106#define FLITE_REG_CISTATUS_IRQ_CAM (1 << 0) 107#define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4) 108 109/* Camera Status2 */ 110#define FLITE_REG_CISTATUS2 0x44 111#define FLITE_REG_CISTATUS2_LASTCAPEND (1 << 1) 112#define FLITE_REG_CISTATUS2_FRMEND (1 << 0) 113 114/* Qos Threshold */ 115#define FLITE_REG_CITHOLD 0xf0 116#define FLITE_REG_CITHOLD_W_QOS_EN (1 << 30) 117 118/* Camera General Purpose */ 119#define FLITE_REG_CIGENERAL 0xfc 120/* b0: 1 - camera B, 0 - camera A */ 121#define FLITE_REG_CIGENERAL_CAM_B (1 << 0) 122 123#define FLITE_REG_CIFCNTSEQ 0x100 124#define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x))) 125 126/* ---------------------------------------------------------------------------- 127 * Function declarations 128 */ 129void flite_hw_reset(struct fimc_lite *dev); 130void flite_hw_clear_pending_irq(struct fimc_lite *dev); 131u32 flite_hw_get_interrupt_source(struct fimc_lite *dev); 132void flite_hw_clear_last_capture_end(struct fimc_lite *dev); 133void flite_hw_set_interrupt_mask(struct fimc_lite *dev); 134void flite_hw_capture_start(struct fimc_lite *dev); 135void flite_hw_capture_stop(struct fimc_lite *dev); 136void flite_hw_set_camera_bus(struct fimc_lite *dev, 137 struct fimc_source_info *s_info); 138void flite_hw_set_camera_polarity(struct fimc_lite *dev, 139 struct fimc_source_info *cam); 140void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f); 141void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f); 142 143void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f, 144 bool enable); 145void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f); 146void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on); 147void flite_hw_dump_regs(struct fimc_lite *dev, const char *label); 148void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf); 149void flite_hw_mask_dma_buffer(struct fimc_lite *dev, u32 index); 150 151static inline void flite_hw_set_dma_buf_mask(struct fimc_lite *dev, u32 mask) 152{ 153 writel(mask, dev->regs + FLITE_REG_CIFCNTSEQ); 154} 155 156#endif /* FIMC_LITE_REG_H */ 157