1/* 2 * drivers/media/platform/samsung/mfc5/s5p_mfc_opr_v5.c 3 * 4 * Samsung MFC (Multi Function Codec - FIMV) driver 5 * This file contains hw related functions. 6 * 7 * Kamil Debski, Copyright (c) 2011 Samsung Electronics 8 * http://www.samsung.com/ 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15#include "s5p_mfc_common.h" 16#include "s5p_mfc_cmd.h" 17#include "s5p_mfc_ctrl.h" 18#include "s5p_mfc_debug.h" 19#include "s5p_mfc_intr.h" 20#include "s5p_mfc_pm.h" 21#include "s5p_mfc_opr.h" 22#include "s5p_mfc_opr_v5.h" 23#include <asm/cacheflush.h> 24#include <linux/delay.h> 25#include <linux/dma-mapping.h> 26#include <linux/err.h> 27#include <linux/firmware.h> 28#include <linux/io.h> 29#include <linux/jiffies.h> 30#include <linux/mm.h> 31#include <linux/sched.h> 32 33#define OFFSETA(x) (((x) - dev->bank1) >> MFC_OFFSET_SHIFT) 34#define OFFSETB(x) (((x) - dev->bank2) >> MFC_OFFSET_SHIFT) 35 36/* Allocate temporary buffers for decoding */ 37static int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx) 38{ 39 struct s5p_mfc_dev *dev = ctx->dev; 40 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; 41 int ret; 42 43 ctx->dsc.size = buf_size->dsc; 44 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->dsc); 45 if (ret) { 46 mfc_err("Failed to allocate temporary buffer\n"); 47 return ret; 48 } 49 50 BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 51 memset(ctx->dsc.virt, 0, ctx->dsc.size); 52 wmb(); 53 return 0; 54} 55 56 57/* Release temporary buffers for decoding */ 58static void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx) 59{ 60 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->dsc); 61} 62 63/* Allocate codec buffers */ 64static int s5p_mfc_alloc_codec_buffers_v5(struct s5p_mfc_ctx *ctx) 65{ 66 struct s5p_mfc_dev *dev = ctx->dev; 67 unsigned int enc_ref_y_size = 0; 68 unsigned int enc_ref_c_size = 0; 69 unsigned int guard_width, guard_height; 70 int ret; 71 72 if (ctx->type == MFCINST_DECODER) { 73 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", 74 ctx->luma_size, ctx->chroma_size, ctx->mv_size); 75 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); 76 } else if (ctx->type == MFCINST_ENCODER) { 77 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 78 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 79 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); 80 81 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { 82 enc_ref_c_size = ALIGN(ctx->img_width, 83 S5P_FIMV_NV12MT_HALIGN) 84 * ALIGN(ctx->img_height >> 1, 85 S5P_FIMV_NV12MT_VALIGN); 86 enc_ref_c_size = ALIGN(enc_ref_c_size, 87 S5P_FIMV_NV12MT_SALIGN); 88 } else { 89 guard_width = ALIGN(ctx->img_width + 16, 90 S5P_FIMV_NV12MT_HALIGN); 91 guard_height = ALIGN((ctx->img_height >> 1) + 4, 92 S5P_FIMV_NV12MT_VALIGN); 93 enc_ref_c_size = ALIGN(guard_width * guard_height, 94 S5P_FIMV_NV12MT_SALIGN); 95 } 96 mfc_debug(2, "recon luma size: %d chroma size: %d\n", 97 enc_ref_y_size, enc_ref_c_size); 98 } else { 99 return -EINVAL; 100 } 101 /* Codecs have different memory requirements */ 102 switch (ctx->codec_mode) { 103 case S5P_MFC_CODEC_H264_DEC: 104 ctx->bank1.size = 105 ALIGN(S5P_FIMV_DEC_NB_IP_SIZE + 106 S5P_FIMV_DEC_VERT_NB_MV_SIZE, 107 S5P_FIMV_DEC_BUF_ALIGN); 108 ctx->bank2.size = ctx->total_dpb_count * ctx->mv_size; 109 break; 110 case S5P_MFC_CODEC_MPEG4_DEC: 111 ctx->bank1.size = 112 ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE + 113 S5P_FIMV_DEC_UPNB_MV_SIZE + 114 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + 115 S5P_FIMV_DEC_STX_PARSER_SIZE + 116 S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE, 117 S5P_FIMV_DEC_BUF_ALIGN); 118 ctx->bank2.size = 0; 119 break; 120 case S5P_MFC_CODEC_VC1RCV_DEC: 121 case S5P_MFC_CODEC_VC1_DEC: 122 ctx->bank1.size = 123 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + 124 S5P_FIMV_DEC_UPNB_MV_SIZE + 125 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + 126 S5P_FIMV_DEC_NB_DCAC_SIZE + 127 3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE, 128 S5P_FIMV_DEC_BUF_ALIGN); 129 ctx->bank2.size = 0; 130 break; 131 case S5P_MFC_CODEC_MPEG2_DEC: 132 ctx->bank1.size = 0; 133 ctx->bank2.size = 0; 134 break; 135 case S5P_MFC_CODEC_H263_DEC: 136 ctx->bank1.size = 137 ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + 138 S5P_FIMV_DEC_UPNB_MV_SIZE + 139 S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + 140 S5P_FIMV_DEC_NB_DCAC_SIZE, 141 S5P_FIMV_DEC_BUF_ALIGN); 142 ctx->bank2.size = 0; 143 break; 144 case S5P_MFC_CODEC_H264_ENC: 145 ctx->bank1.size = (enc_ref_y_size * 2) + 146 S5P_FIMV_ENC_UPMV_SIZE + 147 S5P_FIMV_ENC_COLFLG_SIZE + 148 S5P_FIMV_ENC_INTRAMD_SIZE + 149 S5P_FIMV_ENC_NBORINFO_SIZE; 150 ctx->bank2.size = (enc_ref_y_size * 2) + 151 (enc_ref_c_size * 4) + 152 S5P_FIMV_ENC_INTRAPRED_SIZE; 153 break; 154 case S5P_MFC_CODEC_MPEG4_ENC: 155 ctx->bank1.size = (enc_ref_y_size * 2) + 156 S5P_FIMV_ENC_UPMV_SIZE + 157 S5P_FIMV_ENC_COLFLG_SIZE + 158 S5P_FIMV_ENC_ACDCCOEF_SIZE; 159 ctx->bank2.size = (enc_ref_y_size * 2) + 160 (enc_ref_c_size * 4); 161 break; 162 case S5P_MFC_CODEC_H263_ENC: 163 ctx->bank1.size = (enc_ref_y_size * 2) + 164 S5P_FIMV_ENC_UPMV_SIZE + 165 S5P_FIMV_ENC_ACDCCOEF_SIZE; 166 ctx->bank2.size = (enc_ref_y_size * 2) + 167 (enc_ref_c_size * 4); 168 break; 169 default: 170 break; 171 } 172 /* Allocate only if memory from bank 1 is necessary */ 173 if (ctx->bank1.size > 0) { 174 175 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1); 176 if (ret) { 177 mfc_err("Failed to allocate Bank1 temporary buffer\n"); 178 return ret; 179 } 180 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 181 } 182 /* Allocate only if memory from bank 2 is necessary */ 183 if (ctx->bank2.size > 0) { 184 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_r, &ctx->bank2); 185 if (ret) { 186 mfc_err("Failed to allocate Bank2 temporary buffer\n"); 187 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); 188 return ret; 189 } 190 BUG_ON(ctx->bank2.dma & ((1 << MFC_BANK2_ALIGN_ORDER) - 1)); 191 } 192 return 0; 193} 194 195/* Release buffers allocated for codec */ 196static void s5p_mfc_release_codec_buffers_v5(struct s5p_mfc_ctx *ctx) 197{ 198 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); 199 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_r, &ctx->bank2); 200} 201 202/* Allocate memory for instance data buffer */ 203static int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx) 204{ 205 struct s5p_mfc_dev *dev = ctx->dev; 206 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; 207 int ret; 208 209 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 210 ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) 211 ctx->ctx.size = buf_size->h264_ctx; 212 else 213 ctx->ctx.size = buf_size->non_h264_ctx; 214 215 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx); 216 if (ret) { 217 mfc_err("Failed to allocate instance buffer\n"); 218 return ret; 219 } 220 ctx->ctx.ofs = OFFSETA(ctx->ctx.dma); 221 222 /* Zero content of the allocated memory */ 223 memset(ctx->ctx.virt, 0, ctx->ctx.size); 224 wmb(); 225 226 /* Initialize shared memory */ 227 ctx->shm.size = buf_size->shm; 228 ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->shm); 229 if (ret) { 230 mfc_err("Failed to allocate shared memory buffer\n"); 231 s5p_mfc_release_priv_buf(dev->mem_dev_l, &ctx->ctx); 232 return ret; 233 } 234 235 /* shared memory offset only keeps the offset from base (port a) */ 236 ctx->shm.ofs = ctx->shm.dma - dev->bank1; 237 BUG_ON(ctx->shm.ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); 238 239 memset(ctx->shm.virt, 0, buf_size->shm); 240 wmb(); 241 return 0; 242} 243 244/* Release instance buffer */ 245static void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx) 246{ 247 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx); 248 s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->shm); 249} 250 251static int s5p_mfc_alloc_dev_context_buffer_v5(struct s5p_mfc_dev *dev) 252{ 253 /* NOP */ 254 255 return 0; 256} 257 258static void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev) 259{ 260 /* NOP */ 261} 262 263static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data, 264 unsigned int ofs) 265{ 266 writel(data, (void *)(ctx->shm.virt + ofs)); 267 wmb(); 268} 269 270static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx, 271 unsigned long ofs) 272{ 273 rmb(); 274 return readl((void *)(ctx->shm.virt + ofs)); 275} 276 277static void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx) 278{ 279 unsigned int guard_width, guard_height; 280 281 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); 282 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 283 mfc_debug(2, 284 "SEQ Done: Movie dimensions %dx%d, buffer dimensions: %dx%d\n", 285 ctx->img_width, ctx->img_height, ctx->buf_width, 286 ctx->buf_height); 287 288 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { 289 ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height, 290 S5P_FIMV_DEC_BUF_ALIGN); 291 ctx->chroma_size = ALIGN(ctx->buf_width * 292 ALIGN((ctx->img_height >> 1), 293 S5P_FIMV_NV12MT_VALIGN), 294 S5P_FIMV_DEC_BUF_ALIGN); 295 ctx->mv_size = ALIGN(ctx->buf_width * 296 ALIGN((ctx->buf_height >> 2), 297 S5P_FIMV_NV12MT_VALIGN), 298 S5P_FIMV_DEC_BUF_ALIGN); 299 } else { 300 guard_width = 301 ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN); 302 guard_height = 303 ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN); 304 ctx->luma_size = ALIGN(guard_width * guard_height, 305 S5P_FIMV_DEC_BUF_ALIGN); 306 307 guard_width = 308 ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN); 309 guard_height = 310 ALIGN((ctx->img_height >> 1) + 4, 311 S5P_FIMV_NV12MT_VALIGN); 312 ctx->chroma_size = ALIGN(guard_width * guard_height, 313 S5P_FIMV_DEC_BUF_ALIGN); 314 315 ctx->mv_size = 0; 316 } 317} 318 319static void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx) 320{ 321 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { 322 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN); 323 324 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) 325 * ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN); 326 ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) 327 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN); 328 329 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN); 330 ctx->chroma_size = 331 ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN); 332 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) { 333 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); 334 335 ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 336 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 337 ctx->chroma_size = 338 ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 339 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); 340 341 ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN); 342 ctx->chroma_size = 343 ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN); 344 } 345} 346 347/* Set registers for decoding temporary buffers */ 348static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx) 349{ 350 struct s5p_mfc_dev *dev = ctx->dev; 351 struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; 352 353 mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); 354 mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); 355} 356 357/* Set registers for shared buffer */ 358static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx) 359{ 360 struct s5p_mfc_dev *dev = ctx->dev; 361 mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR); 362} 363 364/* Set registers for decoding stream buffer */ 365static int s5p_mfc_set_dec_stream_buffer_v5(struct s5p_mfc_ctx *ctx, 366 int buf_addr, unsigned int start_num_byte, 367 unsigned int buf_size) 368{ 369 struct s5p_mfc_dev *dev = ctx->dev; 370 371 mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR); 372 mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE); 373 mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE); 374 s5p_mfc_write_info_v5(ctx, start_num_byte, START_BYTE_NUM); 375 return 0; 376} 377 378/* Set decoding frame buffer */ 379static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx) 380{ 381 unsigned int frame_size_lu, i; 382 unsigned int frame_size_ch, frame_size_mv; 383 struct s5p_mfc_dev *dev = ctx->dev; 384 unsigned int dpb; 385 size_t buf_addr1, buf_addr2; 386 int buf_size1, buf_size2; 387 388 buf_addr1 = ctx->bank1.dma; 389 buf_size1 = ctx->bank1.size; 390 buf_addr2 = ctx->bank2.dma; 391 buf_size2 = ctx->bank2.size; 392 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & 393 ~S5P_FIMV_DPB_COUNT_MASK; 394 mfc_write(dev, ctx->total_dpb_count | dpb, 395 S5P_FIMV_SI_CH0_DPB_CONF_CTRL); 396 s5p_mfc_set_shared_buffer(ctx); 397 switch (ctx->codec_mode) { 398 case S5P_MFC_CODEC_H264_DEC: 399 mfc_write(dev, OFFSETA(buf_addr1), 400 S5P_FIMV_H264_VERT_NB_MV_ADR); 401 buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE; 402 buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE; 403 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR); 404 buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE; 405 buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE; 406 break; 407 case S5P_MFC_CODEC_MPEG4_DEC: 408 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR); 409 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; 410 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; 411 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR); 412 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; 413 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; 414 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR); 415 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 416 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 417 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR); 418 buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE; 419 buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE; 420 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR); 421 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 422 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 423 break; 424 case S5P_MFC_CODEC_H263_DEC: 425 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR); 426 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 427 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 428 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR); 429 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; 430 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; 431 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR); 432 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 433 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 434 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR); 435 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; 436 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; 437 break; 438 case S5P_MFC_CODEC_VC1_DEC: 439 case S5P_MFC_CODEC_VC1RCV_DEC: 440 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR); 441 buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; 442 buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; 443 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR); 444 buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 445 buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; 446 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR); 447 buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; 448 buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; 449 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR); 450 buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 451 buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; 452 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR); 453 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 454 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 455 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR); 456 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 457 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 458 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR); 459 buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 460 buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; 461 break; 462 case S5P_MFC_CODEC_MPEG2_DEC: 463 break; 464 default: 465 mfc_err("Unknown codec for decoding (%x)\n", 466 ctx->codec_mode); 467 return -EINVAL; 468 } 469 frame_size_lu = ctx->luma_size; 470 frame_size_ch = ctx->chroma_size; 471 frame_size_mv = ctx->mv_size; 472 mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size_lu, frame_size_ch, 473 frame_size_mv); 474 for (i = 0; i < ctx->total_dpb_count; i++) { 475 /* Bank2 */ 476 mfc_debug(2, "Luma %d: %zx\n", i, 477 ctx->dst_bufs[i].cookie.raw.luma); 478 mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma), 479 S5P_FIMV_DEC_LUMA_ADR + i * 4); 480 mfc_debug(2, "\tChroma %d: %zx\n", i, 481 ctx->dst_bufs[i].cookie.raw.chroma); 482 mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma), 483 S5P_FIMV_DEC_CHROMA_ADR + i * 4); 484 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { 485 mfc_debug(2, "\tBuf2: %zx, size: %d\n", 486 buf_addr2, buf_size2); 487 mfc_write(dev, OFFSETB(buf_addr2), 488 S5P_FIMV_H264_MV_ADR + i * 4); 489 buf_addr2 += frame_size_mv; 490 buf_size2 -= frame_size_mv; 491 } 492 } 493 mfc_debug(2, "Buf1: %zu, buf_size1: %d\n", buf_addr1, buf_size1); 494 mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n", 495 buf_size1, buf_size2, ctx->total_dpb_count); 496 if (buf_size1 < 0 || buf_size2 < 0) { 497 mfc_debug(2, "Not enough memory has been allocated\n"); 498 return -ENOMEM; 499 } 500 s5p_mfc_write_info_v5(ctx, frame_size_lu, ALLOC_LUMA_DPB_SIZE); 501 s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE); 502 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) 503 s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE); 504 mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK) 505 << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), 506 S5P_FIMV_SI_CH0_INST_ID); 507 return 0; 508} 509 510/* Set registers for encoding stream buffer */ 511static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx, 512 unsigned long addr, unsigned int size) 513{ 514 struct s5p_mfc_dev *dev = ctx->dev; 515 516 mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR); 517 mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE); 518 return 0; 519} 520 521static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, 522 unsigned long y_addr, unsigned long c_addr) 523{ 524 struct s5p_mfc_dev *dev = ctx->dev; 525 526 mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR); 527 mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR); 528} 529 530static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, 531 unsigned long *y_addr, unsigned long *c_addr) 532{ 533 struct s5p_mfc_dev *dev = ctx->dev; 534 535 *y_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR) 536 << MFC_OFFSET_SHIFT); 537 *c_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR) 538 << MFC_OFFSET_SHIFT); 539} 540 541/* Set encoding ref & codec buffer */ 542static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) 543{ 544 struct s5p_mfc_dev *dev = ctx->dev; 545 size_t buf_addr1, buf_addr2; 546 size_t buf_size1, buf_size2; 547 unsigned int enc_ref_y_size, enc_ref_c_size; 548 unsigned int guard_width, guard_height; 549 int i; 550 551 buf_addr1 = ctx->bank1.dma; 552 buf_size1 = ctx->bank1.size; 553 buf_addr2 = ctx->bank2.dma; 554 buf_size2 = ctx->bank2.size; 555 enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 556 * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); 557 enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); 558 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { 559 enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) 560 * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); 561 enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN); 562 } else { 563 guard_width = ALIGN(ctx->img_width + 16, 564 S5P_FIMV_NV12MT_HALIGN); 565 guard_height = ALIGN((ctx->img_height >> 1) + 4, 566 S5P_FIMV_NV12MT_VALIGN); 567 enc_ref_c_size = ALIGN(guard_width * guard_height, 568 S5P_FIMV_NV12MT_SALIGN); 569 } 570 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2); 571 switch (ctx->codec_mode) { 572 case S5P_MFC_CODEC_H264_ENC: 573 for (i = 0; i < 2; i++) { 574 mfc_write(dev, OFFSETA(buf_addr1), 575 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); 576 buf_addr1 += enc_ref_y_size; 577 buf_size1 -= enc_ref_y_size; 578 579 mfc_write(dev, OFFSETB(buf_addr2), 580 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); 581 buf_addr2 += enc_ref_y_size; 582 buf_size2 -= enc_ref_y_size; 583 } 584 for (i = 0; i < 4; i++) { 585 mfc_write(dev, OFFSETB(buf_addr2), 586 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); 587 buf_addr2 += enc_ref_c_size; 588 buf_size2 -= enc_ref_c_size; 589 } 590 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR); 591 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; 592 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; 593 mfc_write(dev, OFFSETA(buf_addr1), 594 S5P_FIMV_H264_COZERO_FLAG_ADR); 595 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; 596 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; 597 mfc_write(dev, OFFSETA(buf_addr1), 598 S5P_FIMV_H264_UP_INTRA_MD_ADR); 599 buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE; 600 buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE; 601 mfc_write(dev, OFFSETB(buf_addr2), 602 S5P_FIMV_H264_UP_INTRA_PRED_ADR); 603 buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE; 604 buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE; 605 mfc_write(dev, OFFSETA(buf_addr1), 606 S5P_FIMV_H264_NBOR_INFO_ADR); 607 buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE; 608 buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE; 609 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", 610 buf_size1, buf_size2); 611 break; 612 case S5P_MFC_CODEC_MPEG4_ENC: 613 for (i = 0; i < 2; i++) { 614 mfc_write(dev, OFFSETA(buf_addr1), 615 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); 616 buf_addr1 += enc_ref_y_size; 617 buf_size1 -= enc_ref_y_size; 618 mfc_write(dev, OFFSETB(buf_addr2), 619 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); 620 buf_addr2 += enc_ref_y_size; 621 buf_size2 -= enc_ref_y_size; 622 } 623 for (i = 0; i < 4; i++) { 624 mfc_write(dev, OFFSETB(buf_addr2), 625 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); 626 buf_addr2 += enc_ref_c_size; 627 buf_size2 -= enc_ref_c_size; 628 } 629 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR); 630 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; 631 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; 632 mfc_write(dev, OFFSETA(buf_addr1), 633 S5P_FIMV_MPEG4_COZERO_FLAG_ADR); 634 buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; 635 buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; 636 mfc_write(dev, OFFSETA(buf_addr1), 637 S5P_FIMV_MPEG4_ACDC_COEF_ADR); 638 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; 639 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; 640 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", 641 buf_size1, buf_size2); 642 break; 643 case S5P_MFC_CODEC_H263_ENC: 644 for (i = 0; i < 2; i++) { 645 mfc_write(dev, OFFSETA(buf_addr1), 646 S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); 647 buf_addr1 += enc_ref_y_size; 648 buf_size1 -= enc_ref_y_size; 649 mfc_write(dev, OFFSETB(buf_addr2), 650 S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); 651 buf_addr2 += enc_ref_y_size; 652 buf_size2 -= enc_ref_y_size; 653 } 654 for (i = 0; i < 4; i++) { 655 mfc_write(dev, OFFSETB(buf_addr2), 656 S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); 657 buf_addr2 += enc_ref_c_size; 658 buf_size2 -= enc_ref_c_size; 659 } 660 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR); 661 buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; 662 buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; 663 mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR); 664 buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; 665 buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; 666 mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", 667 buf_size1, buf_size2); 668 break; 669 default: 670 mfc_err("Unknown codec set for encoding: %d\n", 671 ctx->codec_mode); 672 return -EINVAL; 673 } 674 return 0; 675} 676 677static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) 678{ 679 struct s5p_mfc_dev *dev = ctx->dev; 680 struct s5p_mfc_enc_params *p = &ctx->enc_params; 681 unsigned int reg; 682 unsigned int shm; 683 684 /* width */ 685 mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX); 686 /* height */ 687 mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX); 688 /* pictype : enable, IDR period */ 689 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); 690 reg |= (1 << 18); 691 reg &= ~(0xFFFF); 692 reg |= p->gop_size; 693 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); 694 mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON); 695 /* multi-slice control */ 696 /* multi-slice MB number or bit size */ 697 mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL); 698 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 699 mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB); 700 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 701 mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT); 702 } else { 703 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB); 704 mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT); 705 } 706 /* cyclic intra refresh */ 707 mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL); 708 /* memory structure cur. frame */ 709 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) 710 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); 711 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) 712 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); 713 /* padding control & value */ 714 reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL); 715 if (p->pad) { 716 /** enable */ 717 reg |= (1 << 31); 718 /** cr value */ 719 reg &= ~(0xFF << 16); 720 reg |= (p->pad_cr << 16); 721 /** cb value */ 722 reg &= ~(0xFF << 8); 723 reg |= (p->pad_cb << 8); 724 /** y value */ 725 reg &= ~(0xFF); 726 reg |= (p->pad_luma); 727 } else { 728 /** disable & all value clear */ 729 reg = 0; 730 } 731 mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL); 732 /* rate control config. */ 733 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 734 /** frame-level rate control */ 735 reg &= ~(0x1 << 9); 736 reg |= (p->rc_frame << 9); 737 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 738 /* bit rate */ 739 if (p->rc_frame) 740 mfc_write(dev, p->rc_bitrate, 741 S5P_FIMV_ENC_RC_BIT_RATE); 742 else 743 mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE); 744 /* reaction coefficient */ 745 if (p->rc_frame) 746 mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA); 747 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 748 /* seq header ctrl */ 749 shm &= ~(0x1 << 3); 750 shm |= (p->seq_hdr_mode << 3); 751 /* frame skip mode */ 752 shm &= ~(0x3 << 1); 753 shm |= (p->frame_skip_mode << 1); 754 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 755 /* fixed target bit */ 756 s5p_mfc_write_info_v5(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG); 757 return 0; 758} 759 760static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) 761{ 762 struct s5p_mfc_dev *dev = ctx->dev; 763 struct s5p_mfc_enc_params *p = &ctx->enc_params; 764 struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264; 765 unsigned int reg; 766 unsigned int shm; 767 768 s5p_mfc_set_enc_params(ctx); 769 /* pictype : number of B */ 770 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); 771 /* num_b_frame - 0 ~ 2 */ 772 reg &= ~(0x3 << 16); 773 reg |= (p->num_b_frame << 16); 774 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); 775 /* profile & level */ 776 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); 777 /* level */ 778 reg &= ~(0xFF << 8); 779 reg |= (p_264->level << 8); 780 /* profile - 0 ~ 2 */ 781 reg &= ~(0x3F); 782 reg |= p_264->profile; 783 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); 784 /* interlace */ 785 mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT); 786 /* height */ 787 if (p_264->interlace) 788 mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX); 789 /* loopfilter ctrl */ 790 mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL); 791 /* loopfilter alpha offset */ 792 if (p_264->loop_filter_alpha < 0) { 793 reg = 0x10; 794 reg |= (0xFF - p_264->loop_filter_alpha) + 1; 795 } else { 796 reg = 0x00; 797 reg |= (p_264->loop_filter_alpha & 0xF); 798 } 799 mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF); 800 /* loopfilter beta offset */ 801 if (p_264->loop_filter_beta < 0) { 802 reg = 0x10; 803 reg |= (0xFF - p_264->loop_filter_beta) + 1; 804 } else { 805 reg = 0x00; 806 reg |= (p_264->loop_filter_beta & 0xF); 807 } 808 mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF); 809 /* entropy coding mode */ 810 if (p_264->entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) 811 mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE); 812 else 813 mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE); 814 /* number of ref. picture */ 815 reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF); 816 /* num of ref. pictures of P */ 817 reg &= ~(0x3 << 5); 818 reg |= (p_264->num_ref_pic_4p << 5); 819 /* max number of ref. pictures */ 820 reg &= ~(0x1F); 821 reg |= p_264->max_ref_pic; 822 mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF); 823 /* 8x8 transform enable */ 824 mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG); 825 /* rate control config. */ 826 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 827 /* macroblock level rate control */ 828 reg &= ~(0x1 << 8); 829 reg |= (p->rc_mb << 8); 830 /* frame QP */ 831 reg &= ~(0x3F); 832 reg |= p_264->rc_frame_qp; 833 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 834 /* frame rate */ 835 if (p->rc_frame && p->rc_framerate_denom) 836 mfc_write(dev, p->rc_framerate_num * 1000 837 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); 838 else 839 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); 840 /* max & min value of QP */ 841 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); 842 /* max QP */ 843 reg &= ~(0x3F << 8); 844 reg |= (p_264->rc_max_qp << 8); 845 /* min QP */ 846 reg &= ~(0x3F); 847 reg |= p_264->rc_min_qp; 848 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); 849 /* macroblock adaptive scaling features */ 850 if (p->rc_mb) { 851 reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL); 852 /* dark region */ 853 reg &= ~(0x1 << 3); 854 reg |= (p_264->rc_mb_dark << 3); 855 /* smooth region */ 856 reg &= ~(0x1 << 2); 857 reg |= (p_264->rc_mb_smooth << 2); 858 /* static region */ 859 reg &= ~(0x1 << 1); 860 reg |= (p_264->rc_mb_static << 1); 861 /* high activity region */ 862 reg &= ~(0x1); 863 reg |= p_264->rc_mb_activity; 864 mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL); 865 } 866 if (!p->rc_frame && !p->rc_mb) { 867 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); 868 shm &= ~(0xFFF); 869 shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6); 870 shm |= (p_264->rc_p_frame_qp & 0x3F); 871 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); 872 } 873 /* extended encoder ctrl */ 874 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 875 /* AR VUI control */ 876 shm &= ~(0x1 << 15); 877 shm |= (p_264->vui_sar << 1); 878 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 879 if (p_264->vui_sar) { 880 /* aspect ration IDC */ 881 shm = s5p_mfc_read_info_v5(ctx, SAMPLE_ASPECT_RATIO_IDC); 882 shm &= ~(0xFF); 883 shm |= p_264->vui_sar_idc; 884 s5p_mfc_write_info_v5(ctx, shm, SAMPLE_ASPECT_RATIO_IDC); 885 if (p_264->vui_sar_idc == 0xFF) { 886 /* sample AR info */ 887 shm = s5p_mfc_read_info_v5(ctx, EXTENDED_SAR); 888 shm &= ~(0xFFFFFFFF); 889 shm |= p_264->vui_ext_sar_width << 16; 890 shm |= p_264->vui_ext_sar_height; 891 s5p_mfc_write_info_v5(ctx, shm, EXTENDED_SAR); 892 } 893 } 894 /* intra picture period for H.264 */ 895 shm = s5p_mfc_read_info_v5(ctx, H264_I_PERIOD); 896 /* control */ 897 shm &= ~(0x1 << 16); 898 shm |= (p_264->open_gop << 16); 899 /* value */ 900 if (p_264->open_gop) { 901 shm &= ~(0xFFFF); 902 shm |= p_264->open_gop_size; 903 } 904 s5p_mfc_write_info_v5(ctx, shm, H264_I_PERIOD); 905 /* extended encoder ctrl */ 906 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 907 /* vbv buffer size */ 908 if (p->frame_skip_mode == 909 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 910 shm &= ~(0xFFFF << 16); 911 shm |= (p_264->cpb_size << 16); 912 } 913 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 914 return 0; 915} 916 917static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) 918{ 919 struct s5p_mfc_dev *dev = ctx->dev; 920 struct s5p_mfc_enc_params *p = &ctx->enc_params; 921 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; 922 unsigned int reg; 923 unsigned int shm; 924 unsigned int framerate; 925 926 s5p_mfc_set_enc_params(ctx); 927 /* pictype : number of B */ 928 reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); 929 /* num_b_frame - 0 ~ 2 */ 930 reg &= ~(0x3 << 16); 931 reg |= (p->num_b_frame << 16); 932 mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); 933 /* profile & level */ 934 reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); 935 /* level */ 936 reg &= ~(0xFF << 8); 937 reg |= (p_mpeg4->level << 8); 938 /* profile - 0 ~ 2 */ 939 reg &= ~(0x3F); 940 reg |= p_mpeg4->profile; 941 mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); 942 /* quarter_pixel */ 943 mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL); 944 /* qp */ 945 if (!p->rc_frame) { 946 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); 947 shm &= ~(0xFFF); 948 shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6); 949 shm |= (p_mpeg4->rc_p_frame_qp & 0x3F); 950 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); 951 } 952 /* frame rate */ 953 if (p->rc_frame) { 954 if (p->rc_framerate_denom > 0) { 955 framerate = p->rc_framerate_num * 1000 / 956 p->rc_framerate_denom; 957 mfc_write(dev, framerate, 958 S5P_FIMV_ENC_RC_FRAME_RATE); 959 shm = s5p_mfc_read_info_v5(ctx, RC_VOP_TIMING); 960 shm &= ~(0xFFFFFFFF); 961 shm |= (1 << 31); 962 shm |= ((p->rc_framerate_num & 0x7FFF) << 16); 963 shm |= (p->rc_framerate_denom & 0xFFFF); 964 s5p_mfc_write_info_v5(ctx, shm, RC_VOP_TIMING); 965 } 966 } else { 967 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); 968 } 969 /* rate control config. */ 970 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 971 /* frame QP */ 972 reg &= ~(0x3F); 973 reg |= p_mpeg4->rc_frame_qp; 974 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 975 /* max & min value of QP */ 976 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); 977 /* max QP */ 978 reg &= ~(0x3F << 8); 979 reg |= (p_mpeg4->rc_max_qp << 8); 980 /* min QP */ 981 reg &= ~(0x3F); 982 reg |= p_mpeg4->rc_min_qp; 983 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); 984 /* extended encoder ctrl */ 985 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 986 /* vbv buffer size */ 987 if (p->frame_skip_mode == 988 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 989 shm &= ~(0xFFFF << 16); 990 shm |= (p->vbv_size << 16); 991 } 992 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 993 return 0; 994} 995 996static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) 997{ 998 struct s5p_mfc_dev *dev = ctx->dev; 999 struct s5p_mfc_enc_params *p = &ctx->enc_params; 1000 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; 1001 unsigned int reg; 1002 unsigned int shm; 1003 1004 s5p_mfc_set_enc_params(ctx); 1005 /* qp */ 1006 if (!p->rc_frame) { 1007 shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); 1008 shm &= ~(0xFFF); 1009 shm |= (p_h263->rc_p_frame_qp & 0x3F); 1010 s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); 1011 } 1012 /* frame rate */ 1013 if (p->rc_frame && p->rc_framerate_denom) 1014 mfc_write(dev, p->rc_framerate_num * 1000 1015 / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); 1016 else 1017 mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); 1018 /* rate control config. */ 1019 reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); 1020 /* frame QP */ 1021 reg &= ~(0x3F); 1022 reg |= p_h263->rc_frame_qp; 1023 mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); 1024 /* max & min value of QP */ 1025 reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); 1026 /* max QP */ 1027 reg &= ~(0x3F << 8); 1028 reg |= (p_h263->rc_max_qp << 8); 1029 /* min QP */ 1030 reg &= ~(0x3F); 1031 reg |= p_h263->rc_min_qp; 1032 mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); 1033 /* extended encoder ctrl */ 1034 shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); 1035 /* vbv buffer size */ 1036 if (p->frame_skip_mode == 1037 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1038 shm &= ~(0xFFFF << 16); 1039 shm |= (p->vbv_size << 16); 1040 } 1041 s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); 1042 return 0; 1043} 1044 1045/* Initialize decoding */ 1046static int s5p_mfc_init_decode_v5(struct s5p_mfc_ctx *ctx) 1047{ 1048 struct s5p_mfc_dev *dev = ctx->dev; 1049 1050 s5p_mfc_set_shared_buffer(ctx); 1051 /* Setup loop filter, for decoding this is only valid for MPEG4 */ 1052 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) 1053 mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL); 1054 else 1055 mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL); 1056 mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) << 1057 S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable << 1058 S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay & 1059 S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT), 1060 S5P_FIMV_SI_CH0_DPB_CONF_CTRL); 1061 mfc_write(dev, 1062 ((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) 1063 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1064 return 0; 1065} 1066 1067static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) 1068{ 1069 struct s5p_mfc_dev *dev = ctx->dev; 1070 unsigned int dpb; 1071 1072 if (flush) 1073 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | ( 1074 S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); 1075 else 1076 dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & 1077 ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); 1078 mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL); 1079} 1080 1081/* Decode a single frame */ 1082static int s5p_mfc_decode_one_frame_v5(struct s5p_mfc_ctx *ctx, 1083 enum s5p_mfc_decode_arg last_frame) 1084{ 1085 struct s5p_mfc_dev *dev = ctx->dev; 1086 1087 mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF); 1088 s5p_mfc_set_shared_buffer(ctx); 1089 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag); 1090 /* Issue different commands to instance basing on whether it 1091 * is the last frame or not. */ 1092 switch (last_frame) { 1093 case MFC_DEC_FRAME: 1094 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) << 1095 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1096 break; 1097 case MFC_DEC_LAST_FRAME: 1098 mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) << 1099 S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1100 break; 1101 case MFC_DEC_RES_CHANGE: 1102 mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC & 1103 S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), 1104 S5P_FIMV_SI_CH0_INST_ID); 1105 break; 1106 } 1107 mfc_debug(2, "Decoding a usual frame\n"); 1108 return 0; 1109} 1110 1111static int s5p_mfc_init_encode_v5(struct s5p_mfc_ctx *ctx) 1112{ 1113 struct s5p_mfc_dev *dev = ctx->dev; 1114 1115 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) 1116 s5p_mfc_set_enc_params_h264(ctx); 1117 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC) 1118 s5p_mfc_set_enc_params_mpeg4(ctx); 1119 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC) 1120 s5p_mfc_set_enc_params_h263(ctx); 1121 else { 1122 mfc_err("Unknown codec for encoding (%x)\n", 1123 ctx->codec_mode); 1124 return -EINVAL; 1125 } 1126 s5p_mfc_set_shared_buffer(ctx); 1127 mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) | 1128 (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1129 return 0; 1130} 1131 1132/* Encode a single frame */ 1133static int s5p_mfc_encode_one_frame_v5(struct s5p_mfc_ctx *ctx) 1134{ 1135 struct s5p_mfc_dev *dev = ctx->dev; 1136 int cmd; 1137 /* memory structure cur. frame */ 1138 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) 1139 mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); 1140 else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) 1141 mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); 1142 s5p_mfc_set_shared_buffer(ctx); 1143 1144 if (ctx->state == MFCINST_FINISHING) 1145 cmd = S5P_FIMV_CH_LAST_FRAME; 1146 else 1147 cmd = S5P_FIMV_CH_FRAME_START; 1148 mfc_write(dev, ((cmd & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) 1149 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); 1150 1151 return 0; 1152} 1153 1154static int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) 1155{ 1156 unsigned long flags; 1157 int new_ctx; 1158 int cnt; 1159 1160 spin_lock_irqsave(&dev->condlock, flags); 1161 new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS; 1162 cnt = 0; 1163 while (!test_bit(new_ctx, &dev->ctx_work_bits)) { 1164 new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS; 1165 if (++cnt > MFC_NUM_CONTEXTS) { 1166 /* No contexts to run */ 1167 spin_unlock_irqrestore(&dev->condlock, flags); 1168 return -EAGAIN; 1169 } 1170 } 1171 spin_unlock_irqrestore(&dev->condlock, flags); 1172 return new_ctx; 1173} 1174 1175static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx) 1176{ 1177 struct s5p_mfc_dev *dev = ctx->dev; 1178 1179 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); 1180 dev->curr_ctx = ctx->num; 1181 s5p_mfc_decode_one_frame_v5(ctx, MFC_DEC_RES_CHANGE); 1182} 1183 1184static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame) 1185{ 1186 struct s5p_mfc_dev *dev = ctx->dev; 1187 struct s5p_mfc_buf *temp_vb; 1188 unsigned long flags; 1189 1190 if (ctx->state == MFCINST_FINISHING) { 1191 last_frame = MFC_DEC_LAST_FRAME; 1192 s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); 1193 dev->curr_ctx = ctx->num; 1194 s5p_mfc_decode_one_frame_v5(ctx, last_frame); 1195 return 0; 1196 } 1197 1198 spin_lock_irqsave(&dev->irqlock, flags); 1199 /* Frames are being decoded */ 1200 if (list_empty(&ctx->src_queue)) { 1201 mfc_debug(2, "No src buffers\n"); 1202 spin_unlock_irqrestore(&dev->irqlock, flags); 1203 return -EAGAIN; 1204 } 1205 /* Get the next source buffer */ 1206 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1207 temp_vb->flags |= MFC_BUF_FLAG_USED; 1208 s5p_mfc_set_dec_stream_buffer_v5(ctx, 1209 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 1210 ctx->consumed_stream, temp_vb->b->v4l2_planes[0].bytesused); 1211 spin_unlock_irqrestore(&dev->irqlock, flags); 1212 dev->curr_ctx = ctx->num; 1213 if (temp_vb->b->v4l2_planes[0].bytesused == 0) { 1214 last_frame = MFC_DEC_LAST_FRAME; 1215 mfc_debug(2, "Setting ctx->state to FINISHING\n"); 1216 ctx->state = MFCINST_FINISHING; 1217 } 1218 s5p_mfc_decode_one_frame_v5(ctx, last_frame); 1219 return 0; 1220} 1221 1222static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) 1223{ 1224 struct s5p_mfc_dev *dev = ctx->dev; 1225 unsigned long flags; 1226 struct s5p_mfc_buf *dst_mb; 1227 struct s5p_mfc_buf *src_mb; 1228 unsigned long src_y_addr, src_c_addr, dst_addr; 1229 unsigned int dst_size; 1230 1231 spin_lock_irqsave(&dev->irqlock, flags); 1232 if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) { 1233 mfc_debug(2, "no src buffers\n"); 1234 spin_unlock_irqrestore(&dev->irqlock, flags); 1235 return -EAGAIN; 1236 } 1237 if (list_empty(&ctx->dst_queue)) { 1238 mfc_debug(2, "no dst buffers\n"); 1239 spin_unlock_irqrestore(&dev->irqlock, flags); 1240 return -EAGAIN; 1241 } 1242 if (list_empty(&ctx->src_queue)) { 1243 /* send null frame */ 1244 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, dev->bank2); 1245 src_mb = NULL; 1246 } else { 1247 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, 1248 list); 1249 src_mb->flags |= MFC_BUF_FLAG_USED; 1250 if (src_mb->b->v4l2_planes[0].bytesused == 0) { 1251 /* send null frame */ 1252 s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, 1253 dev->bank2); 1254 ctx->state = MFCINST_FINISHING; 1255 } else { 1256 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1257 0); 1258 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1259 1); 1260 s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr, 1261 src_c_addr); 1262 if (src_mb->flags & MFC_BUF_FLAG_EOS) 1263 ctx->state = MFCINST_FINISHING; 1264 } 1265 } 1266 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 1267 dst_mb->flags |= MFC_BUF_FLAG_USED; 1268 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 1269 dst_size = vb2_plane_size(dst_mb->b, 0); 1270 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); 1271 spin_unlock_irqrestore(&dev->irqlock, flags); 1272 dev->curr_ctx = ctx->num; 1273 mfc_debug(2, "encoding buffer with index=%d state=%d\n", 1274 src_mb ? src_mb->b->v4l2_buf.index : -1, ctx->state); 1275 s5p_mfc_encode_one_frame_v5(ctx); 1276 return 0; 1277} 1278 1279static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx) 1280{ 1281 struct s5p_mfc_dev *dev = ctx->dev; 1282 unsigned long flags; 1283 struct s5p_mfc_buf *temp_vb; 1284 1285 /* Initializing decoding - parsing header */ 1286 spin_lock_irqsave(&dev->irqlock, flags); 1287 mfc_debug(2, "Preparing to init decoding\n"); 1288 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1289 s5p_mfc_set_dec_desc_buffer(ctx); 1290 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); 1291 s5p_mfc_set_dec_stream_buffer_v5(ctx, 1292 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 1293 0, temp_vb->b->v4l2_planes[0].bytesused); 1294 spin_unlock_irqrestore(&dev->irqlock, flags); 1295 dev->curr_ctx = ctx->num; 1296 s5p_mfc_init_decode_v5(ctx); 1297} 1298 1299static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx) 1300{ 1301 struct s5p_mfc_dev *dev = ctx->dev; 1302 unsigned long flags; 1303 struct s5p_mfc_buf *dst_mb; 1304 unsigned long dst_addr; 1305 unsigned int dst_size; 1306 1307 s5p_mfc_set_enc_ref_buffer_v5(ctx); 1308 spin_lock_irqsave(&dev->irqlock, flags); 1309 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 1310 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 1311 dst_size = vb2_plane_size(dst_mb->b, 0); 1312 s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); 1313 spin_unlock_irqrestore(&dev->irqlock, flags); 1314 dev->curr_ctx = ctx->num; 1315 s5p_mfc_init_encode_v5(ctx); 1316} 1317 1318static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx) 1319{ 1320 struct s5p_mfc_dev *dev = ctx->dev; 1321 unsigned long flags; 1322 struct s5p_mfc_buf *temp_vb; 1323 int ret; 1324 1325 /* 1326 * Header was parsed now starting processing 1327 * First set the output frame buffers 1328 */ 1329 if (ctx->capture_state != QUEUE_BUFS_MMAPED) { 1330 mfc_err("It seems that not all destionation buffers were " 1331 "mmaped\nMFC requires that all destination are mmaped " 1332 "before starting processing\n"); 1333 return -EAGAIN; 1334 } 1335 spin_lock_irqsave(&dev->irqlock, flags); 1336 if (list_empty(&ctx->src_queue)) { 1337 mfc_err("Header has been deallocated in the middle of" 1338 " initialization\n"); 1339 spin_unlock_irqrestore(&dev->irqlock, flags); 1340 return -EIO; 1341 } 1342 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 1343 mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); 1344 s5p_mfc_set_dec_stream_buffer_v5(ctx, 1345 vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), 1346 0, temp_vb->b->v4l2_planes[0].bytesused); 1347 spin_unlock_irqrestore(&dev->irqlock, flags); 1348 dev->curr_ctx = ctx->num; 1349 ret = s5p_mfc_set_dec_frame_buffer_v5(ctx); 1350 if (ret) { 1351 mfc_err("Failed to alloc frame mem\n"); 1352 ctx->state = MFCINST_ERROR; 1353 } 1354 return ret; 1355} 1356 1357/* Try running an operation on hardware */ 1358static void s5p_mfc_try_run_v5(struct s5p_mfc_dev *dev) 1359{ 1360 struct s5p_mfc_ctx *ctx; 1361 int new_ctx; 1362 unsigned int ret = 0; 1363 1364 if (test_bit(0, &dev->enter_suspend)) { 1365 mfc_debug(1, "Entering suspend so do not schedule any jobs\n"); 1366 return; 1367 } 1368 /* Check whether hardware is not running */ 1369 if (test_and_set_bit(0, &dev->hw_lock) != 0) { 1370 /* This is perfectly ok, the scheduled ctx should wait */ 1371 mfc_debug(1, "Couldn't lock HW\n"); 1372 return; 1373 } 1374 /* Choose the context to run */ 1375 new_ctx = s5p_mfc_get_new_ctx(dev); 1376 if (new_ctx < 0) { 1377 /* No contexts to run */ 1378 if (test_and_clear_bit(0, &dev->hw_lock) == 0) { 1379 mfc_err("Failed to unlock hardware\n"); 1380 return; 1381 } 1382 mfc_debug(1, "No ctx is scheduled to be run\n"); 1383 return; 1384 } 1385 ctx = dev->ctx[new_ctx]; 1386 /* Got context to run in ctx */ 1387 /* 1388 * Last frame has already been sent to MFC. 1389 * Now obtaining frames from MFC buffer 1390 */ 1391 s5p_mfc_clock_on(); 1392 s5p_mfc_clean_ctx_int_flags(ctx); 1393 1394 if (ctx->type == MFCINST_DECODER) { 1395 s5p_mfc_set_dec_desc_buffer(ctx); 1396 switch (ctx->state) { 1397 case MFCINST_FINISHING: 1398 s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME); 1399 break; 1400 case MFCINST_RUNNING: 1401 ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); 1402 break; 1403 case MFCINST_INIT: 1404 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, 1405 ctx); 1406 break; 1407 case MFCINST_RETURN_INST: 1408 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, 1409 ctx); 1410 break; 1411 case MFCINST_GOT_INST: 1412 s5p_mfc_run_init_dec(ctx); 1413 break; 1414 case MFCINST_HEAD_PARSED: 1415 ret = s5p_mfc_run_init_dec_buffers(ctx); 1416 mfc_debug(1, "head parsed\n"); 1417 break; 1418 case MFCINST_RES_CHANGE_INIT: 1419 s5p_mfc_run_res_change(ctx); 1420 break; 1421 case MFCINST_RES_CHANGE_FLUSH: 1422 s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); 1423 break; 1424 case MFCINST_RES_CHANGE_END: 1425 mfc_debug(2, "Finished remaining frames after resolution change\n"); 1426 ctx->capture_state = QUEUE_FREE; 1427 mfc_debug(2, "Will re-init the codec\n"); 1428 s5p_mfc_run_init_dec(ctx); 1429 break; 1430 default: 1431 ret = -EAGAIN; 1432 } 1433 } else if (ctx->type == MFCINST_ENCODER) { 1434 switch (ctx->state) { 1435 case MFCINST_FINISHING: 1436 case MFCINST_RUNNING: 1437 ret = s5p_mfc_run_enc_frame(ctx); 1438 break; 1439 case MFCINST_INIT: 1440 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, 1441 ctx); 1442 break; 1443 case MFCINST_RETURN_INST: 1444 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, 1445 ctx); 1446 break; 1447 case MFCINST_GOT_INST: 1448 s5p_mfc_run_init_enc(ctx); 1449 break; 1450 default: 1451 ret = -EAGAIN; 1452 } 1453 } else { 1454 mfc_err("Invalid context type: %d\n", ctx->type); 1455 ret = -EAGAIN; 1456 } 1457 1458 if (ret) { 1459 /* Free hardware lock */ 1460 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 1461 mfc_err("Failed to unlock hardware\n"); 1462 1463 /* This is in deed imporant, as no operation has been 1464 * scheduled, reduce the clock count as no one will 1465 * ever do this, because no interrupt related to this try_run 1466 * will ever come from hardware. */ 1467 s5p_mfc_clock_off(); 1468 } 1469} 1470 1471 1472static void s5p_mfc_cleanup_queue_v5(struct list_head *lh, struct vb2_queue *vq) 1473{ 1474 struct s5p_mfc_buf *b; 1475 int i; 1476 1477 while (!list_empty(lh)) { 1478 b = list_entry(lh->next, struct s5p_mfc_buf, list); 1479 for (i = 0; i < b->b->num_planes; i++) 1480 vb2_set_plane_payload(b->b, i, 0); 1481 vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR); 1482 list_del(&b->list); 1483 } 1484} 1485 1486static void s5p_mfc_clear_int_flags_v5(struct s5p_mfc_dev *dev) 1487{ 1488 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); 1489 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); 1490 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); 1491} 1492 1493static int s5p_mfc_get_dspl_y_adr_v5(struct s5p_mfc_dev *dev) 1494{ 1495 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_Y_ADR) << MFC_OFFSET_SHIFT; 1496} 1497 1498static int s5p_mfc_get_dec_y_adr_v5(struct s5p_mfc_dev *dev) 1499{ 1500 return mfc_read(dev, S5P_FIMV_SI_DECODE_Y_ADR) << MFC_OFFSET_SHIFT; 1501} 1502 1503static int s5p_mfc_get_dspl_status_v5(struct s5p_mfc_dev *dev) 1504{ 1505 return mfc_read(dev, S5P_FIMV_SI_DISPLAY_STATUS); 1506} 1507 1508static int s5p_mfc_get_dec_status_v5(struct s5p_mfc_dev *dev) 1509{ 1510 return mfc_read(dev, S5P_FIMV_SI_DECODE_STATUS); 1511} 1512 1513static int s5p_mfc_get_dec_frame_type_v5(struct s5p_mfc_dev *dev) 1514{ 1515 return mfc_read(dev, S5P_FIMV_DECODE_FRAME_TYPE) & 1516 S5P_FIMV_DECODE_FRAME_MASK; 1517} 1518 1519static int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx) 1520{ 1521 return (s5p_mfc_read_info_v5(ctx, DISP_PIC_FRAME_TYPE) >> 1522 S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) & 1523 S5P_FIMV_DECODE_FRAME_MASK; 1524} 1525 1526static int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev) 1527{ 1528 return mfc_read(dev, S5P_FIMV_SI_CONSUMED_BYTES); 1529} 1530 1531static int s5p_mfc_get_int_reason_v5(struct s5p_mfc_dev *dev) 1532{ 1533 int reason; 1534 reason = mfc_read(dev, S5P_FIMV_RISC2HOST_CMD) & 1535 S5P_FIMV_RISC2HOST_CMD_MASK; 1536 switch (reason) { 1537 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET: 1538 reason = S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET; 1539 break; 1540 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET: 1541 reason = S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET; 1542 break; 1543 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET: 1544 reason = S5P_MFC_R2H_CMD_SEQ_DONE_RET; 1545 break; 1546 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET: 1547 reason = S5P_MFC_R2H_CMD_FRAME_DONE_RET; 1548 break; 1549 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET: 1550 reason = S5P_MFC_R2H_CMD_SLICE_DONE_RET; 1551 break; 1552 case S5P_FIMV_R2H_CMD_SYS_INIT_RET: 1553 reason = S5P_MFC_R2H_CMD_SYS_INIT_RET; 1554 break; 1555 case S5P_FIMV_R2H_CMD_FW_STATUS_RET: 1556 reason = S5P_MFC_R2H_CMD_FW_STATUS_RET; 1557 break; 1558 case S5P_FIMV_R2H_CMD_SLEEP_RET: 1559 reason = S5P_MFC_R2H_CMD_SLEEP_RET; 1560 break; 1561 case S5P_FIMV_R2H_CMD_WAKEUP_RET: 1562 reason = S5P_MFC_R2H_CMD_WAKEUP_RET; 1563 break; 1564 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET: 1565 reason = S5P_MFC_R2H_CMD_INIT_BUFFERS_RET; 1566 break; 1567 case S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET: 1568 reason = S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET; 1569 break; 1570 case S5P_FIMV_R2H_CMD_ERR_RET: 1571 reason = S5P_MFC_R2H_CMD_ERR_RET; 1572 break; 1573 default: 1574 reason = S5P_MFC_R2H_CMD_EMPTY; 1575 } 1576 return reason; 1577} 1578 1579static int s5p_mfc_get_int_err_v5(struct s5p_mfc_dev *dev) 1580{ 1581 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG2); 1582} 1583 1584static int s5p_mfc_err_dec_v5(unsigned int err) 1585{ 1586 return (err & S5P_FIMV_ERR_DEC_MASK) >> S5P_FIMV_ERR_DEC_SHIFT; 1587} 1588 1589static int s5p_mfc_err_dspl_v5(unsigned int err) 1590{ 1591 return (err & S5P_FIMV_ERR_DSPL_MASK) >> S5P_FIMV_ERR_DSPL_SHIFT; 1592} 1593 1594static int s5p_mfc_get_img_width_v5(struct s5p_mfc_dev *dev) 1595{ 1596 return mfc_read(dev, S5P_FIMV_SI_HRESOL); 1597} 1598 1599static int s5p_mfc_get_img_height_v5(struct s5p_mfc_dev *dev) 1600{ 1601 return mfc_read(dev, S5P_FIMV_SI_VRESOL); 1602} 1603 1604static int s5p_mfc_get_dpb_count_v5(struct s5p_mfc_dev *dev) 1605{ 1606 return mfc_read(dev, S5P_FIMV_SI_BUF_NUMBER); 1607} 1608 1609static int s5p_mfc_get_mv_count_v5(struct s5p_mfc_dev *dev) 1610{ 1611 /* NOP */ 1612 return -1; 1613} 1614 1615static int s5p_mfc_get_inst_no_v5(struct s5p_mfc_dev *dev) 1616{ 1617 return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG1); 1618} 1619 1620static int s5p_mfc_get_enc_strm_size_v5(struct s5p_mfc_dev *dev) 1621{ 1622 return mfc_read(dev, S5P_FIMV_ENC_SI_STRM_SIZE); 1623} 1624 1625static int s5p_mfc_get_enc_slice_type_v5(struct s5p_mfc_dev *dev) 1626{ 1627 return mfc_read(dev, S5P_FIMV_ENC_SI_SLICE_TYPE); 1628} 1629 1630static int s5p_mfc_get_enc_dpb_count_v5(struct s5p_mfc_dev *dev) 1631{ 1632 return -1; 1633} 1634 1635static int s5p_mfc_get_enc_pic_count_v5(struct s5p_mfc_dev *dev) 1636{ 1637 return mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT); 1638} 1639 1640static int s5p_mfc_get_sei_avail_status_v5(struct s5p_mfc_ctx *ctx) 1641{ 1642 return s5p_mfc_read_info_v5(ctx, FRAME_PACK_SEI_AVAIL); 1643} 1644 1645static int s5p_mfc_get_mvc_num_views_v5(struct s5p_mfc_dev *dev) 1646{ 1647 return -1; 1648} 1649 1650static int s5p_mfc_get_mvc_view_id_v5(struct s5p_mfc_dev *dev) 1651{ 1652 return -1; 1653} 1654 1655static unsigned int s5p_mfc_get_pic_type_top_v5(struct s5p_mfc_ctx *ctx) 1656{ 1657 return s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP); 1658} 1659 1660static unsigned int s5p_mfc_get_pic_type_bot_v5(struct s5p_mfc_ctx *ctx) 1661{ 1662 return s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT); 1663} 1664 1665static unsigned int s5p_mfc_get_crop_info_h_v5(struct s5p_mfc_ctx *ctx) 1666{ 1667 return s5p_mfc_read_info_v5(ctx, CROP_INFO_H); 1668} 1669 1670static unsigned int s5p_mfc_get_crop_info_v_v5(struct s5p_mfc_ctx *ctx) 1671{ 1672 return s5p_mfc_read_info_v5(ctx, CROP_INFO_V); 1673} 1674 1675/* Initialize opr function pointers for MFC v5 */ 1676static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = { 1677 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v5, 1678 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v5, 1679 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v5, 1680 .release_codec_buffers = s5p_mfc_release_codec_buffers_v5, 1681 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v5, 1682 .release_instance_buffer = s5p_mfc_release_instance_buffer_v5, 1683 .alloc_dev_context_buffer = s5p_mfc_alloc_dev_context_buffer_v5, 1684 .release_dev_context_buffer = s5p_mfc_release_dev_context_buffer_v5, 1685 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v5, 1686 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v5, 1687 .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v5, 1688 .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v5, 1689 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v5, 1690 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v5, 1691 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v5, 1692 .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v5, 1693 .init_decode = s5p_mfc_init_decode_v5, 1694 .init_encode = s5p_mfc_init_encode_v5, 1695 .encode_one_frame = s5p_mfc_encode_one_frame_v5, 1696 .try_run = s5p_mfc_try_run_v5, 1697 .cleanup_queue = s5p_mfc_cleanup_queue_v5, 1698 .clear_int_flags = s5p_mfc_clear_int_flags_v5, 1699 .write_info = s5p_mfc_write_info_v5, 1700 .read_info = s5p_mfc_read_info_v5, 1701 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v5, 1702 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v5, 1703 .get_dspl_status = s5p_mfc_get_dspl_status_v5, 1704 .get_dec_status = s5p_mfc_get_dec_status_v5, 1705 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v5, 1706 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v5, 1707 .get_consumed_stream = s5p_mfc_get_consumed_stream_v5, 1708 .get_int_reason = s5p_mfc_get_int_reason_v5, 1709 .get_int_err = s5p_mfc_get_int_err_v5, 1710 .err_dec = s5p_mfc_err_dec_v5, 1711 .err_dspl = s5p_mfc_err_dspl_v5, 1712 .get_img_width = s5p_mfc_get_img_width_v5, 1713 .get_img_height = s5p_mfc_get_img_height_v5, 1714 .get_dpb_count = s5p_mfc_get_dpb_count_v5, 1715 .get_mv_count = s5p_mfc_get_mv_count_v5, 1716 .get_inst_no = s5p_mfc_get_inst_no_v5, 1717 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v5, 1718 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v5, 1719 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v5, 1720 .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v5, 1721 .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v5, 1722 .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v5, 1723 .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v5, 1724 .get_pic_type_top = s5p_mfc_get_pic_type_top_v5, 1725 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v5, 1726 .get_crop_info_h = s5p_mfc_get_crop_info_h_v5, 1727 .get_crop_info_v = s5p_mfc_get_crop_info_v_v5, 1728}; 1729 1730struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void) 1731{ 1732 return &s5p_mfc_ops_v5; 1733} 1734