1/* 2 * CARMA Board DATA-FPGA Programmer 3 * 4 * Copyright (c) 2009-2011 Ira W. Snyder <iws@ovro.caltech.edu> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12#include <linux/dma-mapping.h> 13#include <linux/of_address.h> 14#include <linux/of_irq.h> 15#include <linux/of_platform.h> 16#include <linux/completion.h> 17#include <linux/miscdevice.h> 18#include <linux/dmaengine.h> 19#include <linux/fsldma.h> 20#include <linux/interrupt.h> 21#include <linux/highmem.h> 22#include <linux/vmalloc.h> 23#include <linux/kernel.h> 24#include <linux/module.h> 25#include <linux/mutex.h> 26#include <linux/delay.h> 27#include <linux/init.h> 28#include <linux/leds.h> 29#include <linux/slab.h> 30#include <linux/kref.h> 31#include <linux/fs.h> 32#include <linux/io.h> 33 34/* MPC8349EMDS specific get_immrbase() */ 35#include <sysdev/fsl_soc.h> 36 37static const char drv_name[] = "carma-fpga-program"; 38 39/* 40 * Firmware images are always this exact size 41 * 42 * 12849552 bytes for a CARMA Digitizer Board (EP2S90 FPGAs) 43 * 18662880 bytes for a CARMA Correlator Board (EP2S130 FPGAs) 44 */ 45#define FW_SIZE_EP2S90 12849552 46#define FW_SIZE_EP2S130 18662880 47 48struct fpga_dev { 49 struct miscdevice miscdev; 50 51 /* Reference count */ 52 struct kref ref; 53 54 /* Device Registers */ 55 struct device *dev; 56 void __iomem *regs; 57 void __iomem *immr; 58 59 /* Freescale DMA Device */ 60 struct dma_chan *chan; 61 62 /* Interrupts */ 63 int irq, status; 64 struct completion completion; 65 66 /* FPGA Bitfile */ 67 struct mutex lock; 68 69 void *vaddr; 70 struct scatterlist *sglist; 71 int sglen; 72 int nr_pages; 73 bool buf_allocated; 74 75 /* max size and written bytes */ 76 size_t fw_size; 77 size_t bytes; 78}; 79 80static int fpga_dma_init(struct fpga_dev *priv, int nr_pages) 81{ 82 struct page *pg; 83 int i; 84 85 priv->vaddr = vmalloc_32(nr_pages << PAGE_SHIFT); 86 if (NULL == priv->vaddr) { 87 pr_debug("vmalloc_32(%d pages) failed\n", nr_pages); 88 return -ENOMEM; 89 } 90 91 pr_debug("vmalloc is at addr 0x%08lx, size=%d\n", 92 (unsigned long)priv->vaddr, 93 nr_pages << PAGE_SHIFT); 94 95 memset(priv->vaddr, 0, nr_pages << PAGE_SHIFT); 96 priv->nr_pages = nr_pages; 97 98 priv->sglist = vzalloc(priv->nr_pages * sizeof(*priv->sglist)); 99 if (NULL == priv->sglist) 100 goto vzalloc_err; 101 102 sg_init_table(priv->sglist, priv->nr_pages); 103 for (i = 0; i < priv->nr_pages; i++) { 104 pg = vmalloc_to_page(priv->vaddr + i * PAGE_SIZE); 105 if (NULL == pg) 106 goto vmalloc_to_page_err; 107 sg_set_page(&priv->sglist[i], pg, PAGE_SIZE, 0); 108 } 109 return 0; 110 111vmalloc_to_page_err: 112 vfree(priv->sglist); 113 priv->sglist = NULL; 114vzalloc_err: 115 vfree(priv->vaddr); 116 priv->vaddr = NULL; 117 return -ENOMEM; 118} 119 120static int fpga_dma_map(struct fpga_dev *priv) 121{ 122 priv->sglen = dma_map_sg(priv->dev, priv->sglist, 123 priv->nr_pages, DMA_TO_DEVICE); 124 125 if (0 == priv->sglen) { 126 pr_warn("%s: dma_map_sg failed\n", __func__); 127 return -ENOMEM; 128 } 129 return 0; 130} 131 132static int fpga_dma_unmap(struct fpga_dev *priv) 133{ 134 if (!priv->sglen) 135 return 0; 136 137 dma_unmap_sg(priv->dev, priv->sglist, priv->sglen, DMA_TO_DEVICE); 138 priv->sglen = 0; 139 return 0; 140} 141 142/* 143 * FPGA Bitfile Helpers 144 */ 145 146/** 147 * fpga_drop_firmware_data() - drop the bitfile image from memory 148 * @priv: the driver's private data structure 149 * 150 * LOCKING: must hold priv->lock 151 */ 152static void fpga_drop_firmware_data(struct fpga_dev *priv) 153{ 154 vfree(priv->sglist); 155 vfree(priv->vaddr); 156 priv->buf_allocated = false; 157 priv->bytes = 0; 158} 159 160/* 161 * Private Data Reference Count 162 */ 163 164static void fpga_dev_remove(struct kref *ref) 165{ 166 struct fpga_dev *priv = container_of(ref, struct fpga_dev, ref); 167 168 /* free any firmware image that was not programmed */ 169 fpga_drop_firmware_data(priv); 170 171 mutex_destroy(&priv->lock); 172 kfree(priv); 173} 174 175/* 176 * LED Trigger (could be a seperate module) 177 */ 178 179/* 180 * NOTE: this whole thing does have the problem that whenever the led's are 181 * NOTE: first set to use the fpga trigger, they could be in the wrong state 182 */ 183 184DEFINE_LED_TRIGGER(ledtrig_fpga); 185 186static void ledtrig_fpga_programmed(bool enabled) 187{ 188 if (enabled) 189 led_trigger_event(ledtrig_fpga, LED_FULL); 190 else 191 led_trigger_event(ledtrig_fpga, LED_OFF); 192} 193 194/* 195 * FPGA Register Helpers 196 */ 197 198/* Register Definitions */ 199#define FPGA_CONFIG_CONTROL 0x40 200#define FPGA_CONFIG_STATUS 0x44 201#define FPGA_CONFIG_FIFO_SIZE 0x48 202#define FPGA_CONFIG_FIFO_USED 0x4C 203#define FPGA_CONFIG_TOTAL_BYTE_COUNT 0x50 204#define FPGA_CONFIG_CUR_BYTE_COUNT 0x54 205 206#define FPGA_FIFO_ADDRESS 0x3000 207 208static int fpga_fifo_size(void __iomem *regs) 209{ 210 return ioread32be(regs + FPGA_CONFIG_FIFO_SIZE); 211} 212 213#define CFG_STATUS_ERR_MASK 0xfffe 214 215static int fpga_config_error(void __iomem *regs) 216{ 217 return ioread32be(regs + FPGA_CONFIG_STATUS) & CFG_STATUS_ERR_MASK; 218} 219 220static int fpga_fifo_empty(void __iomem *regs) 221{ 222 return ioread32be(regs + FPGA_CONFIG_FIFO_USED) == 0; 223} 224 225static void fpga_fifo_write(void __iomem *regs, u32 val) 226{ 227 iowrite32be(val, regs + FPGA_FIFO_ADDRESS); 228} 229 230static void fpga_set_byte_count(void __iomem *regs, u32 count) 231{ 232 iowrite32be(count, regs + FPGA_CONFIG_TOTAL_BYTE_COUNT); 233} 234 235#define CFG_CTL_ENABLE (1 << 0) 236#define CFG_CTL_RESET (1 << 1) 237#define CFG_CTL_DMA (1 << 2) 238 239static void fpga_programmer_enable(struct fpga_dev *priv, bool dma) 240{ 241 u32 val; 242 243 val = (dma) ? (CFG_CTL_ENABLE | CFG_CTL_DMA) : CFG_CTL_ENABLE; 244 iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL); 245} 246 247static void fpga_programmer_disable(struct fpga_dev *priv) 248{ 249 iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL); 250} 251 252static void fpga_dump_registers(struct fpga_dev *priv) 253{ 254 u32 control, status, size, used, total, curr; 255 256 /* good status: do nothing */ 257 if (priv->status == 0) 258 return; 259 260 /* Dump all status registers */ 261 control = ioread32be(priv->regs + FPGA_CONFIG_CONTROL); 262 status = ioread32be(priv->regs + FPGA_CONFIG_STATUS); 263 size = ioread32be(priv->regs + FPGA_CONFIG_FIFO_SIZE); 264 used = ioread32be(priv->regs + FPGA_CONFIG_FIFO_USED); 265 total = ioread32be(priv->regs + FPGA_CONFIG_TOTAL_BYTE_COUNT); 266 curr = ioread32be(priv->regs + FPGA_CONFIG_CUR_BYTE_COUNT); 267 268 dev_err(priv->dev, "Configuration failed, dumping status registers\n"); 269 dev_err(priv->dev, "Control: 0x%.8x\n", control); 270 dev_err(priv->dev, "Status: 0x%.8x\n", status); 271 dev_err(priv->dev, "FIFO Size: 0x%.8x\n", size); 272 dev_err(priv->dev, "FIFO Used: 0x%.8x\n", used); 273 dev_err(priv->dev, "FIFO Total: 0x%.8x\n", total); 274 dev_err(priv->dev, "FIFO Curr: 0x%.8x\n", curr); 275} 276 277/* 278 * FPGA Power Supply Code 279 */ 280 281#define CTL_PWR_CONTROL 0x2006 282#define CTL_PWR_STATUS 0x200A 283#define CTL_PWR_FAIL 0x200B 284 285#define PWR_CONTROL_ENABLE 0x01 286 287#define PWR_STATUS_ERROR_MASK 0x10 288#define PWR_STATUS_GOOD 0x0f 289 290/* 291 * Determine if the FPGA power is good for all supplies 292 */ 293static bool fpga_power_good(struct fpga_dev *priv) 294{ 295 u8 val; 296 297 val = ioread8(priv->regs + CTL_PWR_STATUS); 298 if (val & PWR_STATUS_ERROR_MASK) 299 return false; 300 301 return val == PWR_STATUS_GOOD; 302} 303 304/* 305 * Disable the FPGA power supplies 306 */ 307static void fpga_disable_power_supplies(struct fpga_dev *priv) 308{ 309 unsigned long start; 310 u8 val; 311 312 iowrite8(0x0, priv->regs + CTL_PWR_CONTROL); 313 314 /* 315 * Wait 500ms for the power rails to discharge 316 * 317 * Without this delay, the CTL-CPLD state machine can get into a 318 * state where it is waiting for the power-goods to assert, but they 319 * never do. This only happens when enabling and disabling the 320 * power sequencer very rapidly. 321 * 322 * The loop below will also wait for the power goods to de-assert, 323 * but testing has shown that they are always disabled by the time 324 * the sleep completes. However, omitting the sleep and only waiting 325 * for the power-goods to de-assert was not sufficient to ensure 326 * that the power sequencer would not wedge itself. 327 */ 328 msleep(500); 329 330 start = jiffies; 331 while (time_before(jiffies, start + HZ)) { 332 val = ioread8(priv->regs + CTL_PWR_STATUS); 333 if (!(val & PWR_STATUS_GOOD)) 334 break; 335 336 usleep_range(5000, 10000); 337 } 338 339 val = ioread8(priv->regs + CTL_PWR_STATUS); 340 if (val & PWR_STATUS_GOOD) { 341 dev_err(priv->dev, "power disable failed: " 342 "power goods: status 0x%.2x\n", val); 343 } 344 345 if (val & PWR_STATUS_ERROR_MASK) { 346 dev_err(priv->dev, "power disable failed: " 347 "alarm bit set: status 0x%.2x\n", val); 348 } 349} 350 351/** 352 * fpga_enable_power_supplies() - enable the DATA-FPGA power supplies 353 * @priv: the driver's private data structure 354 * 355 * Enable the DATA-FPGA power supplies, waiting up to 1 second for 356 * them to enable successfully. 357 * 358 * Returns 0 on success, -ERRNO otherwise 359 */ 360static int fpga_enable_power_supplies(struct fpga_dev *priv) 361{ 362 unsigned long start = jiffies; 363 364 if (fpga_power_good(priv)) { 365 dev_dbg(priv->dev, "power was already good\n"); 366 return 0; 367 } 368 369 iowrite8(PWR_CONTROL_ENABLE, priv->regs + CTL_PWR_CONTROL); 370 while (time_before(jiffies, start + HZ)) { 371 if (fpga_power_good(priv)) 372 return 0; 373 374 usleep_range(5000, 10000); 375 } 376 377 return fpga_power_good(priv) ? 0 : -ETIMEDOUT; 378} 379 380/* 381 * Determine if the FPGA power supplies are all enabled 382 */ 383static bool fpga_power_enabled(struct fpga_dev *priv) 384{ 385 u8 val; 386 387 val = ioread8(priv->regs + CTL_PWR_CONTROL); 388 if (val & PWR_CONTROL_ENABLE) 389 return true; 390 391 return false; 392} 393 394/* 395 * Determine if the FPGA's are programmed and running correctly 396 */ 397static bool fpga_running(struct fpga_dev *priv) 398{ 399 if (!fpga_power_good(priv)) 400 return false; 401 402 /* Check the config done bit */ 403 return ioread32be(priv->regs + FPGA_CONFIG_STATUS) & (1 << 18); 404} 405 406/* 407 * FPGA Programming Code 408 */ 409 410/** 411 * fpga_program_block() - put a block of data into the programmer's FIFO 412 * @priv: the driver's private data structure 413 * @buf: the data to program 414 * @count: the length of data to program (must be a multiple of 4 bytes) 415 * 416 * Returns 0 on success, -ERRNO otherwise 417 */ 418static int fpga_program_block(struct fpga_dev *priv, void *buf, size_t count) 419{ 420 u32 *data = buf; 421 int size = fpga_fifo_size(priv->regs); 422 int i, len; 423 unsigned long timeout; 424 425 /* enforce correct data length for the FIFO */ 426 BUG_ON(count % 4 != 0); 427 428 while (count > 0) { 429 430 /* Get the size of the block to write (maximum is FIFO_SIZE) */ 431 len = min_t(size_t, count, size); 432 timeout = jiffies + HZ / 4; 433 434 /* Write the block */ 435 for (i = 0; i < len / 4; i++) 436 fpga_fifo_write(priv->regs, data[i]); 437 438 /* Update the amounts left */ 439 count -= len; 440 data += len / 4; 441 442 /* Wait for the fifo to empty */ 443 while (true) { 444 445 if (fpga_fifo_empty(priv->regs)) { 446 break; 447 } else { 448 dev_dbg(priv->dev, "Fifo not empty\n"); 449 cpu_relax(); 450 } 451 452 if (fpga_config_error(priv->regs)) { 453 dev_err(priv->dev, "Error detected\n"); 454 return -EIO; 455 } 456 457 if (time_after(jiffies, timeout)) { 458 dev_err(priv->dev, "Fifo drain timeout\n"); 459 return -ETIMEDOUT; 460 } 461 462 usleep_range(5000, 10000); 463 } 464 } 465 466 return 0; 467} 468 469/** 470 * fpga_program_cpu() - program the DATA-FPGA's using the CPU 471 * @priv: the driver's private data structure 472 * 473 * This is useful when the DMA programming method fails. It is possible to 474 * wedge the Freescale DMA controller such that the DMA programming method 475 * always fails. This method has always succeeded. 476 * 477 * Returns 0 on success, -ERRNO otherwise 478 */ 479static noinline int fpga_program_cpu(struct fpga_dev *priv) 480{ 481 int ret; 482 unsigned long timeout; 483 484 /* Disable the programmer */ 485 fpga_programmer_disable(priv); 486 487 /* Set the total byte count */ 488 fpga_set_byte_count(priv->regs, priv->bytes); 489 dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes); 490 491 /* Enable the controller for programming */ 492 fpga_programmer_enable(priv, false); 493 dev_dbg(priv->dev, "enabled the controller\n"); 494 495 /* Write each chunk of the FPGA bitfile to FPGA programmer */ 496 ret = fpga_program_block(priv, priv->vaddr, priv->bytes); 497 if (ret) 498 goto out_disable_controller; 499 500 /* Wait for the interrupt handler to signal that programming finished */ 501 timeout = wait_for_completion_timeout(&priv->completion, 2 * HZ); 502 if (!timeout) { 503 dev_err(priv->dev, "Timed out waiting for completion\n"); 504 ret = -ETIMEDOUT; 505 goto out_disable_controller; 506 } 507 508 /* Retrieve the status from the interrupt handler */ 509 ret = priv->status; 510 511out_disable_controller: 512 fpga_programmer_disable(priv); 513 return ret; 514} 515 516#define FIFO_DMA_ADDRESS 0xf0003000 517#define FIFO_MAX_LEN 4096 518 519/** 520 * fpga_program_dma() - program the DATA-FPGA's using the DMA engine 521 * @priv: the driver's private data structure 522 * 523 * Program the DATA-FPGA's using the Freescale DMA engine. This requires that 524 * the engine is programmed such that the hardware DMA request lines can 525 * control the entire DMA transaction. The system controller FPGA then 526 * completely offloads the programming from the CPU. 527 * 528 * Returns 0 on success, -ERRNO otherwise 529 */ 530static noinline int fpga_program_dma(struct fpga_dev *priv) 531{ 532 struct dma_chan *chan = priv->chan; 533 struct dma_async_tx_descriptor *tx; 534 size_t num_pages, len, avail = 0; 535 struct dma_slave_config config; 536 struct scatterlist *sg; 537 struct sg_table table; 538 dma_cookie_t cookie; 539 int ret, i; 540 unsigned long timeout; 541 542 /* Disable the programmer */ 543 fpga_programmer_disable(priv); 544 545 /* Allocate a scatterlist for the DMA destination */ 546 num_pages = DIV_ROUND_UP(priv->bytes, FIFO_MAX_LEN); 547 ret = sg_alloc_table(&table, num_pages, GFP_KERNEL); 548 if (ret) { 549 dev_err(priv->dev, "Unable to allocate dst scatterlist\n"); 550 ret = -ENOMEM; 551 goto out_return; 552 } 553 554 /* 555 * This is an ugly hack 556 * 557 * We fill in a scatterlist as if it were mapped for DMA. This is 558 * necessary because there exists no better structure for this 559 * inside the kernel code. 560 * 561 * As an added bonus, we can use the DMAEngine API for all of this, 562 * rather than inventing another extremely similar API. 563 */ 564 avail = priv->bytes; 565 for_each_sg(table.sgl, sg, num_pages, i) { 566 len = min_t(size_t, avail, FIFO_MAX_LEN); 567 sg_dma_address(sg) = FIFO_DMA_ADDRESS; 568 sg_dma_len(sg) = len; 569 570 avail -= len; 571 } 572 573 /* Map the buffer for DMA */ 574 ret = fpga_dma_map(priv); 575 if (ret) { 576 dev_err(priv->dev, "Unable to map buffer for DMA\n"); 577 goto out_free_table; 578 } 579 580 /* 581 * Configure the DMA channel to transfer FIFO_SIZE / 2 bytes per 582 * transaction, and then put it under external control 583 */ 584 memset(&config, 0, sizeof(config)); 585 config.direction = DMA_MEM_TO_DEV; 586 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 587 config.dst_maxburst = fpga_fifo_size(priv->regs) / 2 / 4; 588 ret = dmaengine_slave_config(chan, &config); 589 if (ret) { 590 dev_err(priv->dev, "DMA slave configuration failed\n"); 591 goto out_dma_unmap; 592 } 593 594 ret = fsl_dma_external_start(chan, 1); 595 if (ret) { 596 dev_err(priv->dev, "DMA external control setup failed\n"); 597 goto out_dma_unmap; 598 } 599 600 /* setup and submit the DMA transaction */ 601 602 tx = dmaengine_prep_dma_sg(chan, table.sgl, num_pages, 603 priv->sglist, priv->sglen, 0); 604 if (!tx) { 605 dev_err(priv->dev, "Unable to prep DMA transaction\n"); 606 ret = -ENOMEM; 607 goto out_dma_unmap; 608 } 609 610 cookie = tx->tx_submit(tx); 611 if (dma_submit_error(cookie)) { 612 dev_err(priv->dev, "Unable to submit DMA transaction\n"); 613 ret = -ENOMEM; 614 goto out_dma_unmap; 615 } 616 617 dma_async_issue_pending(chan); 618 619 /* Set the total byte count */ 620 fpga_set_byte_count(priv->regs, priv->bytes); 621 dev_dbg(priv->dev, "total byte count %u bytes\n", priv->bytes); 622 623 /* Enable the controller for DMA programming */ 624 fpga_programmer_enable(priv, true); 625 dev_dbg(priv->dev, "enabled the controller\n"); 626 627 /* Wait for the interrupt handler to signal that programming finished */ 628 timeout = wait_for_completion_timeout(&priv->completion, 2 * HZ); 629 if (!timeout) { 630 dev_err(priv->dev, "Timed out waiting for completion\n"); 631 ret = -ETIMEDOUT; 632 goto out_disable_controller; 633 } 634 635 /* Retrieve the status from the interrupt handler */ 636 ret = priv->status; 637 638out_disable_controller: 639 fpga_programmer_disable(priv); 640out_dma_unmap: 641 fpga_dma_unmap(priv); 642out_free_table: 643 sg_free_table(&table); 644out_return: 645 return ret; 646} 647 648/* 649 * Interrupt Handling 650 */ 651 652static irqreturn_t fpga_irq(int irq, void *dev_id) 653{ 654 struct fpga_dev *priv = dev_id; 655 656 /* Save the status */ 657 priv->status = fpga_config_error(priv->regs) ? -EIO : 0; 658 dev_dbg(priv->dev, "INTERRUPT status %d\n", priv->status); 659 fpga_dump_registers(priv); 660 661 /* Disabling the programmer clears the interrupt */ 662 fpga_programmer_disable(priv); 663 664 /* Notify any waiters */ 665 complete(&priv->completion); 666 667 return IRQ_HANDLED; 668} 669 670/* 671 * SYSFS Helpers 672 */ 673 674/** 675 * fpga_do_stop() - deconfigure (reset) the DATA-FPGA's 676 * @priv: the driver's private data structure 677 * 678 * LOCKING: must hold priv->lock 679 */ 680static int fpga_do_stop(struct fpga_dev *priv) 681{ 682 u32 val; 683 684 /* Set the led to unprogrammed */ 685 ledtrig_fpga_programmed(false); 686 687 /* Pulse the config line to reset the FPGA's */ 688 val = CFG_CTL_ENABLE | CFG_CTL_RESET; 689 iowrite32be(val, priv->regs + FPGA_CONFIG_CONTROL); 690 iowrite32be(0x0, priv->regs + FPGA_CONFIG_CONTROL); 691 692 return 0; 693} 694 695static noinline int fpga_do_program(struct fpga_dev *priv) 696{ 697 int ret; 698 699 if (priv->bytes != priv->fw_size) { 700 dev_err(priv->dev, "Incorrect bitfile size: got %zu bytes, " 701 "should be %zu bytes\n", 702 priv->bytes, priv->fw_size); 703 return -EINVAL; 704 } 705 706 if (!fpga_power_enabled(priv)) { 707 dev_err(priv->dev, "Power not enabled\n"); 708 return -EINVAL; 709 } 710 711 if (!fpga_power_good(priv)) { 712 dev_err(priv->dev, "Power not good\n"); 713 return -EINVAL; 714 } 715 716 /* Set the LED to unprogrammed */ 717 ledtrig_fpga_programmed(false); 718 719 /* Try to program the FPGA's using DMA */ 720 ret = fpga_program_dma(priv); 721 722 /* If DMA failed or doesn't exist, try with CPU */ 723 if (ret) { 724 dev_warn(priv->dev, "Falling back to CPU programming\n"); 725 ret = fpga_program_cpu(priv); 726 } 727 728 if (ret) { 729 dev_err(priv->dev, "Unable to program FPGA's\n"); 730 return ret; 731 } 732 733 /* Drop the firmware bitfile from memory */ 734 fpga_drop_firmware_data(priv); 735 736 dev_dbg(priv->dev, "FPGA programming successful\n"); 737 ledtrig_fpga_programmed(true); 738 739 return 0; 740} 741 742/* 743 * File Operations 744 */ 745 746static int fpga_open(struct inode *inode, struct file *filp) 747{ 748 /* 749 * The miscdevice layer puts our struct miscdevice into the 750 * filp->private_data field. We use this to find our private 751 * data and then overwrite it with our own private structure. 752 */ 753 struct fpga_dev *priv = container_of(filp->private_data, 754 struct fpga_dev, miscdev); 755 unsigned int nr_pages; 756 int ret; 757 758 /* We only allow one process at a time */ 759 ret = mutex_lock_interruptible(&priv->lock); 760 if (ret) 761 return ret; 762 763 filp->private_data = priv; 764 kref_get(&priv->ref); 765 766 /* Truncation: drop any existing data */ 767 if (filp->f_flags & O_TRUNC) 768 priv->bytes = 0; 769 770 /* Check if we have already allocated a buffer */ 771 if (priv->buf_allocated) 772 return 0; 773 774 /* Allocate a buffer to hold enough data for the bitfile */ 775 nr_pages = DIV_ROUND_UP(priv->fw_size, PAGE_SIZE); 776 ret = fpga_dma_init(priv, nr_pages); 777 if (ret) { 778 dev_err(priv->dev, "unable to allocate data buffer\n"); 779 mutex_unlock(&priv->lock); 780 kref_put(&priv->ref, fpga_dev_remove); 781 return ret; 782 } 783 784 priv->buf_allocated = true; 785 return 0; 786} 787 788static int fpga_release(struct inode *inode, struct file *filp) 789{ 790 struct fpga_dev *priv = filp->private_data; 791 792 mutex_unlock(&priv->lock); 793 kref_put(&priv->ref, fpga_dev_remove); 794 return 0; 795} 796 797static ssize_t fpga_write(struct file *filp, const char __user *buf, 798 size_t count, loff_t *f_pos) 799{ 800 struct fpga_dev *priv = filp->private_data; 801 802 /* FPGA bitfiles have an exact size: disallow anything else */ 803 if (priv->bytes >= priv->fw_size) 804 return -ENOSPC; 805 806 count = min_t(size_t, priv->fw_size - priv->bytes, count); 807 if (copy_from_user(priv->vaddr + priv->bytes, buf, count)) 808 return -EFAULT; 809 810 priv->bytes += count; 811 return count; 812} 813 814static ssize_t fpga_read(struct file *filp, char __user *buf, size_t count, 815 loff_t *f_pos) 816{ 817 struct fpga_dev *priv = filp->private_data; 818 return simple_read_from_buffer(buf, count, f_pos, 819 priv->vaddr, priv->bytes); 820} 821 822static loff_t fpga_llseek(struct file *filp, loff_t offset, int origin) 823{ 824 struct fpga_dev *priv = filp->private_data; 825 826 /* only read-only opens are allowed to seek */ 827 if ((filp->f_flags & O_ACCMODE) != O_RDONLY) 828 return -EINVAL; 829 830 return fixed_size_llseek(filp, offset, origin, priv->fw_size); 831} 832 833static const struct file_operations fpga_fops = { 834 .open = fpga_open, 835 .release = fpga_release, 836 .write = fpga_write, 837 .read = fpga_read, 838 .llseek = fpga_llseek, 839}; 840 841/* 842 * Device Attributes 843 */ 844 845static ssize_t pfail_show(struct device *dev, struct device_attribute *attr, 846 char *buf) 847{ 848 struct fpga_dev *priv = dev_get_drvdata(dev); 849 u8 val; 850 851 val = ioread8(priv->regs + CTL_PWR_FAIL); 852 return snprintf(buf, PAGE_SIZE, "0x%.2x\n", val); 853} 854 855static ssize_t pgood_show(struct device *dev, struct device_attribute *attr, 856 char *buf) 857{ 858 struct fpga_dev *priv = dev_get_drvdata(dev); 859 return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_good(priv)); 860} 861 862static ssize_t penable_show(struct device *dev, struct device_attribute *attr, 863 char *buf) 864{ 865 struct fpga_dev *priv = dev_get_drvdata(dev); 866 return snprintf(buf, PAGE_SIZE, "%d\n", fpga_power_enabled(priv)); 867} 868 869static ssize_t penable_store(struct device *dev, struct device_attribute *attr, 870 const char *buf, size_t count) 871{ 872 struct fpga_dev *priv = dev_get_drvdata(dev); 873 unsigned long val; 874 int ret; 875 876 ret = kstrtoul(buf, 0, &val); 877 if (ret) 878 return ret; 879 880 if (val) { 881 ret = fpga_enable_power_supplies(priv); 882 if (ret) 883 return ret; 884 } else { 885 fpga_do_stop(priv); 886 fpga_disable_power_supplies(priv); 887 } 888 889 return count; 890} 891 892static ssize_t program_show(struct device *dev, struct device_attribute *attr, 893 char *buf) 894{ 895 struct fpga_dev *priv = dev_get_drvdata(dev); 896 return snprintf(buf, PAGE_SIZE, "%d\n", fpga_running(priv)); 897} 898 899static ssize_t program_store(struct device *dev, struct device_attribute *attr, 900 const char *buf, size_t count) 901{ 902 struct fpga_dev *priv = dev_get_drvdata(dev); 903 unsigned long val; 904 int ret; 905 906 ret = kstrtoul(buf, 0, &val); 907 if (ret) 908 return ret; 909 910 /* We can't have an image writer and be programming simultaneously */ 911 if (mutex_lock_interruptible(&priv->lock)) 912 return -ERESTARTSYS; 913 914 /* Program or Reset the FPGA's */ 915 ret = val ? fpga_do_program(priv) : fpga_do_stop(priv); 916 if (ret) 917 goto out_unlock; 918 919 /* Success */ 920 ret = count; 921 922out_unlock: 923 mutex_unlock(&priv->lock); 924 return ret; 925} 926 927static DEVICE_ATTR(power_fail, S_IRUGO, pfail_show, NULL); 928static DEVICE_ATTR(power_good, S_IRUGO, pgood_show, NULL); 929static DEVICE_ATTR(power_enable, S_IRUGO | S_IWUSR, 930 penable_show, penable_store); 931 932static DEVICE_ATTR(program, S_IRUGO | S_IWUSR, 933 program_show, program_store); 934 935static struct attribute *fpga_attributes[] = { 936 &dev_attr_power_fail.attr, 937 &dev_attr_power_good.attr, 938 &dev_attr_power_enable.attr, 939 &dev_attr_program.attr, 940 NULL, 941}; 942 943static const struct attribute_group fpga_attr_group = { 944 .attrs = fpga_attributes, 945}; 946 947/* 948 * OpenFirmware Device Subsystem 949 */ 950 951#define SYS_REG_VERSION 0x00 952#define SYS_REG_GEOGRAPHIC 0x10 953 954static bool dma_filter(struct dma_chan *chan, void *data) 955{ 956 /* 957 * DMA Channel #0 is the only acceptable device 958 * 959 * This probably won't survive an unload/load cycle of the Freescale 960 * DMAEngine driver, but that won't be a problem 961 */ 962 return chan->chan_id == 0 && chan->device->dev_id == 0; 963} 964 965static int fpga_of_remove(struct platform_device *op) 966{ 967 struct fpga_dev *priv = platform_get_drvdata(op); 968 struct device *this_device = priv->miscdev.this_device; 969 970 sysfs_remove_group(&this_device->kobj, &fpga_attr_group); 971 misc_deregister(&priv->miscdev); 972 973 free_irq(priv->irq, priv); 974 irq_dispose_mapping(priv->irq); 975 976 /* make sure the power supplies are off */ 977 fpga_disable_power_supplies(priv); 978 979 /* unmap registers */ 980 iounmap(priv->immr); 981 iounmap(priv->regs); 982 983 dma_release_channel(priv->chan); 984 985 /* drop our reference to the private data structure */ 986 kref_put(&priv->ref, fpga_dev_remove); 987 return 0; 988} 989 990/* CTL-CPLD Version Register */ 991#define CTL_CPLD_VERSION 0x2000 992 993static int fpga_of_probe(struct platform_device *op) 994{ 995 struct device_node *of_node = op->dev.of_node; 996 struct device *this_device; 997 struct fpga_dev *priv; 998 dma_cap_mask_t mask; 999 u32 ver; 1000 int ret; 1001 1002 /* Allocate private data */ 1003 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 1004 if (!priv) { 1005 dev_err(&op->dev, "Unable to allocate private data\n"); 1006 ret = -ENOMEM; 1007 goto out_return; 1008 } 1009 1010 /* Setup the miscdevice */ 1011 priv->miscdev.minor = MISC_DYNAMIC_MINOR; 1012 priv->miscdev.name = drv_name; 1013 priv->miscdev.fops = &fpga_fops; 1014 1015 kref_init(&priv->ref); 1016 1017 platform_set_drvdata(op, priv); 1018 priv->dev = &op->dev; 1019 mutex_init(&priv->lock); 1020 init_completion(&priv->completion); 1021 1022 dev_set_drvdata(priv->dev, priv); 1023 dma_cap_zero(mask); 1024 dma_cap_set(DMA_MEMCPY, mask); 1025 dma_cap_set(DMA_SLAVE, mask); 1026 dma_cap_set(DMA_SG, mask); 1027 1028 /* Get control of DMA channel #0 */ 1029 priv->chan = dma_request_channel(mask, dma_filter, NULL); 1030 if (!priv->chan) { 1031 dev_err(&op->dev, "Unable to acquire DMA channel #0\n"); 1032 ret = -ENODEV; 1033 goto out_free_priv; 1034 } 1035 1036 /* Remap the registers for use */ 1037 priv->regs = of_iomap(of_node, 0); 1038 if (!priv->regs) { 1039 dev_err(&op->dev, "Unable to ioremap registers\n"); 1040 ret = -ENOMEM; 1041 goto out_dma_release_channel; 1042 } 1043 1044 /* Remap the IMMR for use */ 1045 priv->immr = ioremap(get_immrbase(), 0x100000); 1046 if (!priv->immr) { 1047 dev_err(&op->dev, "Unable to ioremap IMMR\n"); 1048 ret = -ENOMEM; 1049 goto out_unmap_regs; 1050 } 1051 1052 /* 1053 * Check that external DMA is configured 1054 * 1055 * U-Boot does this for us, but we should check it and bail out if 1056 * there is a problem. Failing to have this register setup correctly 1057 * will cause the DMA controller to transfer a single cacheline 1058 * worth of data, then wedge itself. 1059 */ 1060 if ((ioread32be(priv->immr + 0x114) & 0xE00) != 0xE00) { 1061 dev_err(&op->dev, "External DMA control not configured\n"); 1062 ret = -ENODEV; 1063 goto out_unmap_immr; 1064 } 1065 1066 /* 1067 * Check the CTL-CPLD version 1068 * 1069 * This driver uses the CTL-CPLD DATA-FPGA power sequencer, and we 1070 * don't want to run on any version of the CTL-CPLD that does not use 1071 * a compatible register layout. 1072 * 1073 * v2: changed register layout, added power sequencer 1074 * v3: added glitch filter on the i2c overcurrent/overtemp outputs 1075 */ 1076 ver = ioread8(priv->regs + CTL_CPLD_VERSION); 1077 if (ver != 0x02 && ver != 0x03) { 1078 dev_err(&op->dev, "CTL-CPLD is not version 0x02 or 0x03!\n"); 1079 ret = -ENODEV; 1080 goto out_unmap_immr; 1081 } 1082 1083 /* Set the exact size that the firmware image should be */ 1084 ver = ioread32be(priv->regs + SYS_REG_VERSION); 1085 priv->fw_size = (ver & (1 << 18)) ? FW_SIZE_EP2S130 : FW_SIZE_EP2S90; 1086 1087 /* Find the correct IRQ number */ 1088 priv->irq = irq_of_parse_and_map(of_node, 0); 1089 if (priv->irq == NO_IRQ) { 1090 dev_err(&op->dev, "Unable to find IRQ line\n"); 1091 ret = -ENODEV; 1092 goto out_unmap_immr; 1093 } 1094 1095 /* Request the IRQ */ 1096 ret = request_irq(priv->irq, fpga_irq, IRQF_SHARED, drv_name, priv); 1097 if (ret) { 1098 dev_err(&op->dev, "Unable to request IRQ %d\n", priv->irq); 1099 ret = -ENODEV; 1100 goto out_irq_dispose_mapping; 1101 } 1102 1103 /* Reset and stop the FPGA's, just in case */ 1104 fpga_do_stop(priv); 1105 1106 /* Register the miscdevice */ 1107 ret = misc_register(&priv->miscdev); 1108 if (ret) { 1109 dev_err(&op->dev, "Unable to register miscdevice\n"); 1110 goto out_free_irq; 1111 } 1112 1113 /* Create the sysfs files */ 1114 this_device = priv->miscdev.this_device; 1115 dev_set_drvdata(this_device, priv); 1116 ret = sysfs_create_group(&this_device->kobj, &fpga_attr_group); 1117 if (ret) { 1118 dev_err(&op->dev, "Unable to create sysfs files\n"); 1119 goto out_misc_deregister; 1120 } 1121 1122 dev_info(priv->dev, "CARMA FPGA Programmer: %s rev%s with %s FPGAs\n", 1123 (ver & (1 << 17)) ? "Correlator" : "Digitizer", 1124 (ver & (1 << 16)) ? "B" : "A", 1125 (ver & (1 << 18)) ? "EP2S130" : "EP2S90"); 1126 1127 return 0; 1128 1129out_misc_deregister: 1130 misc_deregister(&priv->miscdev); 1131out_free_irq: 1132 free_irq(priv->irq, priv); 1133out_irq_dispose_mapping: 1134 irq_dispose_mapping(priv->irq); 1135out_unmap_immr: 1136 iounmap(priv->immr); 1137out_unmap_regs: 1138 iounmap(priv->regs); 1139out_dma_release_channel: 1140 dma_release_channel(priv->chan); 1141out_free_priv: 1142 kref_put(&priv->ref, fpga_dev_remove); 1143out_return: 1144 return ret; 1145} 1146 1147static const struct of_device_id fpga_of_match[] = { 1148 { .compatible = "carma,fpga-programmer", }, 1149 {}, 1150}; 1151 1152static struct platform_driver fpga_of_driver = { 1153 .probe = fpga_of_probe, 1154 .remove = fpga_of_remove, 1155 .driver = { 1156 .name = drv_name, 1157 .of_match_table = fpga_of_match, 1158 }, 1159}; 1160 1161/* 1162 * Module Init / Exit 1163 */ 1164 1165static int __init fpga_init(void) 1166{ 1167 led_trigger_register_simple("fpga", &ledtrig_fpga); 1168 return platform_driver_register(&fpga_of_driver); 1169} 1170 1171static void __exit fpga_exit(void) 1172{ 1173 platform_driver_unregister(&fpga_of_driver); 1174 led_trigger_unregister_simple(ledtrig_fpga); 1175} 1176 1177MODULE_AUTHOR("Ira W. Snyder <iws@ovro.caltech.edu>"); 1178MODULE_DESCRIPTION("CARMA Board DATA-FPGA Programmer"); 1179MODULE_LICENSE("GPL"); 1180 1181module_init(fpga_init); 1182module_exit(fpga_exit); 1183