1/* 2 * Driver for sunxi SD/MMC host controllers 3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch> 7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/io.h> 18#include <linux/device.h> 19#include <linux/interrupt.h> 20#include <linux/delay.h> 21#include <linux/err.h> 22 23#include <linux/clk.h> 24#include <linux/gpio.h> 25#include <linux/platform_device.h> 26#include <linux/spinlock.h> 27#include <linux/scatterlist.h> 28#include <linux/dma-mapping.h> 29#include <linux/slab.h> 30#include <linux/reset.h> 31 32#include <linux/of_address.h> 33#include <linux/of_gpio.h> 34#include <linux/of_platform.h> 35 36#include <linux/mmc/host.h> 37#include <linux/mmc/sd.h> 38#include <linux/mmc/sdio.h> 39#include <linux/mmc/mmc.h> 40#include <linux/mmc/core.h> 41#include <linux/mmc/card.h> 42#include <linux/mmc/slot-gpio.h> 43 44/* register offset definitions */ 45#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 46#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 47#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 48#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 49#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 50#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 51#define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 52#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 53#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 54#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 55#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 56#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 57#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 58#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 59#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 60#define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 61#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 62#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 63#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 64#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 65#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 66#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 67#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 68#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 69#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 70#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 71#define SDXC_REG_CHDA (0x90) 72#define SDXC_REG_CBDA (0x94) 73 74#define mmc_readl(host, reg) \ 75 readl((host)->reg_base + SDXC_##reg) 76#define mmc_writel(host, reg, value) \ 77 writel((value), (host)->reg_base + SDXC_##reg) 78 79/* global control register bits */ 80#define SDXC_SOFT_RESET BIT(0) 81#define SDXC_FIFO_RESET BIT(1) 82#define SDXC_DMA_RESET BIT(2) 83#define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 84#define SDXC_DMA_ENABLE_BIT BIT(5) 85#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 86#define SDXC_POSEDGE_LATCH_DATA BIT(9) 87#define SDXC_DDR_MODE BIT(10) 88#define SDXC_MEMORY_ACCESS_DONE BIT(29) 89#define SDXC_ACCESS_DONE_DIRECT BIT(30) 90#define SDXC_ACCESS_BY_AHB BIT(31) 91#define SDXC_ACCESS_BY_DMA (0 << 31) 92#define SDXC_HARDWARE_RESET \ 93 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 94 95/* clock control bits */ 96#define SDXC_CARD_CLOCK_ON BIT(16) 97#define SDXC_LOW_POWER_ON BIT(17) 98 99/* bus width */ 100#define SDXC_WIDTH1 0 101#define SDXC_WIDTH4 1 102#define SDXC_WIDTH8 2 103 104/* smc command bits */ 105#define SDXC_RESP_EXPIRE BIT(6) 106#define SDXC_LONG_RESPONSE BIT(7) 107#define SDXC_CHECK_RESPONSE_CRC BIT(8) 108#define SDXC_DATA_EXPIRE BIT(9) 109#define SDXC_WRITE BIT(10) 110#define SDXC_SEQUENCE_MODE BIT(11) 111#define SDXC_SEND_AUTO_STOP BIT(12) 112#define SDXC_WAIT_PRE_OVER BIT(13) 113#define SDXC_STOP_ABORT_CMD BIT(14) 114#define SDXC_SEND_INIT_SEQUENCE BIT(15) 115#define SDXC_UPCLK_ONLY BIT(21) 116#define SDXC_READ_CEATA_DEV BIT(22) 117#define SDXC_CCS_EXPIRE BIT(23) 118#define SDXC_ENABLE_BIT_BOOT BIT(24) 119#define SDXC_ALT_BOOT_OPTIONS BIT(25) 120#define SDXC_BOOT_ACK_EXPIRE BIT(26) 121#define SDXC_BOOT_ABORT BIT(27) 122#define SDXC_VOLTAGE_SWITCH BIT(28) 123#define SDXC_USE_HOLD_REGISTER BIT(29) 124#define SDXC_START BIT(31) 125 126/* interrupt bits */ 127#define SDXC_RESP_ERROR BIT(1) 128#define SDXC_COMMAND_DONE BIT(2) 129#define SDXC_DATA_OVER BIT(3) 130#define SDXC_TX_DATA_REQUEST BIT(4) 131#define SDXC_RX_DATA_REQUEST BIT(5) 132#define SDXC_RESP_CRC_ERROR BIT(6) 133#define SDXC_DATA_CRC_ERROR BIT(7) 134#define SDXC_RESP_TIMEOUT BIT(8) 135#define SDXC_DATA_TIMEOUT BIT(9) 136#define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 137#define SDXC_FIFO_RUN_ERROR BIT(11) 138#define SDXC_HARD_WARE_LOCKED BIT(12) 139#define SDXC_START_BIT_ERROR BIT(13) 140#define SDXC_AUTO_COMMAND_DONE BIT(14) 141#define SDXC_END_BIT_ERROR BIT(15) 142#define SDXC_SDIO_INTERRUPT BIT(16) 143#define SDXC_CARD_INSERT BIT(30) 144#define SDXC_CARD_REMOVE BIT(31) 145#define SDXC_INTERRUPT_ERROR_BIT \ 146 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 147 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 148 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 149#define SDXC_INTERRUPT_DONE_BIT \ 150 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 151 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 152 153/* status */ 154#define SDXC_RXWL_FLAG BIT(0) 155#define SDXC_TXWL_FLAG BIT(1) 156#define SDXC_FIFO_EMPTY BIT(2) 157#define SDXC_FIFO_FULL BIT(3) 158#define SDXC_CARD_PRESENT BIT(8) 159#define SDXC_CARD_DATA_BUSY BIT(9) 160#define SDXC_DATA_FSM_BUSY BIT(10) 161#define SDXC_DMA_REQUEST BIT(31) 162#define SDXC_FIFO_SIZE 16 163 164/* Function select */ 165#define SDXC_CEATA_ON (0xceaa << 16) 166#define SDXC_SEND_IRQ_RESPONSE BIT(0) 167#define SDXC_SDIO_READ_WAIT BIT(1) 168#define SDXC_ABORT_READ_DATA BIT(2) 169#define SDXC_SEND_CCSD BIT(8) 170#define SDXC_SEND_AUTO_STOPCCSD BIT(9) 171#define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 172 173/* IDMA controller bus mod bit field */ 174#define SDXC_IDMAC_SOFT_RESET BIT(0) 175#define SDXC_IDMAC_FIX_BURST BIT(1) 176#define SDXC_IDMAC_IDMA_ON BIT(7) 177#define SDXC_IDMAC_REFETCH_DES BIT(31) 178 179/* IDMA status bit field */ 180#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 181#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 182#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 183#define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 184#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 185#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 186#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 187#define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 188#define SDXC_IDMAC_IDLE (0 << 13) 189#define SDXC_IDMAC_SUSPEND (1 << 13) 190#define SDXC_IDMAC_DESC_READ (2 << 13) 191#define SDXC_IDMAC_DESC_CHECK (3 << 13) 192#define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 193#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 194#define SDXC_IDMAC_READ (6 << 13) 195#define SDXC_IDMAC_WRITE (7 << 13) 196#define SDXC_IDMAC_DESC_CLOSE (8 << 13) 197 198/* 199* If the idma-des-size-bits of property is ie 13, bufsize bits are: 200* Bits 0-12: buf1 size 201* Bits 13-25: buf2 size 202* Bits 26-31: not used 203* Since we only ever set buf1 size, we can simply store it directly. 204*/ 205#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 206#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 207#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 208#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 209#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 210#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 211#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 212 213struct sunxi_idma_des { 214 u32 config; 215 u32 buf_size; 216 u32 buf_addr_ptr1; 217 u32 buf_addr_ptr2; 218}; 219 220struct sunxi_mmc_host { 221 struct mmc_host *mmc; 222 struct reset_control *reset; 223 224 /* IO mapping base */ 225 void __iomem *reg_base; 226 227 /* clock management */ 228 struct clk *clk_ahb; 229 struct clk *clk_mmc; 230 struct clk *clk_sample; 231 struct clk *clk_output; 232 233 /* irq */ 234 spinlock_t lock; 235 int irq; 236 u32 int_sum; 237 u32 sdio_imask; 238 239 /* dma */ 240 u32 idma_des_size_bits; 241 dma_addr_t sg_dma; 242 void *sg_cpu; 243 bool wait_dma; 244 245 struct mmc_request *mrq; 246 struct mmc_request *manual_stop_mrq; 247 int ferror; 248}; 249 250static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 251{ 252 unsigned long expire = jiffies + msecs_to_jiffies(250); 253 u32 rval; 254 255 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 256 do { 257 rval = mmc_readl(host, REG_GCTRL); 258 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 259 260 if (rval & SDXC_HARDWARE_RESET) { 261 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 262 return -EIO; 263 } 264 265 return 0; 266} 267 268static int sunxi_mmc_init_host(struct mmc_host *mmc) 269{ 270 u32 rval; 271 struct sunxi_mmc_host *host = mmc_priv(mmc); 272 273 if (sunxi_mmc_reset_host(host)) 274 return -EIO; 275 276 mmc_writel(host, REG_FTRGL, 0x20070008); 277 mmc_writel(host, REG_TMOUT, 0xffffffff); 278 mmc_writel(host, REG_IMASK, host->sdio_imask); 279 mmc_writel(host, REG_RINTR, 0xffffffff); 280 mmc_writel(host, REG_DBGC, 0xdeb); 281 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 282 mmc_writel(host, REG_DLBA, host->sg_dma); 283 284 rval = mmc_readl(host, REG_GCTRL); 285 rval |= SDXC_INTERRUPT_ENABLE_BIT; 286 rval &= ~SDXC_ACCESS_DONE_DIRECT; 287 mmc_writel(host, REG_GCTRL, rval); 288 289 return 0; 290} 291 292static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 293 struct mmc_data *data) 294{ 295 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 296 dma_addr_t next_desc = host->sg_dma; 297 int i, max_len = (1 << host->idma_des_size_bits); 298 299 for (i = 0; i < data->sg_len; i++) { 300 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN | 301 SDXC_IDMAC_DES0_DIC; 302 303 if (data->sg[i].length == max_len) 304 pdes[i].buf_size = 0; /* 0 == max_len */ 305 else 306 pdes[i].buf_size = data->sg[i].length; 307 308 next_desc += sizeof(struct sunxi_idma_des); 309 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]); 310 pdes[i].buf_addr_ptr2 = (u32)next_desc; 311 } 312 313 pdes[0].config |= SDXC_IDMAC_DES0_FD; 314 pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER; 315 pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC; 316 pdes[i - 1].buf_addr_ptr2 = 0; 317 318 /* 319 * Avoid the io-store starting the idmac hitting io-mem before the 320 * descriptors hit the main-mem. 321 */ 322 wmb(); 323} 324 325static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data) 326{ 327 if (data->flags & MMC_DATA_WRITE) 328 return DMA_TO_DEVICE; 329 else 330 return DMA_FROM_DEVICE; 331} 332 333static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 334 struct mmc_data *data) 335{ 336 u32 i, dma_len; 337 struct scatterlist *sg; 338 339 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 340 sunxi_mmc_get_dma_dir(data)); 341 if (dma_len == 0) { 342 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 343 return -ENOMEM; 344 } 345 346 for_each_sg(data->sg, sg, data->sg_len, i) { 347 if (sg->offset & 3 || sg->length & 3) { 348 dev_err(mmc_dev(host->mmc), 349 "unaligned scatterlist: os %x length %d\n", 350 sg->offset, sg->length); 351 return -EINVAL; 352 } 353 } 354 355 return 0; 356} 357 358static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 359 struct mmc_data *data) 360{ 361 u32 rval; 362 363 sunxi_mmc_init_idma_des(host, data); 364 365 rval = mmc_readl(host, REG_GCTRL); 366 rval |= SDXC_DMA_ENABLE_BIT; 367 mmc_writel(host, REG_GCTRL, rval); 368 rval |= SDXC_DMA_RESET; 369 mmc_writel(host, REG_GCTRL, rval); 370 371 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 372 373 if (!(data->flags & MMC_DATA_WRITE)) 374 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 375 376 mmc_writel(host, REG_DMAC, 377 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 378} 379 380static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 381 struct mmc_request *req) 382{ 383 u32 arg, cmd_val, ri; 384 unsigned long expire = jiffies + msecs_to_jiffies(1000); 385 386 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 387 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 388 389 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 390 cmd_val |= SD_IO_RW_DIRECT; 391 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 392 ((req->cmd->arg >> 28) & 0x7); 393 } else { 394 cmd_val |= MMC_STOP_TRANSMISSION; 395 arg = 0; 396 } 397 398 mmc_writel(host, REG_CARG, arg); 399 mmc_writel(host, REG_CMDR, cmd_val); 400 401 do { 402 ri = mmc_readl(host, REG_RINTR); 403 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 404 time_before(jiffies, expire)); 405 406 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 407 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 408 if (req->stop) 409 req->stop->resp[0] = -ETIMEDOUT; 410 } else { 411 if (req->stop) 412 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 413 } 414 415 mmc_writel(host, REG_RINTR, 0xffff); 416} 417 418static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 419{ 420 struct mmc_command *cmd = host->mrq->cmd; 421 struct mmc_data *data = host->mrq->data; 422 423 /* For some cmds timeout is normal with sd/mmc cards */ 424 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 425 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 426 cmd->opcode == SD_IO_RW_DIRECT)) 427 return; 428 429 dev_err(mmc_dev(host->mmc), 430 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 431 host->mmc->index, cmd->opcode, 432 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 433 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 434 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 435 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 436 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 437 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 438 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 439 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 440 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 441 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 442 ); 443} 444 445/* Called in interrupt context! */ 446static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 447{ 448 struct mmc_request *mrq = host->mrq; 449 struct mmc_data *data = mrq->data; 450 u32 rval; 451 452 mmc_writel(host, REG_IMASK, host->sdio_imask); 453 mmc_writel(host, REG_IDIE, 0); 454 455 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 456 sunxi_mmc_dump_errinfo(host); 457 mrq->cmd->error = -ETIMEDOUT; 458 459 if (data) { 460 data->error = -ETIMEDOUT; 461 host->manual_stop_mrq = mrq; 462 } 463 464 if (mrq->stop) 465 mrq->stop->error = -ETIMEDOUT; 466 } else { 467 if (mrq->cmd->flags & MMC_RSP_136) { 468 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 469 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 470 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 471 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 472 } else { 473 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 474 } 475 476 if (data) 477 data->bytes_xfered = data->blocks * data->blksz; 478 } 479 480 if (data) { 481 mmc_writel(host, REG_IDST, 0x337); 482 mmc_writel(host, REG_DMAC, 0); 483 rval = mmc_readl(host, REG_GCTRL); 484 rval |= SDXC_DMA_RESET; 485 mmc_writel(host, REG_GCTRL, rval); 486 rval &= ~SDXC_DMA_ENABLE_BIT; 487 mmc_writel(host, REG_GCTRL, rval); 488 rval |= SDXC_FIFO_RESET; 489 mmc_writel(host, REG_GCTRL, rval); 490 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 491 sunxi_mmc_get_dma_dir(data)); 492 } 493 494 mmc_writel(host, REG_RINTR, 0xffff); 495 496 host->mrq = NULL; 497 host->int_sum = 0; 498 host->wait_dma = false; 499 500 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 501} 502 503static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 504{ 505 struct sunxi_mmc_host *host = dev_id; 506 struct mmc_request *mrq; 507 u32 msk_int, idma_int; 508 bool finalize = false; 509 bool sdio_int = false; 510 irqreturn_t ret = IRQ_HANDLED; 511 512 spin_lock(&host->lock); 513 514 idma_int = mmc_readl(host, REG_IDST); 515 msk_int = mmc_readl(host, REG_MISTA); 516 517 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 518 host->mrq, msk_int, idma_int); 519 520 mrq = host->mrq; 521 if (mrq) { 522 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 523 host->wait_dma = false; 524 525 host->int_sum |= msk_int; 526 527 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 528 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 529 !(host->int_sum & SDXC_COMMAND_DONE)) 530 mmc_writel(host, REG_IMASK, 531 host->sdio_imask | SDXC_COMMAND_DONE); 532 /* Don't wait for dma on error */ 533 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 534 finalize = true; 535 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 536 !host->wait_dma) 537 finalize = true; 538 } 539 540 if (msk_int & SDXC_SDIO_INTERRUPT) 541 sdio_int = true; 542 543 mmc_writel(host, REG_RINTR, msk_int); 544 mmc_writel(host, REG_IDST, idma_int); 545 546 if (finalize) 547 ret = sunxi_mmc_finalize_request(host); 548 549 spin_unlock(&host->lock); 550 551 if (finalize && ret == IRQ_HANDLED) 552 mmc_request_done(host->mmc, mrq); 553 554 if (sdio_int) 555 mmc_signal_sdio_irq(host->mmc); 556 557 return ret; 558} 559 560static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 561{ 562 struct sunxi_mmc_host *host = dev_id; 563 struct mmc_request *mrq; 564 unsigned long iflags; 565 566 spin_lock_irqsave(&host->lock, iflags); 567 mrq = host->manual_stop_mrq; 568 spin_unlock_irqrestore(&host->lock, iflags); 569 570 if (!mrq) { 571 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 572 return IRQ_HANDLED; 573 } 574 575 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 576 577 /* 578 * We will never have more than one outstanding request, 579 * and we do not complete the request until after 580 * we've cleared host->manual_stop_mrq so we do not need to 581 * spin lock this function. 582 * Additionally we have wait states within this function 583 * so having it in a lock is a very bad idea. 584 */ 585 sunxi_mmc_send_manual_stop(host, mrq); 586 587 spin_lock_irqsave(&host->lock, iflags); 588 host->manual_stop_mrq = NULL; 589 spin_unlock_irqrestore(&host->lock, iflags); 590 591 mmc_request_done(host->mmc, mrq); 592 593 return IRQ_HANDLED; 594} 595 596static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 597{ 598 unsigned long expire = jiffies + msecs_to_jiffies(250); 599 u32 rval; 600 601 rval = mmc_readl(host, REG_CLKCR); 602 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON); 603 604 if (oclk_en) 605 rval |= SDXC_CARD_CLOCK_ON; 606 607 mmc_writel(host, REG_CLKCR, rval); 608 609 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 610 mmc_writel(host, REG_CMDR, rval); 611 612 do { 613 rval = mmc_readl(host, REG_CMDR); 614 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 615 616 /* clear irq status bits set by the command */ 617 mmc_writel(host, REG_RINTR, 618 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 619 620 if (rval & SDXC_START) { 621 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 622 return -EIO; 623 } 624 625 return 0; 626} 627 628static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 629 struct mmc_ios *ios) 630{ 631 u32 rate, oclk_dly, rval, sclk_dly; 632 int ret; 633 634 rate = clk_round_rate(host->clk_mmc, ios->clock); 635 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n", 636 ios->clock, rate); 637 638 /* setting clock rate */ 639 ret = clk_set_rate(host->clk_mmc, rate); 640 if (ret) { 641 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n", 642 rate, ret); 643 return ret; 644 } 645 646 ret = sunxi_mmc_oclk_onoff(host, 0); 647 if (ret) 648 return ret; 649 650 /* clear internal divider */ 651 rval = mmc_readl(host, REG_CLKCR); 652 rval &= ~0xff; 653 mmc_writel(host, REG_CLKCR, rval); 654 655 /* determine delays */ 656 if (rate <= 400000) { 657 oclk_dly = 180; 658 sclk_dly = 42; 659 } else if (rate <= 25000000) { 660 oclk_dly = 180; 661 sclk_dly = 75; 662 } else if (rate <= 50000000) { 663 if (ios->timing == MMC_TIMING_UHS_DDR50) { 664 oclk_dly = 60; 665 sclk_dly = 120; 666 } else { 667 oclk_dly = 90; 668 sclk_dly = 150; 669 } 670 } else if (rate <= 100000000) { 671 oclk_dly = 6; 672 sclk_dly = 24; 673 } else if (rate <= 200000000) { 674 oclk_dly = 3; 675 sclk_dly = 12; 676 } else { 677 return -EINVAL; 678 } 679 680 clk_set_phase(host->clk_sample, sclk_dly); 681 clk_set_phase(host->clk_output, oclk_dly); 682 683 return sunxi_mmc_oclk_onoff(host, 1); 684} 685 686static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 687{ 688 struct sunxi_mmc_host *host = mmc_priv(mmc); 689 u32 rval; 690 691 /* Set the power state */ 692 switch (ios->power_mode) { 693 case MMC_POWER_ON: 694 break; 695 696 case MMC_POWER_UP: 697 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 698 699 host->ferror = sunxi_mmc_init_host(mmc); 700 if (host->ferror) 701 return; 702 703 dev_dbg(mmc_dev(mmc), "power on!\n"); 704 break; 705 706 case MMC_POWER_OFF: 707 dev_dbg(mmc_dev(mmc), "power off!\n"); 708 sunxi_mmc_reset_host(host); 709 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 710 break; 711 } 712 713 /* set bus width */ 714 switch (ios->bus_width) { 715 case MMC_BUS_WIDTH_1: 716 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 717 break; 718 case MMC_BUS_WIDTH_4: 719 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 720 break; 721 case MMC_BUS_WIDTH_8: 722 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 723 break; 724 } 725 726 /* set ddr mode */ 727 rval = mmc_readl(host, REG_GCTRL); 728 if (ios->timing == MMC_TIMING_UHS_DDR50) 729 rval |= SDXC_DDR_MODE; 730 else 731 rval &= ~SDXC_DDR_MODE; 732 mmc_writel(host, REG_GCTRL, rval); 733 734 /* set up clock */ 735 if (ios->clock && ios->power_mode) { 736 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 737 /* Android code had a usleep_range(50000, 55000); here */ 738 } 739} 740 741static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 742{ 743 struct sunxi_mmc_host *host = mmc_priv(mmc); 744 unsigned long flags; 745 u32 imask; 746 747 spin_lock_irqsave(&host->lock, flags); 748 749 imask = mmc_readl(host, REG_IMASK); 750 if (enable) { 751 host->sdio_imask = SDXC_SDIO_INTERRUPT; 752 imask |= SDXC_SDIO_INTERRUPT; 753 } else { 754 host->sdio_imask = 0; 755 imask &= ~SDXC_SDIO_INTERRUPT; 756 } 757 mmc_writel(host, REG_IMASK, imask); 758 spin_unlock_irqrestore(&host->lock, flags); 759} 760 761static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 762{ 763 struct sunxi_mmc_host *host = mmc_priv(mmc); 764 mmc_writel(host, REG_HWRST, 0); 765 udelay(10); 766 mmc_writel(host, REG_HWRST, 1); 767 udelay(300); 768} 769 770static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 771{ 772 struct sunxi_mmc_host *host = mmc_priv(mmc); 773 struct mmc_command *cmd = mrq->cmd; 774 struct mmc_data *data = mrq->data; 775 unsigned long iflags; 776 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 777 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 778 bool wait_dma = host->wait_dma; 779 int ret; 780 781 /* Check for set_ios errors (should never happen) */ 782 if (host->ferror) { 783 mrq->cmd->error = host->ferror; 784 mmc_request_done(mmc, mrq); 785 return; 786 } 787 788 if (data) { 789 ret = sunxi_mmc_map_dma(host, data); 790 if (ret < 0) { 791 dev_err(mmc_dev(mmc), "map DMA failed\n"); 792 cmd->error = ret; 793 data->error = ret; 794 mmc_request_done(mmc, mrq); 795 return; 796 } 797 } 798 799 if (cmd->opcode == MMC_GO_IDLE_STATE) { 800 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 801 imask |= SDXC_COMMAND_DONE; 802 } 803 804 if (cmd->flags & MMC_RSP_PRESENT) { 805 cmd_val |= SDXC_RESP_EXPIRE; 806 if (cmd->flags & MMC_RSP_136) 807 cmd_val |= SDXC_LONG_RESPONSE; 808 if (cmd->flags & MMC_RSP_CRC) 809 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 810 811 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 812 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 813 if (cmd->data->flags & MMC_DATA_STREAM) { 814 imask |= SDXC_AUTO_COMMAND_DONE; 815 cmd_val |= SDXC_SEQUENCE_MODE | 816 SDXC_SEND_AUTO_STOP; 817 } 818 819 if (cmd->data->stop) { 820 imask |= SDXC_AUTO_COMMAND_DONE; 821 cmd_val |= SDXC_SEND_AUTO_STOP; 822 } else { 823 imask |= SDXC_DATA_OVER; 824 } 825 826 if (cmd->data->flags & MMC_DATA_WRITE) 827 cmd_val |= SDXC_WRITE; 828 else 829 wait_dma = true; 830 } else { 831 imask |= SDXC_COMMAND_DONE; 832 } 833 } else { 834 imask |= SDXC_COMMAND_DONE; 835 } 836 837 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 838 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 839 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 840 841 spin_lock_irqsave(&host->lock, iflags); 842 843 if (host->mrq || host->manual_stop_mrq) { 844 spin_unlock_irqrestore(&host->lock, iflags); 845 846 if (data) 847 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 848 sunxi_mmc_get_dma_dir(data)); 849 850 dev_err(mmc_dev(mmc), "request already pending\n"); 851 mrq->cmd->error = -EBUSY; 852 mmc_request_done(mmc, mrq); 853 return; 854 } 855 856 if (data) { 857 mmc_writel(host, REG_BLKSZ, data->blksz); 858 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 859 sunxi_mmc_start_dma(host, data); 860 } 861 862 host->mrq = mrq; 863 host->wait_dma = wait_dma; 864 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 865 mmc_writel(host, REG_CARG, cmd->arg); 866 mmc_writel(host, REG_CMDR, cmd_val); 867 868 spin_unlock_irqrestore(&host->lock, iflags); 869} 870 871static const struct of_device_id sunxi_mmc_of_match[] = { 872 { .compatible = "allwinner,sun4i-a10-mmc", }, 873 { .compatible = "allwinner,sun5i-a13-mmc", }, 874 { /* sentinel */ } 875}; 876MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 877 878static struct mmc_host_ops sunxi_mmc_ops = { 879 .request = sunxi_mmc_request, 880 .set_ios = sunxi_mmc_set_ios, 881 .get_ro = mmc_gpio_get_ro, 882 .get_cd = mmc_gpio_get_cd, 883 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 884 .hw_reset = sunxi_mmc_hw_reset, 885}; 886 887static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 888 struct platform_device *pdev) 889{ 890 struct device_node *np = pdev->dev.of_node; 891 int ret; 892 893 if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc")) 894 host->idma_des_size_bits = 13; 895 else 896 host->idma_des_size_bits = 16; 897 898 ret = mmc_regulator_get_supply(host->mmc); 899 if (ret) { 900 if (ret != -EPROBE_DEFER) 901 dev_err(&pdev->dev, "Could not get vmmc supply\n"); 902 return ret; 903 } 904 905 host->reg_base = devm_ioremap_resource(&pdev->dev, 906 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 907 if (IS_ERR(host->reg_base)) 908 return PTR_ERR(host->reg_base); 909 910 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 911 if (IS_ERR(host->clk_ahb)) { 912 dev_err(&pdev->dev, "Could not get ahb clock\n"); 913 return PTR_ERR(host->clk_ahb); 914 } 915 916 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 917 if (IS_ERR(host->clk_mmc)) { 918 dev_err(&pdev->dev, "Could not get mmc clock\n"); 919 return PTR_ERR(host->clk_mmc); 920 } 921 922 host->clk_output = devm_clk_get(&pdev->dev, "output"); 923 if (IS_ERR(host->clk_output)) { 924 dev_err(&pdev->dev, "Could not get output clock\n"); 925 return PTR_ERR(host->clk_output); 926 } 927 928 host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 929 if (IS_ERR(host->clk_sample)) { 930 dev_err(&pdev->dev, "Could not get sample clock\n"); 931 return PTR_ERR(host->clk_sample); 932 } 933 934 host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb"); 935 if (PTR_ERR(host->reset) == -EPROBE_DEFER) 936 return PTR_ERR(host->reset); 937 938 ret = clk_prepare_enable(host->clk_ahb); 939 if (ret) { 940 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret); 941 return ret; 942 } 943 944 ret = clk_prepare_enable(host->clk_mmc); 945 if (ret) { 946 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret); 947 goto error_disable_clk_ahb; 948 } 949 950 ret = clk_prepare_enable(host->clk_output); 951 if (ret) { 952 dev_err(&pdev->dev, "Enable output clk err %d\n", ret); 953 goto error_disable_clk_mmc; 954 } 955 956 ret = clk_prepare_enable(host->clk_sample); 957 if (ret) { 958 dev_err(&pdev->dev, "Enable sample clk err %d\n", ret); 959 goto error_disable_clk_output; 960 } 961 962 if (!IS_ERR(host->reset)) { 963 ret = reset_control_deassert(host->reset); 964 if (ret) { 965 dev_err(&pdev->dev, "reset err %d\n", ret); 966 goto error_disable_clk_sample; 967 } 968 } 969 970 /* 971 * Sometimes the controller asserts the irq on boot for some reason, 972 * make sure the controller is in a sane state before enabling irqs. 973 */ 974 ret = sunxi_mmc_reset_host(host); 975 if (ret) 976 goto error_assert_reset; 977 978 host->irq = platform_get_irq(pdev, 0); 979 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 980 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 981 982error_assert_reset: 983 if (!IS_ERR(host->reset)) 984 reset_control_assert(host->reset); 985error_disable_clk_sample: 986 clk_disable_unprepare(host->clk_sample); 987error_disable_clk_output: 988 clk_disable_unprepare(host->clk_output); 989error_disable_clk_mmc: 990 clk_disable_unprepare(host->clk_mmc); 991error_disable_clk_ahb: 992 clk_disable_unprepare(host->clk_ahb); 993 return ret; 994} 995 996static int sunxi_mmc_probe(struct platform_device *pdev) 997{ 998 struct sunxi_mmc_host *host; 999 struct mmc_host *mmc; 1000 int ret; 1001 1002 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 1003 if (!mmc) { 1004 dev_err(&pdev->dev, "mmc alloc host failed\n"); 1005 return -ENOMEM; 1006 } 1007 1008 host = mmc_priv(mmc); 1009 host->mmc = mmc; 1010 spin_lock_init(&host->lock); 1011 1012 ret = sunxi_mmc_resource_request(host, pdev); 1013 if (ret) 1014 goto error_free_host; 1015 1016 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1017 &host->sg_dma, GFP_KERNEL); 1018 if (!host->sg_cpu) { 1019 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 1020 ret = -ENOMEM; 1021 goto error_free_host; 1022 } 1023 1024 mmc->ops = &sunxi_mmc_ops; 1025 mmc->max_blk_count = 8192; 1026 mmc->max_blk_size = 4096; 1027 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 1028 mmc->max_seg_size = (1 << host->idma_des_size_bits); 1029 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 1030 /* 400kHz ~ 50MHz */ 1031 mmc->f_min = 400000; 1032 mmc->f_max = 50000000; 1033 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1034 MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 1035 1036 ret = mmc_of_parse(mmc); 1037 if (ret) 1038 goto error_free_dma; 1039 1040 ret = mmc_add_host(mmc); 1041 if (ret) 1042 goto error_free_dma; 1043 1044 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); 1045 platform_set_drvdata(pdev, mmc); 1046 return 0; 1047 1048error_free_dma: 1049 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1050error_free_host: 1051 mmc_free_host(mmc); 1052 return ret; 1053} 1054 1055static int sunxi_mmc_remove(struct platform_device *pdev) 1056{ 1057 struct mmc_host *mmc = platform_get_drvdata(pdev); 1058 struct sunxi_mmc_host *host = mmc_priv(mmc); 1059 1060 mmc_remove_host(mmc); 1061 disable_irq(host->irq); 1062 sunxi_mmc_reset_host(host); 1063 1064 if (!IS_ERR(host->reset)) 1065 reset_control_assert(host->reset); 1066 1067 clk_disable_unprepare(host->clk_mmc); 1068 clk_disable_unprepare(host->clk_ahb); 1069 1070 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1071 mmc_free_host(mmc); 1072 1073 return 0; 1074} 1075 1076static struct platform_driver sunxi_mmc_driver = { 1077 .driver = { 1078 .name = "sunxi-mmc", 1079 .of_match_table = of_match_ptr(sunxi_mmc_of_match), 1080 }, 1081 .probe = sunxi_mmc_probe, 1082 .remove = sunxi_mmc_remove, 1083}; 1084module_platform_driver(sunxi_mmc_driver); 1085 1086MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1087MODULE_LICENSE("GPL v2"); 1088MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>"); 1089MODULE_ALIAS("platform:sunxi-mmc"); 1090