1/* 2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01 3 * 4 * The data sheet for this device can be found at: 5 * http://wiki.laptop.org/go/Datasheets 6 * 7 * Copyright © 2006 Red Hat, Inc. 8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org> 9 */ 10 11#define DEBUG 12 13#include <linux/device.h> 14#undef DEBUG 15#include <linux/mtd/mtd.h> 16#include <linux/mtd/nand.h> 17#include <linux/mtd/partitions.h> 18#include <linux/rslib.h> 19#include <linux/pci.h> 20#include <linux/delay.h> 21#include <linux/interrupt.h> 22#include <linux/dma-mapping.h> 23#include <linux/slab.h> 24#include <linux/module.h> 25#include <asm/io.h> 26 27#define CAFE_NAND_CTRL1 0x00 28#define CAFE_NAND_CTRL2 0x04 29#define CAFE_NAND_CTRL3 0x08 30#define CAFE_NAND_STATUS 0x0c 31#define CAFE_NAND_IRQ 0x10 32#define CAFE_NAND_IRQ_MASK 0x14 33#define CAFE_NAND_DATA_LEN 0x18 34#define CAFE_NAND_ADDR1 0x1c 35#define CAFE_NAND_ADDR2 0x20 36#define CAFE_NAND_TIMING1 0x24 37#define CAFE_NAND_TIMING2 0x28 38#define CAFE_NAND_TIMING3 0x2c 39#define CAFE_NAND_NONMEM 0x30 40#define CAFE_NAND_ECC_RESULT 0x3C 41#define CAFE_NAND_DMA_CTRL 0x40 42#define CAFE_NAND_DMA_ADDR0 0x44 43#define CAFE_NAND_DMA_ADDR1 0x48 44#define CAFE_NAND_ECC_SYN01 0x50 45#define CAFE_NAND_ECC_SYN23 0x54 46#define CAFE_NAND_ECC_SYN45 0x58 47#define CAFE_NAND_ECC_SYN67 0x5c 48#define CAFE_NAND_READ_DATA 0x1000 49#define CAFE_NAND_WRITE_DATA 0x2000 50 51#define CAFE_GLOBAL_CTRL 0x3004 52#define CAFE_GLOBAL_IRQ 0x3008 53#define CAFE_GLOBAL_IRQ_MASK 0x300c 54#define CAFE_NAND_RESET 0x3034 55 56/* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */ 57#define CTRL1_CHIPSELECT (1<<19) 58 59struct cafe_priv { 60 struct nand_chip nand; 61 struct pci_dev *pdev; 62 void __iomem *mmio; 63 struct rs_control *rs; 64 uint32_t ctl1; 65 uint32_t ctl2; 66 int datalen; 67 int nr_data; 68 int data_pos; 69 int page_addr; 70 dma_addr_t dmaaddr; 71 unsigned char *dmabuf; 72}; 73 74static int usedma = 1; 75module_param(usedma, int, 0644); 76 77static int skipbbt = 0; 78module_param(skipbbt, int, 0644); 79 80static int debug = 0; 81module_param(debug, int, 0644); 82 83static int regdebug = 0; 84module_param(regdebug, int, 0644); 85 86static int checkecc = 1; 87module_param(checkecc, int, 0644); 88 89static unsigned int numtimings; 90static int timing[3]; 91module_param_array(timing, int, &numtimings, 0644); 92 93static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL }; 94 95/* Hrm. Why isn't this already conditional on something in the struct device? */ 96#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0) 97 98/* Make it easier to switch to PIO if we need to */ 99#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr) 100#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr) 101 102static int cafe_device_ready(struct mtd_info *mtd) 103{ 104 struct cafe_priv *cafe = mtd->priv; 105 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000); 106 uint32_t irqs = cafe_readl(cafe, NAND_IRQ); 107 108 cafe_writel(cafe, irqs, NAND_IRQ); 109 110 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n", 111 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ), 112 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK)); 113 114 return result; 115} 116 117 118static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 119{ 120 struct cafe_priv *cafe = mtd->priv; 121 122 if (usedma) 123 memcpy(cafe->dmabuf + cafe->datalen, buf, len); 124 else 125 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len); 126 127 cafe->datalen += len; 128 129 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n", 130 len, cafe->datalen); 131} 132 133static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 134{ 135 struct cafe_priv *cafe = mtd->priv; 136 137 if (usedma) 138 memcpy(buf, cafe->dmabuf + cafe->datalen, len); 139 else 140 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len); 141 142 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n", 143 len, cafe->datalen); 144 cafe->datalen += len; 145} 146 147static uint8_t cafe_read_byte(struct mtd_info *mtd) 148{ 149 struct cafe_priv *cafe = mtd->priv; 150 uint8_t d; 151 152 cafe_read_buf(mtd, &d, 1); 153 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d); 154 155 return d; 156} 157 158static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command, 159 int column, int page_addr) 160{ 161 struct cafe_priv *cafe = mtd->priv; 162 int adrbytes = 0; 163 uint32_t ctl1; 164 uint32_t doneint = 0x80000000; 165 166 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n", 167 command, column, page_addr); 168 169 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) { 170 /* Second half of a command we already calculated */ 171 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2); 172 ctl1 = cafe->ctl1; 173 cafe->ctl2 &= ~(1<<30); 174 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n", 175 cafe->ctl1, cafe->nr_data); 176 goto do_command; 177 } 178 /* Reset ECC engine */ 179 cafe_writel(cafe, 0, NAND_CTRL2); 180 181 /* Emulate NAND_CMD_READOOB on large-page chips */ 182 if (mtd->writesize > 512 && 183 command == NAND_CMD_READOOB) { 184 column += mtd->writesize; 185 command = NAND_CMD_READ0; 186 } 187 188 /* FIXME: Do we need to send read command before sending data 189 for small-page chips, to position the buffer correctly? */ 190 191 if (column != -1) { 192 cafe_writel(cafe, column, NAND_ADDR1); 193 adrbytes = 2; 194 if (page_addr != -1) 195 goto write_adr2; 196 } else if (page_addr != -1) { 197 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1); 198 page_addr >>= 16; 199 write_adr2: 200 cafe_writel(cafe, page_addr, NAND_ADDR2); 201 adrbytes += 2; 202 if (mtd->size > mtd->writesize << 16) 203 adrbytes++; 204 } 205 206 cafe->data_pos = cafe->datalen = 0; 207 208 /* Set command valid bit, mask in the chip select bit */ 209 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT); 210 211 /* Set RD or WR bits as appropriate */ 212 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) { 213 ctl1 |= (1<<26); /* rd */ 214 /* Always 5 bytes, for now */ 215 cafe->datalen = 4; 216 /* And one address cycle -- even for STATUS, since the controller doesn't work without */ 217 adrbytes = 1; 218 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || 219 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) { 220 ctl1 |= 1<<26; /* rd */ 221 /* For now, assume just read to end of page */ 222 cafe->datalen = mtd->writesize + mtd->oobsize - column; 223 } else if (command == NAND_CMD_SEQIN) 224 ctl1 |= 1<<25; /* wr */ 225 226 /* Set number of address bytes */ 227 if (adrbytes) 228 ctl1 |= ((adrbytes-1)|8) << 27; 229 230 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) { 231 /* Ignore the first command of a pair; the hardware 232 deals with them both at once, later */ 233 cafe->ctl1 = ctl1; 234 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n", 235 cafe->ctl1, cafe->datalen); 236 return; 237 } 238 /* RNDOUT and READ0 commands need a following byte */ 239 if (command == NAND_CMD_RNDOUT) 240 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2); 241 else if (command == NAND_CMD_READ0 && mtd->writesize > 512) 242 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2); 243 244 do_command: 245 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n", 246 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2)); 247 248 /* NB: The datasheet lies -- we really should be subtracting 1 here */ 249 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN); 250 cafe_writel(cafe, 0x90000000, NAND_IRQ); 251 if (usedma && (ctl1 & (3<<25))) { 252 uint32_t dmactl = 0xc0000000 + cafe->datalen; 253 /* If WR or RD bits set, set up DMA */ 254 if (ctl1 & (1<<26)) { 255 /* It's a read */ 256 dmactl |= (1<<29); 257 /* ... so it's done when the DMA is done, not just 258 the command. */ 259 doneint = 0x10000000; 260 } 261 cafe_writel(cafe, dmactl, NAND_DMA_CTRL); 262 } 263 cafe->datalen = 0; 264 265 if (unlikely(regdebug)) { 266 int i; 267 printk("About to write command %08x to register 0\n", ctl1); 268 for (i=4; i< 0x5c; i+=4) 269 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); 270 } 271 272 cafe_writel(cafe, ctl1, NAND_CTRL1); 273 /* Apply this short delay always to ensure that we do wait tWB in 274 * any case on any machine. */ 275 ndelay(100); 276 277 if (1) { 278 int c; 279 uint32_t irqs; 280 281 for (c = 500000; c != 0; c--) { 282 irqs = cafe_readl(cafe, NAND_IRQ); 283 if (irqs & doneint) 284 break; 285 udelay(1); 286 if (!(c % 100000)) 287 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs); 288 cpu_relax(); 289 } 290 cafe_writel(cafe, doneint, NAND_IRQ); 291 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n", 292 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ)); 293 } 294 295 WARN_ON(cafe->ctl2 & (1<<30)); 296 297 switch (command) { 298 299 case NAND_CMD_CACHEDPROG: 300 case NAND_CMD_PAGEPROG: 301 case NAND_CMD_ERASE1: 302 case NAND_CMD_ERASE2: 303 case NAND_CMD_SEQIN: 304 case NAND_CMD_RNDIN: 305 case NAND_CMD_STATUS: 306 case NAND_CMD_RNDOUT: 307 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); 308 return; 309 } 310 nand_wait_ready(mtd); 311 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2); 312} 313 314static void cafe_select_chip(struct mtd_info *mtd, int chipnr) 315{ 316 struct cafe_priv *cafe = mtd->priv; 317 318 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr); 319 320 /* Mask the appropriate bit into the stored value of ctl1 321 which will be used by cafe_nand_cmdfunc() */ 322 if (chipnr) 323 cafe->ctl1 |= CTRL1_CHIPSELECT; 324 else 325 cafe->ctl1 &= ~CTRL1_CHIPSELECT; 326} 327 328static irqreturn_t cafe_nand_interrupt(int irq, void *id) 329{ 330 struct mtd_info *mtd = id; 331 struct cafe_priv *cafe = mtd->priv; 332 uint32_t irqs = cafe_readl(cafe, NAND_IRQ); 333 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ); 334 if (!irqs) 335 return IRQ_NONE; 336 337 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ)); 338 return IRQ_HANDLED; 339} 340 341static void cafe_nand_bug(struct mtd_info *mtd) 342{ 343 BUG(); 344} 345 346static int cafe_nand_write_oob(struct mtd_info *mtd, 347 struct nand_chip *chip, int page) 348{ 349 int status = 0; 350 351 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page); 352 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 353 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1); 354 status = chip->waitfunc(mtd, chip); 355 356 return status & NAND_STATUS_FAIL ? -EIO : 0; 357} 358 359/* Don't use -- use nand_read_oob_std for now */ 360static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 361 int page) 362{ 363 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page); 364 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 365 return 0; 366} 367/** 368 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read 369 * @mtd: mtd info structure 370 * @chip: nand chip info structure 371 * @buf: buffer to store read data 372 * @oob_required: caller expects OOB data read to chip->oob_poi 373 * 374 * The hw generator calculates the error syndrome automatically. Therefore 375 * we need a special oob layout and handling. 376 */ 377static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, 378 uint8_t *buf, int oob_required, int page) 379{ 380 struct cafe_priv *cafe = mtd->priv; 381 unsigned int max_bitflips = 0; 382 383 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n", 384 cafe_readl(cafe, NAND_ECC_RESULT), 385 cafe_readl(cafe, NAND_ECC_SYN01)); 386 387 chip->read_buf(mtd, buf, mtd->writesize); 388 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 389 390 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) { 391 unsigned short syn[8], pat[4]; 392 int pos[4]; 393 u8 *oob = chip->oob_poi; 394 int i, n; 395 396 for (i=0; i<8; i+=2) { 397 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2)); 398 syn[i] = cafe->rs->index_of[tmp & 0xfff]; 399 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff]; 400 } 401 402 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0, 403 pat); 404 405 for (i = 0; i < n; i++) { 406 int p = pos[i]; 407 408 /* The 12-bit symbols are mapped to bytes here */ 409 410 if (p > 1374) { 411 /* out of range */ 412 n = -1374; 413 } else if (p == 0) { 414 /* high four bits do not correspond to data */ 415 if (pat[i] > 0xff) 416 n = -2048; 417 else 418 buf[0] ^= pat[i]; 419 } else if (p == 1365) { 420 buf[2047] ^= pat[i] >> 4; 421 oob[0] ^= pat[i] << 4; 422 } else if (p > 1365) { 423 if ((p & 1) == 1) { 424 oob[3*p/2 - 2048] ^= pat[i] >> 4; 425 oob[3*p/2 - 2047] ^= pat[i] << 4; 426 } else { 427 oob[3*p/2 - 2049] ^= pat[i] >> 8; 428 oob[3*p/2 - 2048] ^= pat[i]; 429 } 430 } else if ((p & 1) == 1) { 431 buf[3*p/2] ^= pat[i] >> 4; 432 buf[3*p/2 + 1] ^= pat[i] << 4; 433 } else { 434 buf[3*p/2 - 1] ^= pat[i] >> 8; 435 buf[3*p/2] ^= pat[i]; 436 } 437 } 438 439 if (n < 0) { 440 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n", 441 cafe_readl(cafe, NAND_ADDR2) * 2048); 442 for (i = 0; i < 0x5c; i += 4) 443 printk("Register %x: %08x\n", i, readl(cafe->mmio + i)); 444 mtd->ecc_stats.failed++; 445 } else { 446 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n); 447 mtd->ecc_stats.corrected += n; 448 max_bitflips = max_t(unsigned int, max_bitflips, n); 449 } 450 } 451 452 return max_bitflips; 453} 454 455static struct nand_ecclayout cafe_oobinfo_2048 = { 456 .eccbytes = 14, 457 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 458 .oobfree = {{14, 50}} 459}; 460 461/* Ick. The BBT code really ought to be able to work this bit out 462 for itself from the above, at least for the 2KiB case */ 463static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' }; 464static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' }; 465 466static uint8_t cafe_bbt_pattern_512[] = { 0xBB }; 467static uint8_t cafe_mirror_pattern_512[] = { 0xBC }; 468 469 470static struct nand_bbt_descr cafe_bbt_main_descr_2048 = { 471 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 472 | NAND_BBT_2BIT | NAND_BBT_VERSION, 473 .offs = 14, 474 .len = 4, 475 .veroffs = 18, 476 .maxblocks = 4, 477 .pattern = cafe_bbt_pattern_2048 478}; 479 480static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = { 481 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 482 | NAND_BBT_2BIT | NAND_BBT_VERSION, 483 .offs = 14, 484 .len = 4, 485 .veroffs = 18, 486 .maxblocks = 4, 487 .pattern = cafe_mirror_pattern_2048 488}; 489 490static struct nand_ecclayout cafe_oobinfo_512 = { 491 .eccbytes = 14, 492 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 493 .oobfree = {{14, 2}} 494}; 495 496static struct nand_bbt_descr cafe_bbt_main_descr_512 = { 497 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 498 | NAND_BBT_2BIT | NAND_BBT_VERSION, 499 .offs = 14, 500 .len = 1, 501 .veroffs = 15, 502 .maxblocks = 4, 503 .pattern = cafe_bbt_pattern_512 504}; 505 506static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = { 507 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 508 | NAND_BBT_2BIT | NAND_BBT_VERSION, 509 .offs = 14, 510 .len = 1, 511 .veroffs = 15, 512 .maxblocks = 4, 513 .pattern = cafe_mirror_pattern_512 514}; 515 516 517static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd, 518 struct nand_chip *chip, 519 const uint8_t *buf, int oob_required) 520{ 521 struct cafe_priv *cafe = mtd->priv; 522 523 chip->write_buf(mtd, buf, mtd->writesize); 524 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 525 526 /* Set up ECC autogeneration */ 527 cafe->ctl2 |= (1<<30); 528 529 return 0; 530} 531 532static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip) 533{ 534 return 0; 535} 536 537/* F_2[X]/(X**6+X+1) */ 538static unsigned short gf64_mul(u8 a, u8 b) 539{ 540 u8 c; 541 unsigned int i; 542 543 c = 0; 544 for (i = 0; i < 6; i++) { 545 if (a & 1) 546 c ^= b; 547 a >>= 1; 548 b <<= 1; 549 if ((b & 0x40) != 0) 550 b ^= 0x43; 551 } 552 553 return c; 554} 555 556/* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */ 557static u16 gf4096_mul(u16 a, u16 b) 558{ 559 u8 ah, al, bh, bl, ch, cl; 560 561 ah = a >> 6; 562 al = a & 0x3f; 563 bh = b >> 6; 564 bl = b & 0x3f; 565 566 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl); 567 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl); 568 569 return (ch << 6) ^ cl; 570} 571 572static int cafe_mul(int x) 573{ 574 if (x == 0) 575 return 1; 576 return gf4096_mul(x, 0xe01); 577} 578 579static int cafe_nand_probe(struct pci_dev *pdev, 580 const struct pci_device_id *ent) 581{ 582 struct mtd_info *mtd; 583 struct cafe_priv *cafe; 584 uint32_t ctrl; 585 int err = 0; 586 int old_dma; 587 struct nand_buffers *nbuf; 588 589 /* Very old versions shared the same PCI ident for all three 590 functions on the chip. Verify the class too... */ 591 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH) 592 return -ENODEV; 593 594 err = pci_enable_device(pdev); 595 if (err) 596 return err; 597 598 pci_set_master(pdev); 599 600 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL); 601 if (!mtd) 602 return -ENOMEM; 603 cafe = (void *)(&mtd[1]); 604 605 mtd->dev.parent = &pdev->dev; 606 mtd->priv = cafe; 607 mtd->owner = THIS_MODULE; 608 609 cafe->pdev = pdev; 610 cafe->mmio = pci_iomap(pdev, 0, 0); 611 if (!cafe->mmio) { 612 dev_warn(&pdev->dev, "failed to iomap\n"); 613 err = -ENOMEM; 614 goto out_free_mtd; 615 } 616 617 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8); 618 if (!cafe->rs) { 619 err = -ENOMEM; 620 goto out_ior; 621 } 622 623 cafe->nand.cmdfunc = cafe_nand_cmdfunc; 624 cafe->nand.dev_ready = cafe_device_ready; 625 cafe->nand.read_byte = cafe_read_byte; 626 cafe->nand.read_buf = cafe_read_buf; 627 cafe->nand.write_buf = cafe_write_buf; 628 cafe->nand.select_chip = cafe_select_chip; 629 630 cafe->nand.chip_delay = 0; 631 632 /* Enable the following for a flash based bad block table */ 633 cafe->nand.bbt_options = NAND_BBT_USE_FLASH; 634 cafe->nand.options = NAND_OWN_BUFFERS; 635 636 if (skipbbt) { 637 cafe->nand.options |= NAND_SKIP_BBTSCAN; 638 cafe->nand.block_bad = cafe_nand_block_bad; 639 } 640 641 if (numtimings && numtimings != 3) { 642 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings); 643 } 644 645 if (numtimings == 3) { 646 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n", 647 timing[0], timing[1], timing[2]); 648 } else { 649 timing[0] = cafe_readl(cafe, NAND_TIMING1); 650 timing[1] = cafe_readl(cafe, NAND_TIMING2); 651 timing[2] = cafe_readl(cafe, NAND_TIMING3); 652 653 if (timing[0] | timing[1] | timing[2]) { 654 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", 655 timing[0], timing[1], timing[2]); 656 } else { 657 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n"); 658 timing[0] = timing[1] = timing[2] = 0xffffffff; 659 } 660 } 661 662 /* Start off by resetting the NAND controller completely */ 663 cafe_writel(cafe, 1, NAND_RESET); 664 cafe_writel(cafe, 0, NAND_RESET); 665 666 cafe_writel(cafe, timing[0], NAND_TIMING1); 667 cafe_writel(cafe, timing[1], NAND_TIMING2); 668 cafe_writel(cafe, timing[2], NAND_TIMING3); 669 670 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); 671 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED, 672 "CAFE NAND", mtd); 673 if (err) { 674 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq); 675 goto out_ior; 676 } 677 678 /* Disable master reset, enable NAND clock */ 679 ctrl = cafe_readl(cafe, GLOBAL_CTRL); 680 ctrl &= 0xffffeff0; 681 ctrl |= 0x00007000; 682 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); 683 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); 684 cafe_writel(cafe, 0, NAND_DMA_CTRL); 685 686 cafe_writel(cafe, 0x7006, GLOBAL_CTRL); 687 cafe_writel(cafe, 0x700a, GLOBAL_CTRL); 688 689 /* Enable NAND IRQ in global IRQ mask register */ 690 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); 691 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n", 692 cafe_readl(cafe, GLOBAL_CTRL), 693 cafe_readl(cafe, GLOBAL_IRQ_MASK)); 694 695 /* Do not use the DMA for the nand_scan_ident() */ 696 old_dma = usedma; 697 usedma = 0; 698 699 /* Scan to find existence of the device */ 700 if (nand_scan_ident(mtd, 2, NULL)) { 701 err = -ENXIO; 702 goto out_irq; 703 } 704 705 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 706 2112 + sizeof(struct nand_buffers) + 707 mtd->writesize + mtd->oobsize, 708 &cafe->dmaaddr, GFP_KERNEL); 709 if (!cafe->dmabuf) { 710 err = -ENOMEM; 711 goto out_irq; 712 } 713 cafe->nand.buffers = nbuf = (void *)cafe->dmabuf + 2112; 714 715 /* Set up DMA address */ 716 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); 717 if (sizeof(cafe->dmaaddr) > 4) 718 /* Shift in two parts to shut the compiler up */ 719 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); 720 else 721 cafe_writel(cafe, 0, NAND_DMA_ADDR1); 722 723 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n", 724 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf); 725 726 /* this driver does not need the @ecccalc and @ecccode */ 727 nbuf->ecccalc = NULL; 728 nbuf->ecccode = NULL; 729 nbuf->databuf = (uint8_t *)(nbuf + 1); 730 731 /* Restore the DMA flag */ 732 usedma = old_dma; 733 734 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */ 735 if (mtd->writesize == 2048) 736 cafe->ctl2 |= 1<<29; /* 2KiB page size */ 737 738 /* Set up ECC according to the type of chip we found */ 739 if (mtd->writesize == 2048) { 740 cafe->nand.ecc.layout = &cafe_oobinfo_2048; 741 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048; 742 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048; 743 } else if (mtd->writesize == 512) { 744 cafe->nand.ecc.layout = &cafe_oobinfo_512; 745 cafe->nand.bbt_td = &cafe_bbt_main_descr_512; 746 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512; 747 } else { 748 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n", 749 mtd->writesize); 750 goto out_free_dma; 751 } 752 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 753 cafe->nand.ecc.size = mtd->writesize; 754 cafe->nand.ecc.bytes = 14; 755 cafe->nand.ecc.strength = 4; 756 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug; 757 cafe->nand.ecc.calculate = (void *)cafe_nand_bug; 758 cafe->nand.ecc.correct = (void *)cafe_nand_bug; 759 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel; 760 cafe->nand.ecc.write_oob = cafe_nand_write_oob; 761 cafe->nand.ecc.read_page = cafe_nand_read_page; 762 cafe->nand.ecc.read_oob = cafe_nand_read_oob; 763 764 err = nand_scan_tail(mtd); 765 if (err) 766 goto out_free_dma; 767 768 pci_set_drvdata(pdev, mtd); 769 770 mtd->name = "cafe_nand"; 771 mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0); 772 773 goto out; 774 775 out_free_dma: 776 dma_free_coherent(&cafe->pdev->dev, 777 2112 + sizeof(struct nand_buffers) + 778 mtd->writesize + mtd->oobsize, 779 cafe->dmabuf, cafe->dmaaddr); 780 out_irq: 781 /* Disable NAND IRQ in global IRQ mask register */ 782 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); 783 free_irq(pdev->irq, mtd); 784 out_ior: 785 pci_iounmap(pdev, cafe->mmio); 786 out_free_mtd: 787 kfree(mtd); 788 out: 789 return err; 790} 791 792static void cafe_nand_remove(struct pci_dev *pdev) 793{ 794 struct mtd_info *mtd = pci_get_drvdata(pdev); 795 struct cafe_priv *cafe = mtd->priv; 796 797 /* Disable NAND IRQ in global IRQ mask register */ 798 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK); 799 free_irq(pdev->irq, mtd); 800 nand_release(mtd); 801 free_rs(cafe->rs); 802 pci_iounmap(pdev, cafe->mmio); 803 dma_free_coherent(&cafe->pdev->dev, 804 2112 + sizeof(struct nand_buffers) + 805 mtd->writesize + mtd->oobsize, 806 cafe->dmabuf, cafe->dmaaddr); 807 kfree(mtd); 808} 809 810static const struct pci_device_id cafe_nand_tbl[] = { 811 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND, 812 PCI_ANY_ID, PCI_ANY_ID }, 813 { } 814}; 815 816MODULE_DEVICE_TABLE(pci, cafe_nand_tbl); 817 818static int cafe_nand_resume(struct pci_dev *pdev) 819{ 820 uint32_t ctrl; 821 struct mtd_info *mtd = pci_get_drvdata(pdev); 822 struct cafe_priv *cafe = mtd->priv; 823 824 /* Start off by resetting the NAND controller completely */ 825 cafe_writel(cafe, 1, NAND_RESET); 826 cafe_writel(cafe, 0, NAND_RESET); 827 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK); 828 829 /* Restore timing configuration */ 830 cafe_writel(cafe, timing[0], NAND_TIMING1); 831 cafe_writel(cafe, timing[1], NAND_TIMING2); 832 cafe_writel(cafe, timing[2], NAND_TIMING3); 833 834 /* Disable master reset, enable NAND clock */ 835 ctrl = cafe_readl(cafe, GLOBAL_CTRL); 836 ctrl &= 0xffffeff0; 837 ctrl |= 0x00007000; 838 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL); 839 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL); 840 cafe_writel(cafe, 0, NAND_DMA_CTRL); 841 cafe_writel(cafe, 0x7006, GLOBAL_CTRL); 842 cafe_writel(cafe, 0x700a, GLOBAL_CTRL); 843 844 /* Set up DMA address */ 845 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0); 846 if (sizeof(cafe->dmaaddr) > 4) 847 /* Shift in two parts to shut the compiler up */ 848 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1); 849 else 850 cafe_writel(cafe, 0, NAND_DMA_ADDR1); 851 852 /* Enable NAND IRQ in global IRQ mask register */ 853 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK); 854 return 0; 855} 856 857static struct pci_driver cafe_nand_pci_driver = { 858 .name = "CAFÉ NAND", 859 .id_table = cafe_nand_tbl, 860 .probe = cafe_nand_probe, 861 .remove = cafe_nand_remove, 862 .resume = cafe_nand_resume, 863}; 864 865module_pci_driver(cafe_nand_pci_driver); 866 867MODULE_LICENSE("GPL"); 868MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>"); 869MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip"); 870