1/* 2 * SuperH FLCTL nand controller 3 * 4 * Copyright (c) 2008 Renesas Solutions Corp. 5 * Copyright (c) 2008 Atom Create Engineering Co., Ltd. 6 * 7 * Based on fsl_elbc_nand.c, Copyright (c) 2006-2007 Freescale Semiconductor 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; version 2 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 21 * 22 */ 23 24#include <linux/module.h> 25#include <linux/kernel.h> 26#include <linux/completion.h> 27#include <linux/delay.h> 28#include <linux/dmaengine.h> 29#include <linux/dma-mapping.h> 30#include <linux/interrupt.h> 31#include <linux/io.h> 32#include <linux/of.h> 33#include <linux/of_device.h> 34#include <linux/of_mtd.h> 35#include <linux/platform_device.h> 36#include <linux/pm_runtime.h> 37#include <linux/sh_dma.h> 38#include <linux/slab.h> 39#include <linux/string.h> 40 41#include <linux/mtd/mtd.h> 42#include <linux/mtd/nand.h> 43#include <linux/mtd/partitions.h> 44#include <linux/mtd/sh_flctl.h> 45 46static struct nand_ecclayout flctl_4secc_oob_16 = { 47 .eccbytes = 10, 48 .eccpos = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, 49 .oobfree = { 50 {.offset = 12, 51 . length = 4} }, 52}; 53 54static struct nand_ecclayout flctl_4secc_oob_64 = { 55 .eccbytes = 4 * 10, 56 .eccpos = { 57 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 58 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 59 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 60 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }, 61 .oobfree = { 62 {.offset = 2, .length = 4}, 63 {.offset = 16, .length = 6}, 64 {.offset = 32, .length = 6}, 65 {.offset = 48, .length = 6} }, 66}; 67 68static uint8_t scan_ff_pattern[] = { 0xff, 0xff }; 69 70static struct nand_bbt_descr flctl_4secc_smallpage = { 71 .options = NAND_BBT_SCAN2NDPAGE, 72 .offs = 11, 73 .len = 1, 74 .pattern = scan_ff_pattern, 75}; 76 77static struct nand_bbt_descr flctl_4secc_largepage = { 78 .options = NAND_BBT_SCAN2NDPAGE, 79 .offs = 0, 80 .len = 2, 81 .pattern = scan_ff_pattern, 82}; 83 84static void empty_fifo(struct sh_flctl *flctl) 85{ 86 writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl)); 87 writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); 88} 89 90static void start_translation(struct sh_flctl *flctl) 91{ 92 writeb(TRSTRT, FLTRCR(flctl)); 93} 94 95static void timeout_error(struct sh_flctl *flctl, const char *str) 96{ 97 dev_err(&flctl->pdev->dev, "Timeout occurred in %s\n", str); 98} 99 100static void wait_completion(struct sh_flctl *flctl) 101{ 102 uint32_t timeout = LOOP_TIMEOUT_MAX; 103 104 while (timeout--) { 105 if (readb(FLTRCR(flctl)) & TREND) { 106 writeb(0x0, FLTRCR(flctl)); 107 return; 108 } 109 udelay(1); 110 } 111 112 timeout_error(flctl, __func__); 113 writeb(0x0, FLTRCR(flctl)); 114} 115 116static void flctl_dma_complete(void *param) 117{ 118 struct sh_flctl *flctl = param; 119 120 complete(&flctl->dma_complete); 121} 122 123static void flctl_release_dma(struct sh_flctl *flctl) 124{ 125 if (flctl->chan_fifo0_rx) { 126 dma_release_channel(flctl->chan_fifo0_rx); 127 flctl->chan_fifo0_rx = NULL; 128 } 129 if (flctl->chan_fifo0_tx) { 130 dma_release_channel(flctl->chan_fifo0_tx); 131 flctl->chan_fifo0_tx = NULL; 132 } 133} 134 135static void flctl_setup_dma(struct sh_flctl *flctl) 136{ 137 dma_cap_mask_t mask; 138 struct dma_slave_config cfg; 139 struct platform_device *pdev = flctl->pdev; 140 struct sh_flctl_platform_data *pdata = dev_get_platdata(&pdev->dev); 141 int ret; 142 143 if (!pdata) 144 return; 145 146 if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0) 147 return; 148 149 /* We can only either use DMA for both Tx and Rx or not use it at all */ 150 dma_cap_zero(mask); 151 dma_cap_set(DMA_SLAVE, mask); 152 153 flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter, 154 (void *)(uintptr_t)pdata->slave_id_fifo0_tx); 155 dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__, 156 flctl->chan_fifo0_tx); 157 158 if (!flctl->chan_fifo0_tx) 159 return; 160 161 memset(&cfg, 0, sizeof(cfg)); 162 cfg.direction = DMA_MEM_TO_DEV; 163 cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl); 164 cfg.src_addr = 0; 165 ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg); 166 if (ret < 0) 167 goto err; 168 169 flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter, 170 (void *)(uintptr_t)pdata->slave_id_fifo0_rx); 171 dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__, 172 flctl->chan_fifo0_rx); 173 174 if (!flctl->chan_fifo0_rx) 175 goto err; 176 177 cfg.direction = DMA_DEV_TO_MEM; 178 cfg.dst_addr = 0; 179 cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl); 180 ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg); 181 if (ret < 0) 182 goto err; 183 184 init_completion(&flctl->dma_complete); 185 186 return; 187 188err: 189 flctl_release_dma(flctl); 190} 191 192static void set_addr(struct mtd_info *mtd, int column, int page_addr) 193{ 194 struct sh_flctl *flctl = mtd_to_flctl(mtd); 195 uint32_t addr = 0; 196 197 if (column == -1) { 198 addr = page_addr; /* ERASE1 */ 199 } else if (page_addr != -1) { 200 /* SEQIN, READ0, etc.. */ 201 if (flctl->chip.options & NAND_BUSWIDTH_16) 202 column >>= 1; 203 if (flctl->page_size) { 204 addr = column & 0x0FFF; 205 addr |= (page_addr & 0xff) << 16; 206 addr |= ((page_addr >> 8) & 0xff) << 24; 207 /* big than 128MB */ 208 if (flctl->rw_ADRCNT == ADRCNT2_E) { 209 uint32_t addr2; 210 addr2 = (page_addr >> 16) & 0xff; 211 writel(addr2, FLADR2(flctl)); 212 } 213 } else { 214 addr = column; 215 addr |= (page_addr & 0xff) << 8; 216 addr |= ((page_addr >> 8) & 0xff) << 16; 217 addr |= ((page_addr >> 16) & 0xff) << 24; 218 } 219 } 220 writel(addr, FLADR(flctl)); 221} 222 223static void wait_rfifo_ready(struct sh_flctl *flctl) 224{ 225 uint32_t timeout = LOOP_TIMEOUT_MAX; 226 227 while (timeout--) { 228 uint32_t val; 229 /* check FIFO */ 230 val = readl(FLDTCNTR(flctl)) >> 16; 231 if (val & 0xFF) 232 return; 233 udelay(1); 234 } 235 timeout_error(flctl, __func__); 236} 237 238static void wait_wfifo_ready(struct sh_flctl *flctl) 239{ 240 uint32_t len, timeout = LOOP_TIMEOUT_MAX; 241 242 while (timeout--) { 243 /* check FIFO */ 244 len = (readl(FLDTCNTR(flctl)) >> 16) & 0xFF; 245 if (len >= 4) 246 return; 247 udelay(1); 248 } 249 timeout_error(flctl, __func__); 250} 251 252static enum flctl_ecc_res_t wait_recfifo_ready 253 (struct sh_flctl *flctl, int sector_number) 254{ 255 uint32_t timeout = LOOP_TIMEOUT_MAX; 256 void __iomem *ecc_reg[4]; 257 int i; 258 int state = FL_SUCCESS; 259 uint32_t data, size; 260 261 /* 262 * First this loops checks in FLDTCNTR if we are ready to read out the 263 * oob data. This is the case if either all went fine without errors or 264 * if the bottom part of the loop corrected the errors or marked them as 265 * uncorrectable and the controller is given time to push the data into 266 * the FIFO. 267 */ 268 while (timeout--) { 269 /* check if all is ok and we can read out the OOB */ 270 size = readl(FLDTCNTR(flctl)) >> 24; 271 if ((size & 0xFF) == 4) 272 return state; 273 274 /* check if a correction code has been calculated */ 275 if (!(readl(FL4ECCCR(flctl)) & _4ECCEND)) { 276 /* 277 * either we wait for the fifo to be filled or a 278 * correction pattern is being generated 279 */ 280 udelay(1); 281 continue; 282 } 283 284 /* check for an uncorrectable error */ 285 if (readl(FL4ECCCR(flctl)) & _4ECCFA) { 286 /* check if we face a non-empty page */ 287 for (i = 0; i < 512; i++) { 288 if (flctl->done_buff[i] != 0xff) { 289 state = FL_ERROR; /* can't correct */ 290 break; 291 } 292 } 293 294 if (state == FL_SUCCESS) 295 dev_dbg(&flctl->pdev->dev, 296 "reading empty sector %d, ecc error ignored\n", 297 sector_number); 298 299 writel(0, FL4ECCCR(flctl)); 300 continue; 301 } 302 303 /* start error correction */ 304 ecc_reg[0] = FL4ECCRESULT0(flctl); 305 ecc_reg[1] = FL4ECCRESULT1(flctl); 306 ecc_reg[2] = FL4ECCRESULT2(flctl); 307 ecc_reg[3] = FL4ECCRESULT3(flctl); 308 309 for (i = 0; i < 3; i++) { 310 uint8_t org; 311 unsigned int index; 312 313 data = readl(ecc_reg[i]); 314 315 if (flctl->page_size) 316 index = (512 * sector_number) + 317 (data >> 16); 318 else 319 index = data >> 16; 320 321 org = flctl->done_buff[index]; 322 flctl->done_buff[index] = org ^ (data & 0xFF); 323 } 324 state = FL_REPAIRABLE; 325 writel(0, FL4ECCCR(flctl)); 326 } 327 328 timeout_error(flctl, __func__); 329 return FL_TIMEOUT; /* timeout */ 330} 331 332static void wait_wecfifo_ready(struct sh_flctl *flctl) 333{ 334 uint32_t timeout = LOOP_TIMEOUT_MAX; 335 uint32_t len; 336 337 while (timeout--) { 338 /* check FLECFIFO */ 339 len = (readl(FLDTCNTR(flctl)) >> 24) & 0xFF; 340 if (len >= 4) 341 return; 342 udelay(1); 343 } 344 timeout_error(flctl, __func__); 345} 346 347static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf, 348 int len, enum dma_data_direction dir) 349{ 350 struct dma_async_tx_descriptor *desc = NULL; 351 struct dma_chan *chan; 352 enum dma_transfer_direction tr_dir; 353 dma_addr_t dma_addr; 354 dma_cookie_t cookie = -EINVAL; 355 uint32_t reg; 356 int ret; 357 358 if (dir == DMA_FROM_DEVICE) { 359 chan = flctl->chan_fifo0_rx; 360 tr_dir = DMA_DEV_TO_MEM; 361 } else { 362 chan = flctl->chan_fifo0_tx; 363 tr_dir = DMA_MEM_TO_DEV; 364 } 365 366 dma_addr = dma_map_single(chan->device->dev, buf, len, dir); 367 368 if (dma_addr) 369 desc = dmaengine_prep_slave_single(chan, dma_addr, len, 370 tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 371 372 if (desc) { 373 reg = readl(FLINTDMACR(flctl)); 374 reg |= DREQ0EN; 375 writel(reg, FLINTDMACR(flctl)); 376 377 desc->callback = flctl_dma_complete; 378 desc->callback_param = flctl; 379 cookie = dmaengine_submit(desc); 380 381 dma_async_issue_pending(chan); 382 } else { 383 /* DMA failed, fall back to PIO */ 384 flctl_release_dma(flctl); 385 dev_warn(&flctl->pdev->dev, 386 "DMA failed, falling back to PIO\n"); 387 ret = -EIO; 388 goto out; 389 } 390 391 ret = 392 wait_for_completion_timeout(&flctl->dma_complete, 393 msecs_to_jiffies(3000)); 394 395 if (ret <= 0) { 396 dmaengine_terminate_all(chan); 397 dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n"); 398 } 399 400out: 401 reg = readl(FLINTDMACR(flctl)); 402 reg &= ~DREQ0EN; 403 writel(reg, FLINTDMACR(flctl)); 404 405 dma_unmap_single(chan->device->dev, dma_addr, len, dir); 406 407 /* ret > 0 is success */ 408 return ret; 409} 410 411static void read_datareg(struct sh_flctl *flctl, int offset) 412{ 413 unsigned long data; 414 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset]; 415 416 wait_completion(flctl); 417 418 data = readl(FLDATAR(flctl)); 419 *buf = le32_to_cpu(data); 420} 421 422static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset) 423{ 424 int i, len_4align; 425 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset]; 426 427 len_4align = (rlen + 3) / 4; 428 429 /* initiate DMA transfer */ 430 if (flctl->chan_fifo0_rx && rlen >= 32 && 431 flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM) > 0) 432 goto convert; /* DMA success */ 433 434 /* do polling transfer */ 435 for (i = 0; i < len_4align; i++) { 436 wait_rfifo_ready(flctl); 437 buf[i] = readl(FLDTFIFO(flctl)); 438 } 439 440convert: 441 for (i = 0; i < len_4align; i++) 442 buf[i] = be32_to_cpu(buf[i]); 443} 444 445static enum flctl_ecc_res_t read_ecfiforeg 446 (struct sh_flctl *flctl, uint8_t *buff, int sector) 447{ 448 int i; 449 enum flctl_ecc_res_t res; 450 unsigned long *ecc_buf = (unsigned long *)buff; 451 452 res = wait_recfifo_ready(flctl , sector); 453 454 if (res != FL_ERROR) { 455 for (i = 0; i < 4; i++) { 456 ecc_buf[i] = readl(FLECFIFO(flctl)); 457 ecc_buf[i] = be32_to_cpu(ecc_buf[i]); 458 } 459 } 460 461 return res; 462} 463 464static void write_fiforeg(struct sh_flctl *flctl, int rlen, 465 unsigned int offset) 466{ 467 int i, len_4align; 468 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset]; 469 470 len_4align = (rlen + 3) / 4; 471 for (i = 0; i < len_4align; i++) { 472 wait_wfifo_ready(flctl); 473 writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl)); 474 } 475} 476 477static void write_ec_fiforeg(struct sh_flctl *flctl, int rlen, 478 unsigned int offset) 479{ 480 int i, len_4align; 481 unsigned long *buf = (unsigned long *)&flctl->done_buff[offset]; 482 483 len_4align = (rlen + 3) / 4; 484 485 for (i = 0; i < len_4align; i++) 486 buf[i] = cpu_to_be32(buf[i]); 487 488 /* initiate DMA transfer */ 489 if (flctl->chan_fifo0_tx && rlen >= 32 && 490 flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV) > 0) 491 return; /* DMA success */ 492 493 /* do polling transfer */ 494 for (i = 0; i < len_4align; i++) { 495 wait_wecfifo_ready(flctl); 496 writel(buf[i], FLECFIFO(flctl)); 497 } 498} 499 500static void set_cmd_regs(struct mtd_info *mtd, uint32_t cmd, uint32_t flcmcdr_val) 501{ 502 struct sh_flctl *flctl = mtd_to_flctl(mtd); 503 uint32_t flcmncr_val = flctl->flcmncr_base & ~SEL_16BIT; 504 uint32_t flcmdcr_val, addr_len_bytes = 0; 505 506 /* Set SNAND bit if page size is 2048byte */ 507 if (flctl->page_size) 508 flcmncr_val |= SNAND_E; 509 else 510 flcmncr_val &= ~SNAND_E; 511 512 /* default FLCMDCR val */ 513 flcmdcr_val = DOCMD1_E | DOADR_E; 514 515 /* Set for FLCMDCR */ 516 switch (cmd) { 517 case NAND_CMD_ERASE1: 518 addr_len_bytes = flctl->erase_ADRCNT; 519 flcmdcr_val |= DOCMD2_E; 520 break; 521 case NAND_CMD_READ0: 522 case NAND_CMD_READOOB: 523 case NAND_CMD_RNDOUT: 524 addr_len_bytes = flctl->rw_ADRCNT; 525 flcmdcr_val |= CDSRC_E; 526 if (flctl->chip.options & NAND_BUSWIDTH_16) 527 flcmncr_val |= SEL_16BIT; 528 break; 529 case NAND_CMD_SEQIN: 530 /* This case is that cmd is READ0 or READ1 or READ00 */ 531 flcmdcr_val &= ~DOADR_E; /* ONLY execute 1st cmd */ 532 break; 533 case NAND_CMD_PAGEPROG: 534 addr_len_bytes = flctl->rw_ADRCNT; 535 flcmdcr_val |= DOCMD2_E | CDSRC_E | SELRW; 536 if (flctl->chip.options & NAND_BUSWIDTH_16) 537 flcmncr_val |= SEL_16BIT; 538 break; 539 case NAND_CMD_READID: 540 flcmncr_val &= ~SNAND_E; 541 flcmdcr_val |= CDSRC_E; 542 addr_len_bytes = ADRCNT_1; 543 break; 544 case NAND_CMD_STATUS: 545 case NAND_CMD_RESET: 546 flcmncr_val &= ~SNAND_E; 547 flcmdcr_val &= ~(DOADR_E | DOSR_E); 548 break; 549 default: 550 break; 551 } 552 553 /* Set address bytes parameter */ 554 flcmdcr_val |= addr_len_bytes; 555 556 /* Now actually write */ 557 writel(flcmncr_val, FLCMNCR(flctl)); 558 writel(flcmdcr_val, FLCMDCR(flctl)); 559 writel(flcmcdr_val, FLCMCDR(flctl)); 560} 561 562static int flctl_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 563 uint8_t *buf, int oob_required, int page) 564{ 565 chip->read_buf(mtd, buf, mtd->writesize); 566 if (oob_required) 567 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 568 return 0; 569} 570 571static int flctl_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, 572 const uint8_t *buf, int oob_required) 573{ 574 chip->write_buf(mtd, buf, mtd->writesize); 575 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 576 return 0; 577} 578 579static void execmd_read_page_sector(struct mtd_info *mtd, int page_addr) 580{ 581 struct sh_flctl *flctl = mtd_to_flctl(mtd); 582 int sector, page_sectors; 583 enum flctl_ecc_res_t ecc_result; 584 585 page_sectors = flctl->page_size ? 4 : 1; 586 587 set_cmd_regs(mtd, NAND_CMD_READ0, 588 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0); 589 590 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE | _4ECCCORRECT, 591 FLCMNCR(flctl)); 592 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl)); 593 writel(page_addr << 2, FLADR(flctl)); 594 595 empty_fifo(flctl); 596 start_translation(flctl); 597 598 for (sector = 0; sector < page_sectors; sector++) { 599 read_fiforeg(flctl, 512, 512 * sector); 600 601 ecc_result = read_ecfiforeg(flctl, 602 &flctl->done_buff[mtd->writesize + 16 * sector], 603 sector); 604 605 switch (ecc_result) { 606 case FL_REPAIRABLE: 607 dev_info(&flctl->pdev->dev, 608 "applied ecc on page 0x%x", page_addr); 609 flctl->mtd.ecc_stats.corrected++; 610 break; 611 case FL_ERROR: 612 dev_warn(&flctl->pdev->dev, 613 "page 0x%x contains corrupted data\n", 614 page_addr); 615 flctl->mtd.ecc_stats.failed++; 616 break; 617 default: 618 ; 619 } 620 } 621 622 wait_completion(flctl); 623 624 writel(readl(FLCMNCR(flctl)) & ~(ACM_SACCES_MODE | _4ECCCORRECT), 625 FLCMNCR(flctl)); 626} 627 628static void execmd_read_oob(struct mtd_info *mtd, int page_addr) 629{ 630 struct sh_flctl *flctl = mtd_to_flctl(mtd); 631 int page_sectors = flctl->page_size ? 4 : 1; 632 int i; 633 634 set_cmd_regs(mtd, NAND_CMD_READ0, 635 (NAND_CMD_READSTART << 8) | NAND_CMD_READ0); 636 637 empty_fifo(flctl); 638 639 for (i = 0; i < page_sectors; i++) { 640 set_addr(mtd, (512 + 16) * i + 512 , page_addr); 641 writel(16, FLDTCNTR(flctl)); 642 643 start_translation(flctl); 644 read_fiforeg(flctl, 16, 16 * i); 645 wait_completion(flctl); 646 } 647} 648 649static void execmd_write_page_sector(struct mtd_info *mtd) 650{ 651 struct sh_flctl *flctl = mtd_to_flctl(mtd); 652 int page_addr = flctl->seqin_page_addr; 653 int sector, page_sectors; 654 655 page_sectors = flctl->page_size ? 4 : 1; 656 657 set_cmd_regs(mtd, NAND_CMD_PAGEPROG, 658 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN); 659 660 empty_fifo(flctl); 661 writel(readl(FLCMNCR(flctl)) | ACM_SACCES_MODE, FLCMNCR(flctl)); 662 writel(readl(FLCMDCR(flctl)) | page_sectors, FLCMDCR(flctl)); 663 writel(page_addr << 2, FLADR(flctl)); 664 start_translation(flctl); 665 666 for (sector = 0; sector < page_sectors; sector++) { 667 write_fiforeg(flctl, 512, 512 * sector); 668 write_ec_fiforeg(flctl, 16, mtd->writesize + 16 * sector); 669 } 670 671 wait_completion(flctl); 672 writel(readl(FLCMNCR(flctl)) & ~ACM_SACCES_MODE, FLCMNCR(flctl)); 673} 674 675static void execmd_write_oob(struct mtd_info *mtd) 676{ 677 struct sh_flctl *flctl = mtd_to_flctl(mtd); 678 int page_addr = flctl->seqin_page_addr; 679 int sector, page_sectors; 680 681 page_sectors = flctl->page_size ? 4 : 1; 682 683 set_cmd_regs(mtd, NAND_CMD_PAGEPROG, 684 (NAND_CMD_PAGEPROG << 8) | NAND_CMD_SEQIN); 685 686 for (sector = 0; sector < page_sectors; sector++) { 687 empty_fifo(flctl); 688 set_addr(mtd, sector * 528 + 512, page_addr); 689 writel(16, FLDTCNTR(flctl)); /* set read size */ 690 691 start_translation(flctl); 692 write_fiforeg(flctl, 16, 16 * sector); 693 wait_completion(flctl); 694 } 695} 696 697static void flctl_cmdfunc(struct mtd_info *mtd, unsigned int command, 698 int column, int page_addr) 699{ 700 struct sh_flctl *flctl = mtd_to_flctl(mtd); 701 uint32_t read_cmd = 0; 702 703 pm_runtime_get_sync(&flctl->pdev->dev); 704 705 flctl->read_bytes = 0; 706 if (command != NAND_CMD_PAGEPROG) 707 flctl->index = 0; 708 709 switch (command) { 710 case NAND_CMD_READ1: 711 case NAND_CMD_READ0: 712 if (flctl->hwecc) { 713 /* read page with hwecc */ 714 execmd_read_page_sector(mtd, page_addr); 715 break; 716 } 717 if (flctl->page_size) 718 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8) 719 | command); 720 else 721 set_cmd_regs(mtd, command, command); 722 723 set_addr(mtd, 0, page_addr); 724 725 flctl->read_bytes = mtd->writesize + mtd->oobsize; 726 if (flctl->chip.options & NAND_BUSWIDTH_16) 727 column >>= 1; 728 flctl->index += column; 729 goto read_normal_exit; 730 731 case NAND_CMD_READOOB: 732 if (flctl->hwecc) { 733 /* read page with hwecc */ 734 execmd_read_oob(mtd, page_addr); 735 break; 736 } 737 738 if (flctl->page_size) { 739 set_cmd_regs(mtd, command, (NAND_CMD_READSTART << 8) 740 | NAND_CMD_READ0); 741 set_addr(mtd, mtd->writesize, page_addr); 742 } else { 743 set_cmd_regs(mtd, command, command); 744 set_addr(mtd, 0, page_addr); 745 } 746 flctl->read_bytes = mtd->oobsize; 747 goto read_normal_exit; 748 749 case NAND_CMD_RNDOUT: 750 if (flctl->hwecc) 751 break; 752 753 if (flctl->page_size) 754 set_cmd_regs(mtd, command, (NAND_CMD_RNDOUTSTART << 8) 755 | command); 756 else 757 set_cmd_regs(mtd, command, command); 758 759 set_addr(mtd, column, 0); 760 761 flctl->read_bytes = mtd->writesize + mtd->oobsize - column; 762 goto read_normal_exit; 763 764 case NAND_CMD_READID: 765 set_cmd_regs(mtd, command, command); 766 767 /* READID is always performed using an 8-bit bus */ 768 if (flctl->chip.options & NAND_BUSWIDTH_16) 769 column <<= 1; 770 set_addr(mtd, column, 0); 771 772 flctl->read_bytes = 8; 773 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ 774 empty_fifo(flctl); 775 start_translation(flctl); 776 read_fiforeg(flctl, flctl->read_bytes, 0); 777 wait_completion(flctl); 778 break; 779 780 case NAND_CMD_ERASE1: 781 flctl->erase1_page_addr = page_addr; 782 break; 783 784 case NAND_CMD_ERASE2: 785 set_cmd_regs(mtd, NAND_CMD_ERASE1, 786 (command << 8) | NAND_CMD_ERASE1); 787 set_addr(mtd, -1, flctl->erase1_page_addr); 788 start_translation(flctl); 789 wait_completion(flctl); 790 break; 791 792 case NAND_CMD_SEQIN: 793 if (!flctl->page_size) { 794 /* output read command */ 795 if (column >= mtd->writesize) { 796 column -= mtd->writesize; 797 read_cmd = NAND_CMD_READOOB; 798 } else if (column < 256) { 799 read_cmd = NAND_CMD_READ0; 800 } else { 801 column -= 256; 802 read_cmd = NAND_CMD_READ1; 803 } 804 } 805 flctl->seqin_column = column; 806 flctl->seqin_page_addr = page_addr; 807 flctl->seqin_read_cmd = read_cmd; 808 break; 809 810 case NAND_CMD_PAGEPROG: 811 empty_fifo(flctl); 812 if (!flctl->page_size) { 813 set_cmd_regs(mtd, NAND_CMD_SEQIN, 814 flctl->seqin_read_cmd); 815 set_addr(mtd, -1, -1); 816 writel(0, FLDTCNTR(flctl)); /* set 0 size */ 817 start_translation(flctl); 818 wait_completion(flctl); 819 } 820 if (flctl->hwecc) { 821 /* write page with hwecc */ 822 if (flctl->seqin_column == mtd->writesize) 823 execmd_write_oob(mtd); 824 else if (!flctl->seqin_column) 825 execmd_write_page_sector(mtd); 826 else 827 printk(KERN_ERR "Invalid address !?\n"); 828 break; 829 } 830 set_cmd_regs(mtd, command, (command << 8) | NAND_CMD_SEQIN); 831 set_addr(mtd, flctl->seqin_column, flctl->seqin_page_addr); 832 writel(flctl->index, FLDTCNTR(flctl)); /* set write size */ 833 start_translation(flctl); 834 write_fiforeg(flctl, flctl->index, 0); 835 wait_completion(flctl); 836 break; 837 838 case NAND_CMD_STATUS: 839 set_cmd_regs(mtd, command, command); 840 set_addr(mtd, -1, -1); 841 842 flctl->read_bytes = 1; 843 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ 844 start_translation(flctl); 845 read_datareg(flctl, 0); /* read and end */ 846 break; 847 848 case NAND_CMD_RESET: 849 set_cmd_regs(mtd, command, command); 850 set_addr(mtd, -1, -1); 851 852 writel(0, FLDTCNTR(flctl)); /* set 0 size */ 853 start_translation(flctl); 854 wait_completion(flctl); 855 break; 856 857 default: 858 break; 859 } 860 goto runtime_exit; 861 862read_normal_exit: 863 writel(flctl->read_bytes, FLDTCNTR(flctl)); /* set read size */ 864 empty_fifo(flctl); 865 start_translation(flctl); 866 read_fiforeg(flctl, flctl->read_bytes, 0); 867 wait_completion(flctl); 868runtime_exit: 869 pm_runtime_put_sync(&flctl->pdev->dev); 870 return; 871} 872 873static void flctl_select_chip(struct mtd_info *mtd, int chipnr) 874{ 875 struct sh_flctl *flctl = mtd_to_flctl(mtd); 876 int ret; 877 878 switch (chipnr) { 879 case -1: 880 flctl->flcmncr_base &= ~CE0_ENABLE; 881 882 pm_runtime_get_sync(&flctl->pdev->dev); 883 writel(flctl->flcmncr_base, FLCMNCR(flctl)); 884 885 if (flctl->qos_request) { 886 dev_pm_qos_remove_request(&flctl->pm_qos); 887 flctl->qos_request = 0; 888 } 889 890 pm_runtime_put_sync(&flctl->pdev->dev); 891 break; 892 case 0: 893 flctl->flcmncr_base |= CE0_ENABLE; 894 895 if (!flctl->qos_request) { 896 ret = dev_pm_qos_add_request(&flctl->pdev->dev, 897 &flctl->pm_qos, 898 DEV_PM_QOS_RESUME_LATENCY, 899 100); 900 if (ret < 0) 901 dev_err(&flctl->pdev->dev, 902 "PM QoS request failed: %d\n", ret); 903 flctl->qos_request = 1; 904 } 905 906 if (flctl->holden) { 907 pm_runtime_get_sync(&flctl->pdev->dev); 908 writel(HOLDEN, FLHOLDCR(flctl)); 909 pm_runtime_put_sync(&flctl->pdev->dev); 910 } 911 break; 912 default: 913 BUG(); 914 } 915} 916 917static void flctl_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 918{ 919 struct sh_flctl *flctl = mtd_to_flctl(mtd); 920 921 memcpy(&flctl->done_buff[flctl->index], buf, len); 922 flctl->index += len; 923} 924 925static uint8_t flctl_read_byte(struct mtd_info *mtd) 926{ 927 struct sh_flctl *flctl = mtd_to_flctl(mtd); 928 uint8_t data; 929 930 data = flctl->done_buff[flctl->index]; 931 flctl->index++; 932 return data; 933} 934 935static uint16_t flctl_read_word(struct mtd_info *mtd) 936{ 937 struct sh_flctl *flctl = mtd_to_flctl(mtd); 938 uint16_t *buf = (uint16_t *)&flctl->done_buff[flctl->index]; 939 940 flctl->index += 2; 941 return *buf; 942} 943 944static void flctl_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 945{ 946 struct sh_flctl *flctl = mtd_to_flctl(mtd); 947 948 memcpy(buf, &flctl->done_buff[flctl->index], len); 949 flctl->index += len; 950} 951 952static int flctl_chip_init_tail(struct mtd_info *mtd) 953{ 954 struct sh_flctl *flctl = mtd_to_flctl(mtd); 955 struct nand_chip *chip = &flctl->chip; 956 957 if (mtd->writesize == 512) { 958 flctl->page_size = 0; 959 if (chip->chipsize > (32 << 20)) { 960 /* big than 32MB */ 961 flctl->rw_ADRCNT = ADRCNT_4; 962 flctl->erase_ADRCNT = ADRCNT_3; 963 } else if (chip->chipsize > (2 << 16)) { 964 /* big than 128KB */ 965 flctl->rw_ADRCNT = ADRCNT_3; 966 flctl->erase_ADRCNT = ADRCNT_2; 967 } else { 968 flctl->rw_ADRCNT = ADRCNT_2; 969 flctl->erase_ADRCNT = ADRCNT_1; 970 } 971 } else { 972 flctl->page_size = 1; 973 if (chip->chipsize > (128 << 20)) { 974 /* big than 128MB */ 975 flctl->rw_ADRCNT = ADRCNT2_E; 976 flctl->erase_ADRCNT = ADRCNT_3; 977 } else if (chip->chipsize > (8 << 16)) { 978 /* big than 512KB */ 979 flctl->rw_ADRCNT = ADRCNT_4; 980 flctl->erase_ADRCNT = ADRCNT_2; 981 } else { 982 flctl->rw_ADRCNT = ADRCNT_3; 983 flctl->erase_ADRCNT = ADRCNT_1; 984 } 985 } 986 987 if (flctl->hwecc) { 988 if (mtd->writesize == 512) { 989 chip->ecc.layout = &flctl_4secc_oob_16; 990 chip->badblock_pattern = &flctl_4secc_smallpage; 991 } else { 992 chip->ecc.layout = &flctl_4secc_oob_64; 993 chip->badblock_pattern = &flctl_4secc_largepage; 994 } 995 996 chip->ecc.size = 512; 997 chip->ecc.bytes = 10; 998 chip->ecc.strength = 4; 999 chip->ecc.read_page = flctl_read_page_hwecc; 1000 chip->ecc.write_page = flctl_write_page_hwecc; 1001 chip->ecc.mode = NAND_ECC_HW; 1002 1003 /* 4 symbols ECC enabled */ 1004 flctl->flcmncr_base |= _4ECCEN; 1005 } else { 1006 chip->ecc.mode = NAND_ECC_SOFT; 1007 } 1008 1009 return 0; 1010} 1011 1012static irqreturn_t flctl_handle_flste(int irq, void *dev_id) 1013{ 1014 struct sh_flctl *flctl = dev_id; 1015 1016 dev_err(&flctl->pdev->dev, "flste irq: %x\n", readl(FLINTDMACR(flctl))); 1017 writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); 1018 1019 return IRQ_HANDLED; 1020} 1021 1022struct flctl_soc_config { 1023 unsigned long flcmncr_val; 1024 unsigned has_hwecc:1; 1025 unsigned use_holden:1; 1026}; 1027 1028static struct flctl_soc_config flctl_sh7372_config = { 1029 .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL, 1030 .has_hwecc = 1, 1031 .use_holden = 1, 1032}; 1033 1034static const struct of_device_id of_flctl_match[] = { 1035 { .compatible = "renesas,shmobile-flctl-sh7372", 1036 .data = &flctl_sh7372_config }, 1037 {}, 1038}; 1039MODULE_DEVICE_TABLE(of, of_flctl_match); 1040 1041static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev) 1042{ 1043 const struct of_device_id *match; 1044 struct flctl_soc_config *config; 1045 struct sh_flctl_platform_data *pdata; 1046 struct device_node *dn = dev->of_node; 1047 int ret; 1048 1049 match = of_match_device(of_flctl_match, dev); 1050 if (match) 1051 config = (struct flctl_soc_config *)match->data; 1052 else { 1053 dev_err(dev, "%s: no OF configuration attached\n", __func__); 1054 return NULL; 1055 } 1056 1057 pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data), 1058 GFP_KERNEL); 1059 if (!pdata) 1060 return NULL; 1061 1062 /* set SoC specific options */ 1063 pdata->flcmncr_val = config->flcmncr_val; 1064 pdata->has_hwecc = config->has_hwecc; 1065 pdata->use_holden = config->use_holden; 1066 1067 /* parse user defined options */ 1068 ret = of_get_nand_bus_width(dn); 1069 if (ret == 16) 1070 pdata->flcmncr_val |= SEL_16BIT; 1071 else if (ret != 8) { 1072 dev_err(dev, "%s: invalid bus width\n", __func__); 1073 return NULL; 1074 } 1075 1076 return pdata; 1077} 1078 1079static int flctl_probe(struct platform_device *pdev) 1080{ 1081 struct resource *res; 1082 struct sh_flctl *flctl; 1083 struct mtd_info *flctl_mtd; 1084 struct nand_chip *nand; 1085 struct sh_flctl_platform_data *pdata; 1086 int ret; 1087 int irq; 1088 struct mtd_part_parser_data ppdata = {}; 1089 1090 flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL); 1091 if (!flctl) 1092 return -ENOMEM; 1093 1094 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1095 flctl->reg = devm_ioremap_resource(&pdev->dev, res); 1096 if (IS_ERR(flctl->reg)) 1097 return PTR_ERR(flctl->reg); 1098 1099 irq = platform_get_irq(pdev, 0); 1100 if (irq < 0) { 1101 dev_err(&pdev->dev, "failed to get flste irq data\n"); 1102 return -ENXIO; 1103 } 1104 1105 ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED, 1106 "flste", flctl); 1107 if (ret) { 1108 dev_err(&pdev->dev, "request interrupt failed.\n"); 1109 return ret; 1110 } 1111 1112 if (pdev->dev.of_node) 1113 pdata = flctl_parse_dt(&pdev->dev); 1114 else 1115 pdata = dev_get_platdata(&pdev->dev); 1116 1117 if (!pdata) { 1118 dev_err(&pdev->dev, "no setup data defined\n"); 1119 return -EINVAL; 1120 } 1121 1122 platform_set_drvdata(pdev, flctl); 1123 flctl_mtd = &flctl->mtd; 1124 nand = &flctl->chip; 1125 flctl_mtd->priv = nand; 1126 flctl->pdev = pdev; 1127 flctl->hwecc = pdata->has_hwecc; 1128 flctl->holden = pdata->use_holden; 1129 flctl->flcmncr_base = pdata->flcmncr_val; 1130 flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE; 1131 1132 /* Set address of hardware control function */ 1133 /* 20 us command delay time */ 1134 nand->chip_delay = 20; 1135 1136 nand->read_byte = flctl_read_byte; 1137 nand->write_buf = flctl_write_buf; 1138 nand->read_buf = flctl_read_buf; 1139 nand->select_chip = flctl_select_chip; 1140 nand->cmdfunc = flctl_cmdfunc; 1141 1142 if (pdata->flcmncr_val & SEL_16BIT) { 1143 nand->options |= NAND_BUSWIDTH_16; 1144 nand->read_word = flctl_read_word; 1145 } 1146 1147 pm_runtime_enable(&pdev->dev); 1148 pm_runtime_resume(&pdev->dev); 1149 1150 flctl_setup_dma(flctl); 1151 1152 ret = nand_scan_ident(flctl_mtd, 1, NULL); 1153 if (ret) 1154 goto err_chip; 1155 1156 ret = flctl_chip_init_tail(flctl_mtd); 1157 if (ret) 1158 goto err_chip; 1159 1160 ret = nand_scan_tail(flctl_mtd); 1161 if (ret) 1162 goto err_chip; 1163 1164 ppdata.of_node = pdev->dev.of_node; 1165 ret = mtd_device_parse_register(flctl_mtd, NULL, &ppdata, pdata->parts, 1166 pdata->nr_parts); 1167 1168 return 0; 1169 1170err_chip: 1171 flctl_release_dma(flctl); 1172 pm_runtime_disable(&pdev->dev); 1173 return ret; 1174} 1175 1176static int flctl_remove(struct platform_device *pdev) 1177{ 1178 struct sh_flctl *flctl = platform_get_drvdata(pdev); 1179 1180 flctl_release_dma(flctl); 1181 nand_release(&flctl->mtd); 1182 pm_runtime_disable(&pdev->dev); 1183 1184 return 0; 1185} 1186 1187static struct platform_driver flctl_driver = { 1188 .remove = flctl_remove, 1189 .driver = { 1190 .name = "sh_flctl", 1191 .of_match_table = of_match_ptr(of_flctl_match), 1192 }, 1193}; 1194 1195module_platform_driver_probe(flctl_driver, flctl_probe); 1196 1197MODULE_LICENSE("GPL"); 1198MODULE_AUTHOR("Yoshihiro Shimoda"); 1199MODULE_DESCRIPTION("SuperH FLCTL driver"); 1200MODULE_ALIAS("platform:sh_flctl"); 1201