1/* Renesas R-Car CAN device driver 2 * 3 * Copyright (C) 2013 Cogent Embedded, Inc. <source@cogentembedded.com> 4 * Copyright (C) 2013 Renesas Solutions Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12#include <linux/module.h> 13#include <linux/kernel.h> 14#include <linux/types.h> 15#include <linux/interrupt.h> 16#include <linux/errno.h> 17#include <linux/netdevice.h> 18#include <linux/platform_device.h> 19#include <linux/can/led.h> 20#include <linux/can/dev.h> 21#include <linux/clk.h> 22#include <linux/can/platform/rcar_can.h> 23#include <linux/of.h> 24 25#define RCAR_CAN_DRV_NAME "rcar_can" 26 27/* Mailbox configuration: 28 * mailbox 60 - 63 - Rx FIFO mailboxes 29 * mailbox 56 - 59 - Tx FIFO mailboxes 30 * non-FIFO mailboxes are not used 31 */ 32#define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */ 33#define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */ 34#define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */ 35#define RCAR_CAN_FIFO_DEPTH 4 36 37/* Mailbox registers structure */ 38struct rcar_can_mbox_regs { 39 u32 id; /* IDE and RTR bits, SID and EID */ 40 u8 stub; /* Not used */ 41 u8 dlc; /* Data Length Code - bits [0..3] */ 42 u8 data[8]; /* Data Bytes */ 43 u8 tsh; /* Time Stamp Higher Byte */ 44 u8 tsl; /* Time Stamp Lower Byte */ 45}; 46 47struct rcar_can_regs { 48 struct rcar_can_mbox_regs mb[RCAR_CAN_N_MBX]; /* Mailbox registers */ 49 u32 mkr_2_9[8]; /* Mask Registers 2-9 */ 50 u32 fidcr[2]; /* FIFO Received ID Compare Register */ 51 u32 mkivlr1; /* Mask Invalid Register 1 */ 52 u32 mier1; /* Mailbox Interrupt Enable Register 1 */ 53 u32 mkr_0_1[2]; /* Mask Registers 0-1 */ 54 u32 mkivlr0; /* Mask Invalid Register 0*/ 55 u32 mier0; /* Mailbox Interrupt Enable Register 0 */ 56 u8 pad_440[0x3c0]; 57 u8 mctl[64]; /* Message Control Registers */ 58 u16 ctlr; /* Control Register */ 59 u16 str; /* Status register */ 60 u8 bcr[3]; /* Bit Configuration Register */ 61 u8 clkr; /* Clock Select Register */ 62 u8 rfcr; /* Receive FIFO Control Register */ 63 u8 rfpcr; /* Receive FIFO Pointer Control Register */ 64 u8 tfcr; /* Transmit FIFO Control Register */ 65 u8 tfpcr; /* Transmit FIFO Pointer Control Register */ 66 u8 eier; /* Error Interrupt Enable Register */ 67 u8 eifr; /* Error Interrupt Factor Judge Register */ 68 u8 recr; /* Receive Error Count Register */ 69 u8 tecr; /* Transmit Error Count Register */ 70 u8 ecsr; /* Error Code Store Register */ 71 u8 cssr; /* Channel Search Support Register */ 72 u8 mssr; /* Mailbox Search Status Register */ 73 u8 msmr; /* Mailbox Search Mode Register */ 74 u16 tsr; /* Time Stamp Register */ 75 u8 afsr; /* Acceptance Filter Support Register */ 76 u8 pad_857; 77 u8 tcr; /* Test Control Register */ 78 u8 pad_859[7]; 79 u8 ier; /* Interrupt Enable Register */ 80 u8 isr; /* Interrupt Status Register */ 81 u8 pad_862; 82 u8 mbsmr; /* Mailbox Search Mask Register */ 83}; 84 85struct rcar_can_priv { 86 struct can_priv can; /* Must be the first member! */ 87 struct net_device *ndev; 88 struct napi_struct napi; 89 struct rcar_can_regs __iomem *regs; 90 struct clk *clk; 91 struct clk *can_clk; 92 u8 tx_dlc[RCAR_CAN_FIFO_DEPTH]; 93 u32 tx_head; 94 u32 tx_tail; 95 u8 clock_select; 96 u8 ier; 97}; 98 99static const struct can_bittiming_const rcar_can_bittiming_const = { 100 .name = RCAR_CAN_DRV_NAME, 101 .tseg1_min = 4, 102 .tseg1_max = 16, 103 .tseg2_min = 2, 104 .tseg2_max = 8, 105 .sjw_max = 4, 106 .brp_min = 1, 107 .brp_max = 1024, 108 .brp_inc = 1, 109}; 110 111/* Control Register bits */ 112#define RCAR_CAN_CTLR_BOM (3 << 11) /* Bus-Off Recovery Mode Bits */ 113#define RCAR_CAN_CTLR_BOM_ENT (1 << 11) /* Entry to halt mode */ 114 /* at bus-off entry */ 115#define RCAR_CAN_CTLR_SLPM (1 << 10) 116#define RCAR_CAN_CTLR_CANM (3 << 8) /* Operating Mode Select Bit */ 117#define RCAR_CAN_CTLR_CANM_HALT (1 << 9) 118#define RCAR_CAN_CTLR_CANM_RESET (1 << 8) 119#define RCAR_CAN_CTLR_CANM_FORCE_RESET (3 << 8) 120#define RCAR_CAN_CTLR_MLM (1 << 3) /* Message Lost Mode Select */ 121#define RCAR_CAN_CTLR_IDFM (3 << 1) /* ID Format Mode Select Bits */ 122#define RCAR_CAN_CTLR_IDFM_MIXED (1 << 2) /* Mixed ID mode */ 123#define RCAR_CAN_CTLR_MBM (1 << 0) /* Mailbox Mode select */ 124 125/* Status Register bits */ 126#define RCAR_CAN_STR_RSTST (1 << 8) /* Reset Status Bit */ 127 128/* FIFO Received ID Compare Registers 0 and 1 bits */ 129#define RCAR_CAN_FIDCR_IDE (1 << 31) /* ID Extension Bit */ 130#define RCAR_CAN_FIDCR_RTR (1 << 30) /* Remote Transmission Request Bit */ 131 132/* Receive FIFO Control Register bits */ 133#define RCAR_CAN_RFCR_RFEST (1 << 7) /* Receive FIFO Empty Status Flag */ 134#define RCAR_CAN_RFCR_RFE (1 << 0) /* Receive FIFO Enable */ 135 136/* Transmit FIFO Control Register bits */ 137#define RCAR_CAN_TFCR_TFUST (7 << 1) /* Transmit FIFO Unsent Message */ 138 /* Number Status Bits */ 139#define RCAR_CAN_TFCR_TFUST_SHIFT 1 /* Offset of Transmit FIFO Unsent */ 140 /* Message Number Status Bits */ 141#define RCAR_CAN_TFCR_TFE (1 << 0) /* Transmit FIFO Enable */ 142 143#define RCAR_CAN_N_RX_MKREGS1 2 /* Number of mask registers */ 144 /* for Rx mailboxes 0-31 */ 145#define RCAR_CAN_N_RX_MKREGS2 8 146 147/* Bit Configuration Register settings */ 148#define RCAR_CAN_BCR_TSEG1(x) (((x) & 0x0f) << 20) 149#define RCAR_CAN_BCR_BPR(x) (((x) & 0x3ff) << 8) 150#define RCAR_CAN_BCR_SJW(x) (((x) & 0x3) << 4) 151#define RCAR_CAN_BCR_TSEG2(x) ((x) & 0x07) 152 153/* Mailbox and Mask Registers bits */ 154#define RCAR_CAN_IDE (1 << 31) 155#define RCAR_CAN_RTR (1 << 30) 156#define RCAR_CAN_SID_SHIFT 18 157 158/* Mailbox Interrupt Enable Register 1 bits */ 159#define RCAR_CAN_MIER1_RXFIE (1 << 28) /* Receive FIFO Interrupt Enable */ 160#define RCAR_CAN_MIER1_TXFIE (1 << 24) /* Transmit FIFO Interrupt Enable */ 161 162/* Interrupt Enable Register bits */ 163#define RCAR_CAN_IER_ERSIE (1 << 5) /* Error (ERS) Interrupt Enable Bit */ 164#define RCAR_CAN_IER_RXFIE (1 << 4) /* Reception FIFO Interrupt */ 165 /* Enable Bit */ 166#define RCAR_CAN_IER_TXFIE (1 << 3) /* Transmission FIFO Interrupt */ 167 /* Enable Bit */ 168/* Interrupt Status Register bits */ 169#define RCAR_CAN_ISR_ERSF (1 << 5) /* Error (ERS) Interrupt Status Bit */ 170#define RCAR_CAN_ISR_RXFF (1 << 4) /* Reception FIFO Interrupt */ 171 /* Status Bit */ 172#define RCAR_CAN_ISR_TXFF (1 << 3) /* Transmission FIFO Interrupt */ 173 /* Status Bit */ 174 175/* Error Interrupt Enable Register bits */ 176#define RCAR_CAN_EIER_BLIE (1 << 7) /* Bus Lock Interrupt Enable */ 177#define RCAR_CAN_EIER_OLIE (1 << 6) /* Overload Frame Transmit */ 178 /* Interrupt Enable */ 179#define RCAR_CAN_EIER_ORIE (1 << 5) /* Receive Overrun Interrupt Enable */ 180#define RCAR_CAN_EIER_BORIE (1 << 4) /* Bus-Off Recovery Interrupt Enable */ 181#define RCAR_CAN_EIER_BOEIE (1 << 3) /* Bus-Off Entry Interrupt Enable */ 182#define RCAR_CAN_EIER_EPIE (1 << 2) /* Error Passive Interrupt Enable */ 183#define RCAR_CAN_EIER_EWIE (1 << 1) /* Error Warning Interrupt Enable */ 184#define RCAR_CAN_EIER_BEIE (1 << 0) /* Bus Error Interrupt Enable */ 185 186/* Error Interrupt Factor Judge Register bits */ 187#define RCAR_CAN_EIFR_BLIF (1 << 7) /* Bus Lock Detect Flag */ 188#define RCAR_CAN_EIFR_OLIF (1 << 6) /* Overload Frame Transmission */ 189 /* Detect Flag */ 190#define RCAR_CAN_EIFR_ORIF (1 << 5) /* Receive Overrun Detect Flag */ 191#define RCAR_CAN_EIFR_BORIF (1 << 4) /* Bus-Off Recovery Detect Flag */ 192#define RCAR_CAN_EIFR_BOEIF (1 << 3) /* Bus-Off Entry Detect Flag */ 193#define RCAR_CAN_EIFR_EPIF (1 << 2) /* Error Passive Detect Flag */ 194#define RCAR_CAN_EIFR_EWIF (1 << 1) /* Error Warning Detect Flag */ 195#define RCAR_CAN_EIFR_BEIF (1 << 0) /* Bus Error Detect Flag */ 196 197/* Error Code Store Register bits */ 198#define RCAR_CAN_ECSR_EDPM (1 << 7) /* Error Display Mode Select Bit */ 199#define RCAR_CAN_ECSR_ADEF (1 << 6) /* ACK Delimiter Error Flag */ 200#define RCAR_CAN_ECSR_BE0F (1 << 5) /* Bit Error (dominant) Flag */ 201#define RCAR_CAN_ECSR_BE1F (1 << 4) /* Bit Error (recessive) Flag */ 202#define RCAR_CAN_ECSR_CEF (1 << 3) /* CRC Error Flag */ 203#define RCAR_CAN_ECSR_AEF (1 << 2) /* ACK Error Flag */ 204#define RCAR_CAN_ECSR_FEF (1 << 1) /* Form Error Flag */ 205#define RCAR_CAN_ECSR_SEF (1 << 0) /* Stuff Error Flag */ 206 207#define RCAR_CAN_NAPI_WEIGHT 4 208#define MAX_STR_READS 0x100 209 210static void tx_failure_cleanup(struct net_device *ndev) 211{ 212 int i; 213 214 for (i = 0; i < RCAR_CAN_FIFO_DEPTH; i++) 215 can_free_echo_skb(ndev, i); 216} 217 218static void rcar_can_error(struct net_device *ndev) 219{ 220 struct rcar_can_priv *priv = netdev_priv(ndev); 221 struct net_device_stats *stats = &ndev->stats; 222 struct can_frame *cf; 223 struct sk_buff *skb; 224 u8 eifr, txerr = 0, rxerr = 0; 225 226 /* Propagate the error condition to the CAN stack */ 227 skb = alloc_can_err_skb(ndev, &cf); 228 229 eifr = readb(&priv->regs->eifr); 230 if (eifr & (RCAR_CAN_EIFR_EWIF | RCAR_CAN_EIFR_EPIF)) { 231 txerr = readb(&priv->regs->tecr); 232 rxerr = readb(&priv->regs->recr); 233 if (skb) { 234 cf->can_id |= CAN_ERR_CRTL; 235 cf->data[6] = txerr; 236 cf->data[7] = rxerr; 237 } 238 } 239 if (eifr & RCAR_CAN_EIFR_BEIF) { 240 int rx_errors = 0, tx_errors = 0; 241 u8 ecsr; 242 243 netdev_dbg(priv->ndev, "Bus error interrupt:\n"); 244 if (skb) { 245 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT; 246 cf->data[2] = CAN_ERR_PROT_UNSPEC; 247 } 248 ecsr = readb(&priv->regs->ecsr); 249 if (ecsr & RCAR_CAN_ECSR_ADEF) { 250 netdev_dbg(priv->ndev, "ACK Delimiter Error\n"); 251 tx_errors++; 252 writeb(~RCAR_CAN_ECSR_ADEF, &priv->regs->ecsr); 253 if (skb) 254 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL; 255 } 256 if (ecsr & RCAR_CAN_ECSR_BE0F) { 257 netdev_dbg(priv->ndev, "Bit Error (dominant)\n"); 258 tx_errors++; 259 writeb(~RCAR_CAN_ECSR_BE0F, &priv->regs->ecsr); 260 if (skb) 261 cf->data[2] |= CAN_ERR_PROT_BIT0; 262 } 263 if (ecsr & RCAR_CAN_ECSR_BE1F) { 264 netdev_dbg(priv->ndev, "Bit Error (recessive)\n"); 265 tx_errors++; 266 writeb(~RCAR_CAN_ECSR_BE1F, &priv->regs->ecsr); 267 if (skb) 268 cf->data[2] |= CAN_ERR_PROT_BIT1; 269 } 270 if (ecsr & RCAR_CAN_ECSR_CEF) { 271 netdev_dbg(priv->ndev, "CRC Error\n"); 272 rx_errors++; 273 writeb(~RCAR_CAN_ECSR_CEF, &priv->regs->ecsr); 274 if (skb) 275 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 276 } 277 if (ecsr & RCAR_CAN_ECSR_AEF) { 278 netdev_dbg(priv->ndev, "ACK Error\n"); 279 tx_errors++; 280 writeb(~RCAR_CAN_ECSR_AEF, &priv->regs->ecsr); 281 if (skb) { 282 cf->can_id |= CAN_ERR_ACK; 283 cf->data[3] |= CAN_ERR_PROT_LOC_ACK; 284 } 285 } 286 if (ecsr & RCAR_CAN_ECSR_FEF) { 287 netdev_dbg(priv->ndev, "Form Error\n"); 288 rx_errors++; 289 writeb(~RCAR_CAN_ECSR_FEF, &priv->regs->ecsr); 290 if (skb) 291 cf->data[2] |= CAN_ERR_PROT_FORM; 292 } 293 if (ecsr & RCAR_CAN_ECSR_SEF) { 294 netdev_dbg(priv->ndev, "Stuff Error\n"); 295 rx_errors++; 296 writeb(~RCAR_CAN_ECSR_SEF, &priv->regs->ecsr); 297 if (skb) 298 cf->data[2] |= CAN_ERR_PROT_STUFF; 299 } 300 301 priv->can.can_stats.bus_error++; 302 ndev->stats.rx_errors += rx_errors; 303 ndev->stats.tx_errors += tx_errors; 304 writeb(~RCAR_CAN_EIFR_BEIF, &priv->regs->eifr); 305 } 306 if (eifr & RCAR_CAN_EIFR_EWIF) { 307 netdev_dbg(priv->ndev, "Error warning interrupt\n"); 308 priv->can.state = CAN_STATE_ERROR_WARNING; 309 priv->can.can_stats.error_warning++; 310 /* Clear interrupt condition */ 311 writeb(~RCAR_CAN_EIFR_EWIF, &priv->regs->eifr); 312 if (skb) 313 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING : 314 CAN_ERR_CRTL_RX_WARNING; 315 } 316 if (eifr & RCAR_CAN_EIFR_EPIF) { 317 netdev_dbg(priv->ndev, "Error passive interrupt\n"); 318 priv->can.state = CAN_STATE_ERROR_PASSIVE; 319 priv->can.can_stats.error_passive++; 320 /* Clear interrupt condition */ 321 writeb(~RCAR_CAN_EIFR_EPIF, &priv->regs->eifr); 322 if (skb) 323 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE : 324 CAN_ERR_CRTL_RX_PASSIVE; 325 } 326 if (eifr & RCAR_CAN_EIFR_BOEIF) { 327 netdev_dbg(priv->ndev, "Bus-off entry interrupt\n"); 328 tx_failure_cleanup(ndev); 329 priv->ier = RCAR_CAN_IER_ERSIE; 330 writeb(priv->ier, &priv->regs->ier); 331 priv->can.state = CAN_STATE_BUS_OFF; 332 /* Clear interrupt condition */ 333 writeb(~RCAR_CAN_EIFR_BOEIF, &priv->regs->eifr); 334 priv->can.can_stats.bus_off++; 335 can_bus_off(ndev); 336 if (skb) 337 cf->can_id |= CAN_ERR_BUSOFF; 338 } 339 if (eifr & RCAR_CAN_EIFR_ORIF) { 340 netdev_dbg(priv->ndev, "Receive overrun error interrupt\n"); 341 ndev->stats.rx_over_errors++; 342 ndev->stats.rx_errors++; 343 writeb(~RCAR_CAN_EIFR_ORIF, &priv->regs->eifr); 344 if (skb) { 345 cf->can_id |= CAN_ERR_CRTL; 346 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 347 } 348 } 349 if (eifr & RCAR_CAN_EIFR_OLIF) { 350 netdev_dbg(priv->ndev, 351 "Overload Frame Transmission error interrupt\n"); 352 ndev->stats.rx_over_errors++; 353 ndev->stats.rx_errors++; 354 writeb(~RCAR_CAN_EIFR_OLIF, &priv->regs->eifr); 355 if (skb) { 356 cf->can_id |= CAN_ERR_PROT; 357 cf->data[2] |= CAN_ERR_PROT_OVERLOAD; 358 } 359 } 360 361 if (skb) { 362 stats->rx_packets++; 363 stats->rx_bytes += cf->can_dlc; 364 netif_rx(skb); 365 } 366} 367 368static void rcar_can_tx_done(struct net_device *ndev) 369{ 370 struct rcar_can_priv *priv = netdev_priv(ndev); 371 struct net_device_stats *stats = &ndev->stats; 372 u8 isr; 373 374 while (1) { 375 u8 unsent = readb(&priv->regs->tfcr); 376 377 unsent = (unsent & RCAR_CAN_TFCR_TFUST) >> 378 RCAR_CAN_TFCR_TFUST_SHIFT; 379 if (priv->tx_head - priv->tx_tail <= unsent) 380 break; 381 stats->tx_packets++; 382 stats->tx_bytes += priv->tx_dlc[priv->tx_tail % 383 RCAR_CAN_FIFO_DEPTH]; 384 priv->tx_dlc[priv->tx_tail % RCAR_CAN_FIFO_DEPTH] = 0; 385 can_get_echo_skb(ndev, priv->tx_tail % RCAR_CAN_FIFO_DEPTH); 386 priv->tx_tail++; 387 netif_wake_queue(ndev); 388 } 389 /* Clear interrupt */ 390 isr = readb(&priv->regs->isr); 391 writeb(isr & ~RCAR_CAN_ISR_TXFF, &priv->regs->isr); 392 can_led_event(ndev, CAN_LED_EVENT_TX); 393} 394 395static irqreturn_t rcar_can_interrupt(int irq, void *dev_id) 396{ 397 struct net_device *ndev = dev_id; 398 struct rcar_can_priv *priv = netdev_priv(ndev); 399 u8 isr; 400 401 isr = readb(&priv->regs->isr); 402 if (!(isr & priv->ier)) 403 return IRQ_NONE; 404 405 if (isr & RCAR_CAN_ISR_ERSF) 406 rcar_can_error(ndev); 407 408 if (isr & RCAR_CAN_ISR_TXFF) 409 rcar_can_tx_done(ndev); 410 411 if (isr & RCAR_CAN_ISR_RXFF) { 412 if (napi_schedule_prep(&priv->napi)) { 413 /* Disable Rx FIFO interrupts */ 414 priv->ier &= ~RCAR_CAN_IER_RXFIE; 415 writeb(priv->ier, &priv->regs->ier); 416 __napi_schedule(&priv->napi); 417 } 418 } 419 420 return IRQ_HANDLED; 421} 422 423static void rcar_can_set_bittiming(struct net_device *dev) 424{ 425 struct rcar_can_priv *priv = netdev_priv(dev); 426 struct can_bittiming *bt = &priv->can.bittiming; 427 u32 bcr; 428 429 bcr = RCAR_CAN_BCR_TSEG1(bt->phase_seg1 + bt->prop_seg - 1) | 430 RCAR_CAN_BCR_BPR(bt->brp - 1) | RCAR_CAN_BCR_SJW(bt->sjw - 1) | 431 RCAR_CAN_BCR_TSEG2(bt->phase_seg2 - 1); 432 /* Don't overwrite CLKR with 32-bit BCR access; CLKR has 8-bit access. 433 * All the registers are big-endian but they get byte-swapped on 32-bit 434 * read/write (but not on 8-bit, contrary to the manuals)... 435 */ 436 writel((bcr << 8) | priv->clock_select, &priv->regs->bcr); 437} 438 439static void rcar_can_start(struct net_device *ndev) 440{ 441 struct rcar_can_priv *priv = netdev_priv(ndev); 442 u16 ctlr; 443 int i; 444 445 /* Set controller to known mode: 446 * - FIFO mailbox mode 447 * - accept all messages 448 * - overrun mode 449 * CAN is in sleep mode after MCU hardware or software reset. 450 */ 451 ctlr = readw(&priv->regs->ctlr); 452 ctlr &= ~RCAR_CAN_CTLR_SLPM; 453 writew(ctlr, &priv->regs->ctlr); 454 /* Go to reset mode */ 455 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 456 writew(ctlr, &priv->regs->ctlr); 457 for (i = 0; i < MAX_STR_READS; i++) { 458 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 459 break; 460 } 461 rcar_can_set_bittiming(ndev); 462 ctlr |= RCAR_CAN_CTLR_IDFM_MIXED; /* Select mixed ID mode */ 463 ctlr |= RCAR_CAN_CTLR_BOM_ENT; /* Entry to halt mode automatically */ 464 /* at bus-off */ 465 ctlr |= RCAR_CAN_CTLR_MBM; /* Select FIFO mailbox mode */ 466 ctlr |= RCAR_CAN_CTLR_MLM; /* Overrun mode */ 467 writew(ctlr, &priv->regs->ctlr); 468 469 /* Accept all SID and EID */ 470 writel(0, &priv->regs->mkr_2_9[6]); 471 writel(0, &priv->regs->mkr_2_9[7]); 472 /* In FIFO mailbox mode, write "0" to bits 24 to 31 */ 473 writel(0, &priv->regs->mkivlr1); 474 /* Accept all frames */ 475 writel(0, &priv->regs->fidcr[0]); 476 writel(RCAR_CAN_FIDCR_IDE | RCAR_CAN_FIDCR_RTR, &priv->regs->fidcr[1]); 477 /* Enable and configure FIFO mailbox interrupts */ 478 writel(RCAR_CAN_MIER1_RXFIE | RCAR_CAN_MIER1_TXFIE, &priv->regs->mier1); 479 480 priv->ier = RCAR_CAN_IER_ERSIE | RCAR_CAN_IER_RXFIE | 481 RCAR_CAN_IER_TXFIE; 482 writeb(priv->ier, &priv->regs->ier); 483 484 /* Accumulate error codes */ 485 writeb(RCAR_CAN_ECSR_EDPM, &priv->regs->ecsr); 486 /* Enable error interrupts */ 487 writeb(RCAR_CAN_EIER_EWIE | RCAR_CAN_EIER_EPIE | RCAR_CAN_EIER_BOEIE | 488 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING ? 489 RCAR_CAN_EIER_BEIE : 0) | RCAR_CAN_EIER_ORIE | 490 RCAR_CAN_EIER_OLIE, &priv->regs->eier); 491 priv->can.state = CAN_STATE_ERROR_ACTIVE; 492 493 /* Go to operation mode */ 494 writew(ctlr & ~RCAR_CAN_CTLR_CANM, &priv->regs->ctlr); 495 for (i = 0; i < MAX_STR_READS; i++) { 496 if (!(readw(&priv->regs->str) & RCAR_CAN_STR_RSTST)) 497 break; 498 } 499 /* Enable Rx and Tx FIFO */ 500 writeb(RCAR_CAN_RFCR_RFE, &priv->regs->rfcr); 501 writeb(RCAR_CAN_TFCR_TFE, &priv->regs->tfcr); 502} 503 504static int rcar_can_open(struct net_device *ndev) 505{ 506 struct rcar_can_priv *priv = netdev_priv(ndev); 507 int err; 508 509 err = clk_prepare_enable(priv->clk); 510 if (err) { 511 netdev_err(ndev, "failed to enable periperal clock, error %d\n", 512 err); 513 goto out; 514 } 515 err = clk_prepare_enable(priv->can_clk); 516 if (err) { 517 netdev_err(ndev, "failed to enable CAN clock, error %d\n", 518 err); 519 goto out_clock; 520 } 521 err = open_candev(ndev); 522 if (err) { 523 netdev_err(ndev, "open_candev() failed, error %d\n", err); 524 goto out_can_clock; 525 } 526 napi_enable(&priv->napi); 527 err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev); 528 if (err) { 529 netdev_err(ndev, "error requesting interrupt %d\n", ndev->irq); 530 goto out_close; 531 } 532 can_led_event(ndev, CAN_LED_EVENT_OPEN); 533 rcar_can_start(ndev); 534 netif_start_queue(ndev); 535 return 0; 536out_close: 537 napi_disable(&priv->napi); 538 close_candev(ndev); 539out_can_clock: 540 clk_disable_unprepare(priv->can_clk); 541out_clock: 542 clk_disable_unprepare(priv->clk); 543out: 544 return err; 545} 546 547static void rcar_can_stop(struct net_device *ndev) 548{ 549 struct rcar_can_priv *priv = netdev_priv(ndev); 550 u16 ctlr; 551 int i; 552 553 /* Go to (force) reset mode */ 554 ctlr = readw(&priv->regs->ctlr); 555 ctlr |= RCAR_CAN_CTLR_CANM_FORCE_RESET; 556 writew(ctlr, &priv->regs->ctlr); 557 for (i = 0; i < MAX_STR_READS; i++) { 558 if (readw(&priv->regs->str) & RCAR_CAN_STR_RSTST) 559 break; 560 } 561 writel(0, &priv->regs->mier0); 562 writel(0, &priv->regs->mier1); 563 writeb(0, &priv->regs->ier); 564 writeb(0, &priv->regs->eier); 565 /* Go to sleep mode */ 566 ctlr |= RCAR_CAN_CTLR_SLPM; 567 writew(ctlr, &priv->regs->ctlr); 568 priv->can.state = CAN_STATE_STOPPED; 569} 570 571static int rcar_can_close(struct net_device *ndev) 572{ 573 struct rcar_can_priv *priv = netdev_priv(ndev); 574 575 netif_stop_queue(ndev); 576 rcar_can_stop(ndev); 577 free_irq(ndev->irq, ndev); 578 napi_disable(&priv->napi); 579 clk_disable_unprepare(priv->can_clk); 580 clk_disable_unprepare(priv->clk); 581 close_candev(ndev); 582 can_led_event(ndev, CAN_LED_EVENT_STOP); 583 return 0; 584} 585 586static netdev_tx_t rcar_can_start_xmit(struct sk_buff *skb, 587 struct net_device *ndev) 588{ 589 struct rcar_can_priv *priv = netdev_priv(ndev); 590 struct can_frame *cf = (struct can_frame *)skb->data; 591 u32 data, i; 592 593 if (can_dropped_invalid_skb(ndev, skb)) 594 return NETDEV_TX_OK; 595 596 if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ 597 data = (cf->can_id & CAN_EFF_MASK) | RCAR_CAN_IDE; 598 else /* Standard frame format */ 599 data = (cf->can_id & CAN_SFF_MASK) << RCAR_CAN_SID_SHIFT; 600 601 if (cf->can_id & CAN_RTR_FLAG) { /* Remote transmission request */ 602 data |= RCAR_CAN_RTR; 603 } else { 604 for (i = 0; i < cf->can_dlc; i++) 605 writeb(cf->data[i], 606 &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].data[i]); 607 } 608 609 writel(data, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].id); 610 611 writeb(cf->can_dlc, &priv->regs->mb[RCAR_CAN_TX_FIFO_MBX].dlc); 612 613 priv->tx_dlc[priv->tx_head % RCAR_CAN_FIFO_DEPTH] = cf->can_dlc; 614 can_put_echo_skb(skb, ndev, priv->tx_head % RCAR_CAN_FIFO_DEPTH); 615 priv->tx_head++; 616 /* Start Tx: write 0xff to the TFPCR register to increment 617 * the CPU-side pointer for the transmit FIFO to the next 618 * mailbox location 619 */ 620 writeb(0xff, &priv->regs->tfpcr); 621 /* Stop the queue if we've filled all FIFO entries */ 622 if (priv->tx_head - priv->tx_tail >= RCAR_CAN_FIFO_DEPTH) 623 netif_stop_queue(ndev); 624 625 return NETDEV_TX_OK; 626} 627 628static const struct net_device_ops rcar_can_netdev_ops = { 629 .ndo_open = rcar_can_open, 630 .ndo_stop = rcar_can_close, 631 .ndo_start_xmit = rcar_can_start_xmit, 632 .ndo_change_mtu = can_change_mtu, 633}; 634 635static void rcar_can_rx_pkt(struct rcar_can_priv *priv) 636{ 637 struct net_device_stats *stats = &priv->ndev->stats; 638 struct can_frame *cf; 639 struct sk_buff *skb; 640 u32 data; 641 u8 dlc; 642 643 skb = alloc_can_skb(priv->ndev, &cf); 644 if (!skb) { 645 stats->rx_dropped++; 646 return; 647 } 648 649 data = readl(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].id); 650 if (data & RCAR_CAN_IDE) 651 cf->can_id = (data & CAN_EFF_MASK) | CAN_EFF_FLAG; 652 else 653 cf->can_id = (data >> RCAR_CAN_SID_SHIFT) & CAN_SFF_MASK; 654 655 dlc = readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].dlc); 656 cf->can_dlc = get_can_dlc(dlc); 657 if (data & RCAR_CAN_RTR) { 658 cf->can_id |= CAN_RTR_FLAG; 659 } else { 660 for (dlc = 0; dlc < cf->can_dlc; dlc++) 661 cf->data[dlc] = 662 readb(&priv->regs->mb[RCAR_CAN_RX_FIFO_MBX].data[dlc]); 663 } 664 665 can_led_event(priv->ndev, CAN_LED_EVENT_RX); 666 667 stats->rx_bytes += cf->can_dlc; 668 stats->rx_packets++; 669 netif_receive_skb(skb); 670} 671 672static int rcar_can_rx_poll(struct napi_struct *napi, int quota) 673{ 674 struct rcar_can_priv *priv = container_of(napi, 675 struct rcar_can_priv, napi); 676 int num_pkts; 677 678 for (num_pkts = 0; num_pkts < quota; num_pkts++) { 679 u8 rfcr, isr; 680 681 isr = readb(&priv->regs->isr); 682 /* Clear interrupt bit */ 683 if (isr & RCAR_CAN_ISR_RXFF) 684 writeb(isr & ~RCAR_CAN_ISR_RXFF, &priv->regs->isr); 685 rfcr = readb(&priv->regs->rfcr); 686 if (rfcr & RCAR_CAN_RFCR_RFEST) 687 break; 688 rcar_can_rx_pkt(priv); 689 /* Write 0xff to the RFPCR register to increment 690 * the CPU-side pointer for the receive FIFO 691 * to the next mailbox location 692 */ 693 writeb(0xff, &priv->regs->rfpcr); 694 } 695 /* All packets processed */ 696 if (num_pkts < quota) { 697 napi_complete(napi); 698 priv->ier |= RCAR_CAN_IER_RXFIE; 699 writeb(priv->ier, &priv->regs->ier); 700 } 701 return num_pkts; 702} 703 704static int rcar_can_do_set_mode(struct net_device *ndev, enum can_mode mode) 705{ 706 switch (mode) { 707 case CAN_MODE_START: 708 rcar_can_start(ndev); 709 netif_wake_queue(ndev); 710 return 0; 711 default: 712 return -EOPNOTSUPP; 713 } 714} 715 716static int rcar_can_get_berr_counter(const struct net_device *dev, 717 struct can_berr_counter *bec) 718{ 719 struct rcar_can_priv *priv = netdev_priv(dev); 720 int err; 721 722 err = clk_prepare_enable(priv->clk); 723 if (err) 724 return err; 725 bec->txerr = readb(&priv->regs->tecr); 726 bec->rxerr = readb(&priv->regs->recr); 727 clk_disable_unprepare(priv->clk); 728 return 0; 729} 730 731static const char * const clock_names[] = { 732 [CLKR_CLKP1] = "clkp1", 733 [CLKR_CLKP2] = "clkp2", 734 [CLKR_CLKEXT] = "can_clk", 735}; 736 737static int rcar_can_probe(struct platform_device *pdev) 738{ 739 struct rcar_can_platform_data *pdata; 740 struct rcar_can_priv *priv; 741 struct net_device *ndev; 742 struct resource *mem; 743 void __iomem *addr; 744 u32 clock_select = CLKR_CLKP1; 745 int err = -ENODEV; 746 int irq; 747 748 if (pdev->dev.of_node) { 749 of_property_read_u32(pdev->dev.of_node, 750 "renesas,can-clock-select", &clock_select); 751 } else { 752 pdata = dev_get_platdata(&pdev->dev); 753 if (!pdata) { 754 dev_err(&pdev->dev, "No platform data provided!\n"); 755 goto fail; 756 } 757 clock_select = pdata->clock_select; 758 } 759 760 irq = platform_get_irq(pdev, 0); 761 if (irq < 0) { 762 dev_err(&pdev->dev, "No IRQ resource\n"); 763 err = irq; 764 goto fail; 765 } 766 767 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 768 addr = devm_ioremap_resource(&pdev->dev, mem); 769 if (IS_ERR(addr)) { 770 err = PTR_ERR(addr); 771 goto fail; 772 } 773 774 ndev = alloc_candev(sizeof(struct rcar_can_priv), RCAR_CAN_FIFO_DEPTH); 775 if (!ndev) { 776 dev_err(&pdev->dev, "alloc_candev() failed\n"); 777 err = -ENOMEM; 778 goto fail; 779 } 780 781 priv = netdev_priv(ndev); 782 783 priv->clk = devm_clk_get(&pdev->dev, "clkp1"); 784 if (IS_ERR(priv->clk)) { 785 err = PTR_ERR(priv->clk); 786 dev_err(&pdev->dev, "cannot get peripheral clock: %d\n", err); 787 goto fail_clk; 788 } 789 790 if (clock_select >= ARRAY_SIZE(clock_names)) { 791 err = -EINVAL; 792 dev_err(&pdev->dev, "invalid CAN clock selected\n"); 793 goto fail_clk; 794 } 795 priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]); 796 if (IS_ERR(priv->can_clk)) { 797 err = PTR_ERR(priv->can_clk); 798 dev_err(&pdev->dev, "cannot get CAN clock: %d\n", err); 799 goto fail_clk; 800 } 801 802 ndev->netdev_ops = &rcar_can_netdev_ops; 803 ndev->irq = irq; 804 ndev->flags |= IFF_ECHO; 805 priv->ndev = ndev; 806 priv->regs = addr; 807 priv->clock_select = clock_select; 808 priv->can.clock.freq = clk_get_rate(priv->can_clk); 809 priv->can.bittiming_const = &rcar_can_bittiming_const; 810 priv->can.do_set_mode = rcar_can_do_set_mode; 811 priv->can.do_get_berr_counter = rcar_can_get_berr_counter; 812 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING; 813 platform_set_drvdata(pdev, ndev); 814 SET_NETDEV_DEV(ndev, &pdev->dev); 815 816 netif_napi_add(ndev, &priv->napi, rcar_can_rx_poll, 817 RCAR_CAN_NAPI_WEIGHT); 818 err = register_candev(ndev); 819 if (err) { 820 dev_err(&pdev->dev, "register_candev() failed, error %d\n", 821 err); 822 goto fail_candev; 823 } 824 825 devm_can_led_init(ndev); 826 827 dev_info(&pdev->dev, "device registered (regs @ %p, IRQ%d)\n", 828 priv->regs, ndev->irq); 829 830 return 0; 831fail_candev: 832 netif_napi_del(&priv->napi); 833fail_clk: 834 free_candev(ndev); 835fail: 836 return err; 837} 838 839static int rcar_can_remove(struct platform_device *pdev) 840{ 841 struct net_device *ndev = platform_get_drvdata(pdev); 842 struct rcar_can_priv *priv = netdev_priv(ndev); 843 844 unregister_candev(ndev); 845 netif_napi_del(&priv->napi); 846 free_candev(ndev); 847 return 0; 848} 849 850static int __maybe_unused rcar_can_suspend(struct device *dev) 851{ 852 struct net_device *ndev = dev_get_drvdata(dev); 853 struct rcar_can_priv *priv = netdev_priv(ndev); 854 u16 ctlr; 855 856 if (netif_running(ndev)) { 857 netif_stop_queue(ndev); 858 netif_device_detach(ndev); 859 } 860 ctlr = readw(&priv->regs->ctlr); 861 ctlr |= RCAR_CAN_CTLR_CANM_HALT; 862 writew(ctlr, &priv->regs->ctlr); 863 ctlr |= RCAR_CAN_CTLR_SLPM; 864 writew(ctlr, &priv->regs->ctlr); 865 priv->can.state = CAN_STATE_SLEEPING; 866 867 clk_disable(priv->clk); 868 return 0; 869} 870 871static int __maybe_unused rcar_can_resume(struct device *dev) 872{ 873 struct net_device *ndev = dev_get_drvdata(dev); 874 struct rcar_can_priv *priv = netdev_priv(ndev); 875 u16 ctlr; 876 int err; 877 878 err = clk_enable(priv->clk); 879 if (err) { 880 netdev_err(ndev, "clk_enable() failed, error %d\n", err); 881 return err; 882 } 883 884 ctlr = readw(&priv->regs->ctlr); 885 ctlr &= ~RCAR_CAN_CTLR_SLPM; 886 writew(ctlr, &priv->regs->ctlr); 887 ctlr &= ~RCAR_CAN_CTLR_CANM; 888 writew(ctlr, &priv->regs->ctlr); 889 priv->can.state = CAN_STATE_ERROR_ACTIVE; 890 891 if (netif_running(ndev)) { 892 netif_device_attach(ndev); 893 netif_start_queue(ndev); 894 } 895 return 0; 896} 897 898static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume); 899 900static const struct of_device_id rcar_can_of_table[] __maybe_unused = { 901 { .compatible = "renesas,can-r8a7778" }, 902 { .compatible = "renesas,can-r8a7779" }, 903 { .compatible = "renesas,can-r8a7790" }, 904 { .compatible = "renesas,can-r8a7791" }, 905 { } 906}; 907MODULE_DEVICE_TABLE(of, rcar_can_of_table); 908 909static struct platform_driver rcar_can_driver = { 910 .driver = { 911 .name = RCAR_CAN_DRV_NAME, 912 .of_match_table = of_match_ptr(rcar_can_of_table), 913 .pm = &rcar_can_pm_ops, 914 }, 915 .probe = rcar_can_probe, 916 .remove = rcar_can_remove, 917}; 918 919module_platform_driver(rcar_can_driver); 920 921MODULE_AUTHOR("Cogent Embedded, Inc."); 922MODULE_LICENSE("GPL"); 923MODULE_DESCRIPTION("CAN driver for Renesas R-Car SoC"); 924MODULE_ALIAS("platform:" RCAR_CAN_DRV_NAME); 925