1/* 2 * AMD 10Gb Ethernet driver 3 * 4 * This file is available to you under your choice of the following two 5 * licenses: 6 * 7 * License 1: GPLv2 8 * 9 * Copyright (c) 2014 Advanced Micro Devices, Inc. 10 * 11 * This file is free software; you may copy, redistribute and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or (at 14 * your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 * 24 * This file incorporates work covered by the following copyright and 25 * permission notice: 26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 28 * Inc. unless otherwise expressly agreed to in writing between Synopsys 29 * and you. 30 * 31 * The Software IS NOT an item of Licensed Software or Licensed Product 32 * under any End User Software License Agreement or Agreement for Licensed 33 * Product with Synopsys or any supplement thereto. Permission is hereby 34 * granted, free of charge, to any person obtaining a copy of this software 35 * annotated with this license and the Software, to deal in the Software 36 * without restriction, including without limitation the rights to use, 37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 38 * of the Software, and to permit persons to whom the Software is furnished 39 * to do so, subject to the following conditions: 40 * 41 * The above copyright notice and this permission notice shall be included 42 * in all copies or substantial portions of the Software. 43 * 44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 54 * THE POSSIBILITY OF SUCH DAMAGE. 55 * 56 * 57 * License 2: Modified BSD 58 * 59 * Copyright (c) 2014 Advanced Micro Devices, Inc. 60 * All rights reserved. 61 * 62 * Redistribution and use in source and binary forms, with or without 63 * modification, are permitted provided that the following conditions are met: 64 * * Redistributions of source code must retain the above copyright 65 * notice, this list of conditions and the following disclaimer. 66 * * Redistributions in binary form must reproduce the above copyright 67 * notice, this list of conditions and the following disclaimer in the 68 * documentation and/or other materials provided with the distribution. 69 * * Neither the name of Advanced Micro Devices, Inc. nor the 70 * names of its contributors may be used to endorse or promote products 71 * derived from this software without specific prior written permission. 72 * 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY 77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 83 * 84 * This file incorporates work covered by the following copyright and 85 * permission notice: 86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation 87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys, 88 * Inc. unless otherwise expressly agreed to in writing between Synopsys 89 * and you. 90 * 91 * The Software IS NOT an item of Licensed Software or Licensed Product 92 * under any End User Software License Agreement or Agreement for Licensed 93 * Product with Synopsys or any supplement thereto. Permission is hereby 94 * granted, free of charge, to any person obtaining a copy of this software 95 * annotated with this license and the Software, to deal in the Software 96 * without restriction, including without limitation the rights to use, 97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies 98 * of the Software, and to permit persons to whom the Software is furnished 99 * to do so, subject to the following conditions: 100 * 101 * The above copyright notice and this permission notice shall be included 102 * in all copies or substantial portions of the Software. 103 * 104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" 105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS 108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 114 * THE POSSIBILITY OF SUCH DAMAGE. 115 */ 116 117#include <linux/platform_device.h> 118#include <linux/spinlock.h> 119#include <linux/tcp.h> 120#include <linux/if_vlan.h> 121#include <net/busy_poll.h> 122#include <linux/clk.h> 123#include <linux/if_ether.h> 124#include <linux/net_tstamp.h> 125#include <linux/phy.h> 126 127#include "xgbe.h" 128#include "xgbe-common.h" 129 130static int xgbe_one_poll(struct napi_struct *, int); 131static int xgbe_all_poll(struct napi_struct *, int); 132 133static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) 134{ 135 struct xgbe_channel *channel_mem, *channel; 136 struct xgbe_ring *tx_ring, *rx_ring; 137 unsigned int count, i; 138 int ret = -ENOMEM; 139 140 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 141 142 channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL); 143 if (!channel_mem) 144 goto err_channel; 145 146 tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring), 147 GFP_KERNEL); 148 if (!tx_ring) 149 goto err_tx_ring; 150 151 rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring), 152 GFP_KERNEL); 153 if (!rx_ring) 154 goto err_rx_ring; 155 156 for (i = 0, channel = channel_mem; i < count; i++, channel++) { 157 snprintf(channel->name, sizeof(channel->name), "channel-%d", i); 158 channel->pdata = pdata; 159 channel->queue_index = i; 160 channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + 161 (DMA_CH_INC * i); 162 163 if (pdata->per_channel_irq) { 164 /* Get the DMA interrupt (offset 1) */ 165 ret = platform_get_irq(pdata->pdev, i + 1); 166 if (ret < 0) { 167 netdev_err(pdata->netdev, 168 "platform_get_irq %u failed\n", 169 i + 1); 170 goto err_irq; 171 } 172 173 channel->dma_irq = ret; 174 } 175 176 if (i < pdata->tx_ring_count) { 177 spin_lock_init(&tx_ring->lock); 178 channel->tx_ring = tx_ring++; 179 } 180 181 if (i < pdata->rx_ring_count) { 182 spin_lock_init(&rx_ring->lock); 183 channel->rx_ring = rx_ring++; 184 } 185 186 DBGPR(" %s: queue=%u, dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", 187 channel->name, channel->queue_index, channel->dma_regs, 188 channel->dma_irq, channel->tx_ring, channel->rx_ring); 189 } 190 191 pdata->channel = channel_mem; 192 pdata->channel_count = count; 193 194 return 0; 195 196err_irq: 197 kfree(rx_ring); 198 199err_rx_ring: 200 kfree(tx_ring); 201 202err_tx_ring: 203 kfree(channel_mem); 204 205err_channel: 206 return ret; 207} 208 209static void xgbe_free_channels(struct xgbe_prv_data *pdata) 210{ 211 if (!pdata->channel) 212 return; 213 214 kfree(pdata->channel->rx_ring); 215 kfree(pdata->channel->tx_ring); 216 kfree(pdata->channel); 217 218 pdata->channel = NULL; 219 pdata->channel_count = 0; 220} 221 222static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) 223{ 224 return (ring->rdesc_count - (ring->cur - ring->dirty)); 225} 226 227static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) 228{ 229 return (ring->cur - ring->dirty); 230} 231 232static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, 233 struct xgbe_ring *ring, unsigned int count) 234{ 235 struct xgbe_prv_data *pdata = channel->pdata; 236 237 if (count > xgbe_tx_avail_desc(ring)) { 238 DBGPR(" Tx queue stopped, not enough descriptors available\n"); 239 netif_stop_subqueue(pdata->netdev, channel->queue_index); 240 ring->tx.queue_stopped = 1; 241 242 /* If we haven't notified the hardware because of xmit_more 243 * support, tell it now 244 */ 245 if (ring->tx.xmit_more) 246 pdata->hw_if.tx_start_xmit(channel, ring); 247 248 return NETDEV_TX_BUSY; 249 } 250 251 return 0; 252} 253 254static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) 255{ 256 unsigned int rx_buf_size; 257 258 if (mtu > XGMAC_JUMBO_PACKET_MTU) { 259 netdev_alert(netdev, "MTU exceeds maximum supported value\n"); 260 return -EINVAL; 261 } 262 263 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 264 rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); 265 266 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & 267 ~(XGBE_RX_BUF_ALIGN - 1); 268 269 return rx_buf_size; 270} 271 272static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) 273{ 274 struct xgbe_hw_if *hw_if = &pdata->hw_if; 275 struct xgbe_channel *channel; 276 enum xgbe_int int_id; 277 unsigned int i; 278 279 channel = pdata->channel; 280 for (i = 0; i < pdata->channel_count; i++, channel++) { 281 if (channel->tx_ring && channel->rx_ring) 282 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 283 else if (channel->tx_ring) 284 int_id = XGMAC_INT_DMA_CH_SR_TI; 285 else if (channel->rx_ring) 286 int_id = XGMAC_INT_DMA_CH_SR_RI; 287 else 288 continue; 289 290 hw_if->enable_int(channel, int_id); 291 } 292} 293 294static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) 295{ 296 struct xgbe_hw_if *hw_if = &pdata->hw_if; 297 struct xgbe_channel *channel; 298 enum xgbe_int int_id; 299 unsigned int i; 300 301 channel = pdata->channel; 302 for (i = 0; i < pdata->channel_count; i++, channel++) { 303 if (channel->tx_ring && channel->rx_ring) 304 int_id = XGMAC_INT_DMA_CH_SR_TI_RI; 305 else if (channel->tx_ring) 306 int_id = XGMAC_INT_DMA_CH_SR_TI; 307 else if (channel->rx_ring) 308 int_id = XGMAC_INT_DMA_CH_SR_RI; 309 else 310 continue; 311 312 hw_if->disable_int(channel, int_id); 313 } 314} 315 316static irqreturn_t xgbe_isr(int irq, void *data) 317{ 318 struct xgbe_prv_data *pdata = data; 319 struct xgbe_hw_if *hw_if = &pdata->hw_if; 320 struct xgbe_channel *channel; 321 unsigned int dma_isr, dma_ch_isr; 322 unsigned int mac_isr, mac_tssr; 323 unsigned int i; 324 325 /* The DMA interrupt status register also reports MAC and MTL 326 * interrupts. So for polling mode, we just need to check for 327 * this register to be non-zero 328 */ 329 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); 330 if (!dma_isr) 331 goto isr_done; 332 333 DBGPR(" DMA_ISR = %08x\n", dma_isr); 334 335 for (i = 0; i < pdata->channel_count; i++) { 336 if (!(dma_isr & (1 << i))) 337 continue; 338 339 channel = pdata->channel + i; 340 341 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); 342 DBGPR(" DMA_CH%u_ISR = %08x\n", i, dma_ch_isr); 343 344 /* The TI or RI interrupt bits may still be set even if using 345 * per channel DMA interrupts. Check to be sure those are not 346 * enabled before using the private data napi structure. 347 */ 348 if (!pdata->per_channel_irq && 349 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || 350 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { 351 if (napi_schedule_prep(&pdata->napi)) { 352 /* Disable Tx and Rx interrupts */ 353 xgbe_disable_rx_tx_ints(pdata); 354 355 /* Turn on polling */ 356 __napi_schedule(&pdata->napi); 357 } 358 } 359 360 /* Restart the device on a Fatal Bus Error */ 361 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) 362 schedule_work(&pdata->restart_work); 363 364 /* Clear all interrupt signals */ 365 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); 366 } 367 368 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { 369 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); 370 371 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) 372 hw_if->tx_mmc_int(pdata); 373 374 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) 375 hw_if->rx_mmc_int(pdata); 376 377 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { 378 mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); 379 380 if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { 381 /* Read Tx Timestamp to clear interrupt */ 382 pdata->tx_tstamp = 383 hw_if->get_tx_tstamp(pdata); 384 schedule_work(&pdata->tx_tstamp_work); 385 } 386 } 387 } 388 389 DBGPR(" DMA_ISR = %08x\n", XGMAC_IOREAD(pdata, DMA_ISR)); 390 391isr_done: 392 return IRQ_HANDLED; 393} 394 395static irqreturn_t xgbe_dma_isr(int irq, void *data) 396{ 397 struct xgbe_channel *channel = data; 398 399 /* Per channel DMA interrupts are enabled, so we use the per 400 * channel napi structure and not the private data napi structure 401 */ 402 if (napi_schedule_prep(&channel->napi)) { 403 /* Disable Tx and Rx interrupts */ 404 disable_irq_nosync(channel->dma_irq); 405 406 /* Turn on polling */ 407 __napi_schedule(&channel->napi); 408 } 409 410 return IRQ_HANDLED; 411} 412 413static void xgbe_tx_timer(unsigned long data) 414{ 415 struct xgbe_channel *channel = (struct xgbe_channel *)data; 416 struct xgbe_prv_data *pdata = channel->pdata; 417 struct napi_struct *napi; 418 419 DBGPR("-->xgbe_tx_timer\n"); 420 421 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 422 423 if (napi_schedule_prep(napi)) { 424 /* Disable Tx and Rx interrupts */ 425 if (pdata->per_channel_irq) 426 disable_irq_nosync(channel->dma_irq); 427 else 428 xgbe_disable_rx_tx_ints(pdata); 429 430 /* Turn on polling */ 431 __napi_schedule(napi); 432 } 433 434 channel->tx_timer_active = 0; 435 436 DBGPR("<--xgbe_tx_timer\n"); 437} 438 439static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata) 440{ 441 struct xgbe_channel *channel; 442 unsigned int i; 443 444 DBGPR("-->xgbe_init_tx_timers\n"); 445 446 channel = pdata->channel; 447 for (i = 0; i < pdata->channel_count; i++, channel++) { 448 if (!channel->tx_ring) 449 break; 450 451 DBGPR(" %s adding tx timer\n", channel->name); 452 setup_timer(&channel->tx_timer, xgbe_tx_timer, 453 (unsigned long)channel); 454 } 455 456 DBGPR("<--xgbe_init_tx_timers\n"); 457} 458 459static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata) 460{ 461 struct xgbe_channel *channel; 462 unsigned int i; 463 464 DBGPR("-->xgbe_stop_tx_timers\n"); 465 466 channel = pdata->channel; 467 for (i = 0; i < pdata->channel_count; i++, channel++) { 468 if (!channel->tx_ring) 469 break; 470 471 DBGPR(" %s deleting tx timer\n", channel->name); 472 del_timer_sync(&channel->tx_timer); 473 } 474 475 DBGPR("<--xgbe_stop_tx_timers\n"); 476} 477 478void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) 479{ 480 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 481 struct xgbe_hw_features *hw_feat = &pdata->hw_feat; 482 483 DBGPR("-->xgbe_get_all_hw_features\n"); 484 485 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); 486 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); 487 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); 488 489 memset(hw_feat, 0, sizeof(*hw_feat)); 490 491 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); 492 493 /* Hardware feature register 0 */ 494 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 495 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 496 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 497 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 498 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 499 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 500 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 501 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 502 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 503 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 504 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 505 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 506 ADDMACADRSEL); 507 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 508 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 509 510 /* Hardware feature register 1 */ 511 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 512 RXFIFOSIZE); 513 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 514 TXFIFOSIZE); 515 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 516 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 517 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 518 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 519 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 520 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 521 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 522 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 523 HASHTBLSZ); 524 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 525 L3L4FNUM); 526 527 /* Hardware feature register 2 */ 528 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 529 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 530 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 531 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 532 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 533 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); 534 535 /* Translate the Hash Table size into actual number */ 536 switch (hw_feat->hash_table_size) { 537 case 0: 538 break; 539 case 1: 540 hw_feat->hash_table_size = 64; 541 break; 542 case 2: 543 hw_feat->hash_table_size = 128; 544 break; 545 case 3: 546 hw_feat->hash_table_size = 256; 547 break; 548 } 549 550 /* Translate the address width setting into actual number */ 551 switch (hw_feat->dma_width) { 552 case 0: 553 hw_feat->dma_width = 32; 554 break; 555 case 1: 556 hw_feat->dma_width = 40; 557 break; 558 case 2: 559 hw_feat->dma_width = 48; 560 break; 561 default: 562 hw_feat->dma_width = 32; 563 } 564 565 /* The Queue, Channel and TC counts are zero based so increment them 566 * to get the actual number 567 */ 568 hw_feat->rx_q_cnt++; 569 hw_feat->tx_q_cnt++; 570 hw_feat->rx_ch_cnt++; 571 hw_feat->tx_ch_cnt++; 572 hw_feat->tc_cnt++; 573 574 DBGPR("<--xgbe_get_all_hw_features\n"); 575} 576 577static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) 578{ 579 struct xgbe_channel *channel; 580 unsigned int i; 581 582 if (pdata->per_channel_irq) { 583 channel = pdata->channel; 584 for (i = 0; i < pdata->channel_count; i++, channel++) { 585 if (add) 586 netif_napi_add(pdata->netdev, &channel->napi, 587 xgbe_one_poll, NAPI_POLL_WEIGHT); 588 589 napi_enable(&channel->napi); 590 } 591 } else { 592 if (add) 593 netif_napi_add(pdata->netdev, &pdata->napi, 594 xgbe_all_poll, NAPI_POLL_WEIGHT); 595 596 napi_enable(&pdata->napi); 597 } 598} 599 600static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) 601{ 602 struct xgbe_channel *channel; 603 unsigned int i; 604 605 if (pdata->per_channel_irq) { 606 channel = pdata->channel; 607 for (i = 0; i < pdata->channel_count; i++, channel++) { 608 napi_disable(&channel->napi); 609 610 if (del) 611 netif_napi_del(&channel->napi); 612 } 613 } else { 614 napi_disable(&pdata->napi); 615 616 if (del) 617 netif_napi_del(&pdata->napi); 618 } 619} 620 621static int xgbe_request_irqs(struct xgbe_prv_data *pdata) 622{ 623 struct xgbe_channel *channel; 624 struct net_device *netdev = pdata->netdev; 625 unsigned int i; 626 int ret; 627 628 ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, 629 netdev->name, pdata); 630 if (ret) { 631 netdev_alert(netdev, "error requesting irq %d\n", 632 pdata->dev_irq); 633 return ret; 634 } 635 636 if (!pdata->per_channel_irq) 637 return 0; 638 639 channel = pdata->channel; 640 for (i = 0; i < pdata->channel_count; i++, channel++) { 641 snprintf(channel->dma_irq_name, 642 sizeof(channel->dma_irq_name) - 1, 643 "%s-TxRx-%u", netdev_name(netdev), 644 channel->queue_index); 645 646 ret = devm_request_irq(pdata->dev, channel->dma_irq, 647 xgbe_dma_isr, 0, 648 channel->dma_irq_name, channel); 649 if (ret) { 650 netdev_alert(netdev, "error requesting irq %d\n", 651 channel->dma_irq); 652 goto err_irq; 653 } 654 } 655 656 return 0; 657 658err_irq: 659 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ 660 for (i--, channel--; i < pdata->channel_count; i--, channel--) 661 devm_free_irq(pdata->dev, channel->dma_irq, channel); 662 663 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 664 665 return ret; 666} 667 668static void xgbe_free_irqs(struct xgbe_prv_data *pdata) 669{ 670 struct xgbe_channel *channel; 671 unsigned int i; 672 673 devm_free_irq(pdata->dev, pdata->dev_irq, pdata); 674 675 if (!pdata->per_channel_irq) 676 return; 677 678 channel = pdata->channel; 679 for (i = 0; i < pdata->channel_count; i++, channel++) 680 devm_free_irq(pdata->dev, channel->dma_irq, channel); 681} 682 683void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) 684{ 685 struct xgbe_hw_if *hw_if = &pdata->hw_if; 686 687 DBGPR("-->xgbe_init_tx_coalesce\n"); 688 689 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; 690 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; 691 692 hw_if->config_tx_coalesce(pdata); 693 694 DBGPR("<--xgbe_init_tx_coalesce\n"); 695} 696 697void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) 698{ 699 struct xgbe_hw_if *hw_if = &pdata->hw_if; 700 701 DBGPR("-->xgbe_init_rx_coalesce\n"); 702 703 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); 704 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; 705 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; 706 707 hw_if->config_rx_coalesce(pdata); 708 709 DBGPR("<--xgbe_init_rx_coalesce\n"); 710} 711 712static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) 713{ 714 struct xgbe_desc_if *desc_if = &pdata->desc_if; 715 struct xgbe_channel *channel; 716 struct xgbe_ring *ring; 717 struct xgbe_ring_data *rdata; 718 unsigned int i, j; 719 720 DBGPR("-->xgbe_free_tx_data\n"); 721 722 channel = pdata->channel; 723 for (i = 0; i < pdata->channel_count; i++, channel++) { 724 ring = channel->tx_ring; 725 if (!ring) 726 break; 727 728 for (j = 0; j < ring->rdesc_count; j++) { 729 rdata = XGBE_GET_DESC_DATA(ring, j); 730 desc_if->unmap_rdata(pdata, rdata); 731 } 732 } 733 734 DBGPR("<--xgbe_free_tx_data\n"); 735} 736 737static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) 738{ 739 struct xgbe_desc_if *desc_if = &pdata->desc_if; 740 struct xgbe_channel *channel; 741 struct xgbe_ring *ring; 742 struct xgbe_ring_data *rdata; 743 unsigned int i, j; 744 745 DBGPR("-->xgbe_free_rx_data\n"); 746 747 channel = pdata->channel; 748 for (i = 0; i < pdata->channel_count; i++, channel++) { 749 ring = channel->rx_ring; 750 if (!ring) 751 break; 752 753 for (j = 0; j < ring->rdesc_count; j++) { 754 rdata = XGBE_GET_DESC_DATA(ring, j); 755 desc_if->unmap_rdata(pdata, rdata); 756 } 757 } 758 759 DBGPR("<--xgbe_free_rx_data\n"); 760} 761 762static void xgbe_adjust_link(struct net_device *netdev) 763{ 764 struct xgbe_prv_data *pdata = netdev_priv(netdev); 765 struct xgbe_hw_if *hw_if = &pdata->hw_if; 766 struct phy_device *phydev = pdata->phydev; 767 int new_state = 0; 768 769 if (!phydev) 770 return; 771 772 if (phydev->link) { 773 /* Flow control support */ 774 if (pdata->pause_autoneg) { 775 if (phydev->pause || phydev->asym_pause) { 776 pdata->tx_pause = 1; 777 pdata->rx_pause = 1; 778 } else { 779 pdata->tx_pause = 0; 780 pdata->rx_pause = 0; 781 } 782 } 783 784 if (pdata->tx_pause != pdata->phy_tx_pause) { 785 hw_if->config_tx_flow_control(pdata); 786 pdata->phy_tx_pause = pdata->tx_pause; 787 } 788 789 if (pdata->rx_pause != pdata->phy_rx_pause) { 790 hw_if->config_rx_flow_control(pdata); 791 pdata->phy_rx_pause = pdata->rx_pause; 792 } 793 794 /* Speed support */ 795 if (phydev->speed != pdata->phy_speed) { 796 new_state = 1; 797 798 switch (phydev->speed) { 799 case SPEED_10000: 800 hw_if->set_xgmii_speed(pdata); 801 break; 802 803 case SPEED_2500: 804 hw_if->set_gmii_2500_speed(pdata); 805 break; 806 807 case SPEED_1000: 808 hw_if->set_gmii_speed(pdata); 809 break; 810 } 811 pdata->phy_speed = phydev->speed; 812 } 813 814 if (phydev->link != pdata->phy_link) { 815 new_state = 1; 816 pdata->phy_link = 1; 817 } 818 } else if (pdata->phy_link) { 819 new_state = 1; 820 pdata->phy_link = 0; 821 pdata->phy_speed = SPEED_UNKNOWN; 822 } 823 824 if (new_state) 825 phy_print_status(phydev); 826} 827 828static int xgbe_phy_init(struct xgbe_prv_data *pdata) 829{ 830 struct net_device *netdev = pdata->netdev; 831 struct phy_device *phydev = pdata->phydev; 832 int ret; 833 834 pdata->phy_link = -1; 835 pdata->phy_speed = SPEED_UNKNOWN; 836 pdata->phy_tx_pause = pdata->tx_pause; 837 pdata->phy_rx_pause = pdata->rx_pause; 838 839 ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link, 840 pdata->phy_mode); 841 if (ret) { 842 netdev_err(netdev, "phy_connect_direct failed\n"); 843 return ret; 844 } 845 846 if (!phydev->drv || (phydev->drv->phy_id == 0)) { 847 netdev_err(netdev, "phy_id not valid\n"); 848 ret = -ENODEV; 849 goto err_phy_connect; 850 } 851 DBGPR(" phy_connect_direct succeeded for PHY %s, link=%d\n", 852 dev_name(&phydev->dev), phydev->link); 853 854 return 0; 855 856err_phy_connect: 857 phy_disconnect(phydev); 858 859 return ret; 860} 861 862static void xgbe_phy_exit(struct xgbe_prv_data *pdata) 863{ 864 if (!pdata->phydev) 865 return; 866 867 phy_disconnect(pdata->phydev); 868} 869 870int xgbe_powerdown(struct net_device *netdev, unsigned int caller) 871{ 872 struct xgbe_prv_data *pdata = netdev_priv(netdev); 873 struct xgbe_hw_if *hw_if = &pdata->hw_if; 874 unsigned long flags; 875 876 DBGPR("-->xgbe_powerdown\n"); 877 878 if (!netif_running(netdev) || 879 (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { 880 netdev_alert(netdev, "Device is already powered down\n"); 881 DBGPR("<--xgbe_powerdown\n"); 882 return -EINVAL; 883 } 884 885 spin_lock_irqsave(&pdata->lock, flags); 886 887 if (caller == XGMAC_DRIVER_CONTEXT) 888 netif_device_detach(netdev); 889 890 netif_tx_stop_all_queues(netdev); 891 892 hw_if->powerdown_tx(pdata); 893 hw_if->powerdown_rx(pdata); 894 895 xgbe_napi_disable(pdata, 0); 896 897 phy_stop(pdata->phydev); 898 899 pdata->power_down = 1; 900 901 spin_unlock_irqrestore(&pdata->lock, flags); 902 903 DBGPR("<--xgbe_powerdown\n"); 904 905 return 0; 906} 907 908int xgbe_powerup(struct net_device *netdev, unsigned int caller) 909{ 910 struct xgbe_prv_data *pdata = netdev_priv(netdev); 911 struct xgbe_hw_if *hw_if = &pdata->hw_if; 912 unsigned long flags; 913 914 DBGPR("-->xgbe_powerup\n"); 915 916 if (!netif_running(netdev) || 917 (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { 918 netdev_alert(netdev, "Device is already powered up\n"); 919 DBGPR("<--xgbe_powerup\n"); 920 return -EINVAL; 921 } 922 923 spin_lock_irqsave(&pdata->lock, flags); 924 925 pdata->power_down = 0; 926 927 phy_start(pdata->phydev); 928 929 xgbe_napi_enable(pdata, 0); 930 931 hw_if->powerup_tx(pdata); 932 hw_if->powerup_rx(pdata); 933 934 if (caller == XGMAC_DRIVER_CONTEXT) 935 netif_device_attach(netdev); 936 937 netif_tx_start_all_queues(netdev); 938 939 spin_unlock_irqrestore(&pdata->lock, flags); 940 941 DBGPR("<--xgbe_powerup\n"); 942 943 return 0; 944} 945 946static int xgbe_start(struct xgbe_prv_data *pdata) 947{ 948 struct xgbe_hw_if *hw_if = &pdata->hw_if; 949 struct net_device *netdev = pdata->netdev; 950 int ret; 951 952 DBGPR("-->xgbe_start\n"); 953 954 hw_if->init(pdata); 955 956 phy_start(pdata->phydev); 957 958 xgbe_napi_enable(pdata, 1); 959 960 ret = xgbe_request_irqs(pdata); 961 if (ret) 962 goto err_napi; 963 964 hw_if->enable_tx(pdata); 965 hw_if->enable_rx(pdata); 966 967 xgbe_init_tx_timers(pdata); 968 969 netif_tx_start_all_queues(netdev); 970 971 DBGPR("<--xgbe_start\n"); 972 973 return 0; 974 975err_napi: 976 xgbe_napi_disable(pdata, 1); 977 978 phy_stop(pdata->phydev); 979 980 hw_if->exit(pdata); 981 982 return ret; 983} 984 985static void xgbe_stop(struct xgbe_prv_data *pdata) 986{ 987 struct xgbe_hw_if *hw_if = &pdata->hw_if; 988 struct xgbe_channel *channel; 989 struct net_device *netdev = pdata->netdev; 990 struct netdev_queue *txq; 991 unsigned int i; 992 993 DBGPR("-->xgbe_stop\n"); 994 995 netif_tx_stop_all_queues(netdev); 996 997 xgbe_stop_tx_timers(pdata); 998 999 hw_if->disable_tx(pdata); 1000 hw_if->disable_rx(pdata); 1001 1002 xgbe_free_irqs(pdata); 1003 1004 xgbe_napi_disable(pdata, 1); 1005 1006 phy_stop(pdata->phydev); 1007 1008 hw_if->exit(pdata); 1009 1010 channel = pdata->channel; 1011 for (i = 0; i < pdata->channel_count; i++, channel++) { 1012 if (!channel->tx_ring) 1013 continue; 1014 1015 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1016 netdev_tx_reset_queue(txq); 1017 } 1018 1019 DBGPR("<--xgbe_stop\n"); 1020} 1021 1022static void xgbe_restart_dev(struct xgbe_prv_data *pdata) 1023{ 1024 DBGPR("-->xgbe_restart_dev\n"); 1025 1026 /* If not running, "restart" will happen on open */ 1027 if (!netif_running(pdata->netdev)) 1028 return; 1029 1030 xgbe_stop(pdata); 1031 1032 xgbe_free_tx_data(pdata); 1033 xgbe_free_rx_data(pdata); 1034 1035 xgbe_start(pdata); 1036 1037 DBGPR("<--xgbe_restart_dev\n"); 1038} 1039 1040static void xgbe_restart(struct work_struct *work) 1041{ 1042 struct xgbe_prv_data *pdata = container_of(work, 1043 struct xgbe_prv_data, 1044 restart_work); 1045 1046 rtnl_lock(); 1047 1048 xgbe_restart_dev(pdata); 1049 1050 rtnl_unlock(); 1051} 1052 1053static void xgbe_tx_tstamp(struct work_struct *work) 1054{ 1055 struct xgbe_prv_data *pdata = container_of(work, 1056 struct xgbe_prv_data, 1057 tx_tstamp_work); 1058 struct skb_shared_hwtstamps hwtstamps; 1059 u64 nsec; 1060 unsigned long flags; 1061 1062 if (pdata->tx_tstamp) { 1063 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 1064 pdata->tx_tstamp); 1065 1066 memset(&hwtstamps, 0, sizeof(hwtstamps)); 1067 hwtstamps.hwtstamp = ns_to_ktime(nsec); 1068 skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); 1069 } 1070 1071 dev_kfree_skb_any(pdata->tx_tstamp_skb); 1072 1073 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1074 pdata->tx_tstamp_skb = NULL; 1075 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1076} 1077 1078static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, 1079 struct ifreq *ifreq) 1080{ 1081 if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, 1082 sizeof(pdata->tstamp_config))) 1083 return -EFAULT; 1084 1085 return 0; 1086} 1087 1088static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, 1089 struct ifreq *ifreq) 1090{ 1091 struct hwtstamp_config config; 1092 unsigned int mac_tscr; 1093 1094 if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) 1095 return -EFAULT; 1096 1097 if (config.flags) 1098 return -EINVAL; 1099 1100 mac_tscr = 0; 1101 1102 switch (config.tx_type) { 1103 case HWTSTAMP_TX_OFF: 1104 break; 1105 1106 case HWTSTAMP_TX_ON: 1107 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1108 break; 1109 1110 default: 1111 return -ERANGE; 1112 } 1113 1114 switch (config.rx_filter) { 1115 case HWTSTAMP_FILTER_NONE: 1116 break; 1117 1118 case HWTSTAMP_FILTER_ALL: 1119 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); 1120 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1121 break; 1122 1123 /* PTP v2, UDP, any kind of event packet */ 1124 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1125 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1126 /* PTP v1, UDP, any kind of event packet */ 1127 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1128 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1129 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1130 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1131 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1132 break; 1133 1134 /* PTP v2, UDP, Sync packet */ 1135 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1136 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1137 /* PTP v1, UDP, Sync packet */ 1138 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1139 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1140 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1141 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1142 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1143 break; 1144 1145 /* PTP v2, UDP, Delay_req packet */ 1146 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1147 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1148 /* PTP v1, UDP, Delay_req packet */ 1149 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1150 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1151 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1152 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1153 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1154 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1155 break; 1156 1157 /* 802.AS1, Ethernet, any kind of event packet */ 1158 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1159 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1160 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1161 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1162 break; 1163 1164 /* 802.AS1, Ethernet, Sync packet */ 1165 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1166 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1167 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1168 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1169 break; 1170 1171 /* 802.AS1, Ethernet, Delay_req packet */ 1172 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1173 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); 1174 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1175 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1176 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1177 break; 1178 1179 /* PTP v2/802.AS1, any layer, any kind of event packet */ 1180 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1181 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1182 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1183 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1184 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1185 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); 1186 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1187 break; 1188 1189 /* PTP v2/802.AS1, any layer, Sync packet */ 1190 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1191 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1192 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1193 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1194 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1195 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1196 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1197 break; 1198 1199 /* PTP v2/802.AS1, any layer, Delay_req packet */ 1200 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1201 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); 1202 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); 1203 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); 1204 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); 1205 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); 1206 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); 1207 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); 1208 break; 1209 1210 default: 1211 return -ERANGE; 1212 } 1213 1214 pdata->hw_if.config_tstamp(pdata, mac_tscr); 1215 1216 memcpy(&pdata->tstamp_config, &config, sizeof(config)); 1217 1218 return 0; 1219} 1220 1221static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, 1222 struct sk_buff *skb, 1223 struct xgbe_packet_data *packet) 1224{ 1225 unsigned long flags; 1226 1227 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { 1228 spin_lock_irqsave(&pdata->tstamp_lock, flags); 1229 if (pdata->tx_tstamp_skb) { 1230 /* Another timestamp in progress, ignore this one */ 1231 XGMAC_SET_BITS(packet->attributes, 1232 TX_PACKET_ATTRIBUTES, PTP, 0); 1233 } else { 1234 pdata->tx_tstamp_skb = skb_get(skb); 1235 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1236 } 1237 spin_unlock_irqrestore(&pdata->tstamp_lock, flags); 1238 } 1239 1240 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) 1241 skb_tx_timestamp(skb); 1242} 1243 1244static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) 1245{ 1246 if (skb_vlan_tag_present(skb)) 1247 packet->vlan_ctag = skb_vlan_tag_get(skb); 1248} 1249 1250static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) 1251{ 1252 int ret; 1253 1254 if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1255 TSO_ENABLE)) 1256 return 0; 1257 1258 ret = skb_cow_head(skb, 0); 1259 if (ret) 1260 return ret; 1261 1262 packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 1263 packet->tcp_header_len = tcp_hdrlen(skb); 1264 packet->tcp_payload_len = skb->len - packet->header_len; 1265 packet->mss = skb_shinfo(skb)->gso_size; 1266 DBGPR(" packet->header_len=%u\n", packet->header_len); 1267 DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", 1268 packet->tcp_header_len, packet->tcp_payload_len); 1269 DBGPR(" packet->mss=%u\n", packet->mss); 1270 1271 /* Update the number of packets that will ultimately be transmitted 1272 * along with the extra bytes for each extra packet 1273 */ 1274 packet->tx_packets = skb_shinfo(skb)->gso_segs; 1275 packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; 1276 1277 return 0; 1278} 1279 1280static int xgbe_is_tso(struct sk_buff *skb) 1281{ 1282 if (skb->ip_summed != CHECKSUM_PARTIAL) 1283 return 0; 1284 1285 if (!skb_is_gso(skb)) 1286 return 0; 1287 1288 DBGPR(" TSO packet to be processed\n"); 1289 1290 return 1; 1291} 1292 1293static void xgbe_packet_info(struct xgbe_prv_data *pdata, 1294 struct xgbe_ring *ring, struct sk_buff *skb, 1295 struct xgbe_packet_data *packet) 1296{ 1297 struct skb_frag_struct *frag; 1298 unsigned int context_desc; 1299 unsigned int len; 1300 unsigned int i; 1301 1302 packet->skb = skb; 1303 1304 context_desc = 0; 1305 packet->rdesc_count = 0; 1306 1307 packet->tx_packets = 1; 1308 packet->tx_bytes = skb->len; 1309 1310 if (xgbe_is_tso(skb)) { 1311 /* TSO requires an extra descriptor if mss is different */ 1312 if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { 1313 context_desc = 1; 1314 packet->rdesc_count++; 1315 } 1316 1317 /* TSO requires an extra descriptor for TSO header */ 1318 packet->rdesc_count++; 1319 1320 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1321 TSO_ENABLE, 1); 1322 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1323 CSUM_ENABLE, 1); 1324 } else if (skb->ip_summed == CHECKSUM_PARTIAL) 1325 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1326 CSUM_ENABLE, 1); 1327 1328 if (skb_vlan_tag_present(skb)) { 1329 /* VLAN requires an extra descriptor if tag is different */ 1330 if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) 1331 /* We can share with the TSO context descriptor */ 1332 if (!context_desc) { 1333 context_desc = 1; 1334 packet->rdesc_count++; 1335 } 1336 1337 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1338 VLAN_CTAG, 1); 1339 } 1340 1341 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 1342 (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) 1343 XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, 1344 PTP, 1); 1345 1346 for (len = skb_headlen(skb); len;) { 1347 packet->rdesc_count++; 1348 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1349 } 1350 1351 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1352 frag = &skb_shinfo(skb)->frags[i]; 1353 for (len = skb_frag_size(frag); len; ) { 1354 packet->rdesc_count++; 1355 len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); 1356 } 1357 } 1358} 1359 1360static int xgbe_open(struct net_device *netdev) 1361{ 1362 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1363 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1364 int ret; 1365 1366 DBGPR("-->xgbe_open\n"); 1367 1368 /* Initialize the phy */ 1369 ret = xgbe_phy_init(pdata); 1370 if (ret) 1371 return ret; 1372 1373 /* Enable the clocks */ 1374 ret = clk_prepare_enable(pdata->sysclk); 1375 if (ret) { 1376 netdev_alert(netdev, "dma clk_prepare_enable failed\n"); 1377 goto err_phy_init; 1378 } 1379 1380 ret = clk_prepare_enable(pdata->ptpclk); 1381 if (ret) { 1382 netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); 1383 goto err_sysclk; 1384 } 1385 1386 /* Calculate the Rx buffer size before allocating rings */ 1387 ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu); 1388 if (ret < 0) 1389 goto err_ptpclk; 1390 pdata->rx_buf_size = ret; 1391 1392 /* Allocate the channel and ring structures */ 1393 ret = xgbe_alloc_channels(pdata); 1394 if (ret) 1395 goto err_ptpclk; 1396 1397 /* Allocate the ring descriptors and buffers */ 1398 ret = desc_if->alloc_ring_resources(pdata); 1399 if (ret) 1400 goto err_channels; 1401 1402 /* Initialize the device restart and Tx timestamp work struct */ 1403 INIT_WORK(&pdata->restart_work, xgbe_restart); 1404 INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); 1405 1406 ret = xgbe_start(pdata); 1407 if (ret) 1408 goto err_rings; 1409 1410 DBGPR("<--xgbe_open\n"); 1411 1412 return 0; 1413 1414err_rings: 1415 desc_if->free_ring_resources(pdata); 1416 1417err_channels: 1418 xgbe_free_channels(pdata); 1419 1420err_ptpclk: 1421 clk_disable_unprepare(pdata->ptpclk); 1422 1423err_sysclk: 1424 clk_disable_unprepare(pdata->sysclk); 1425 1426err_phy_init: 1427 xgbe_phy_exit(pdata); 1428 1429 return ret; 1430} 1431 1432static int xgbe_close(struct net_device *netdev) 1433{ 1434 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1435 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1436 1437 DBGPR("-->xgbe_close\n"); 1438 1439 /* Stop the device */ 1440 xgbe_stop(pdata); 1441 1442 /* Free the ring descriptors and buffers */ 1443 desc_if->free_ring_resources(pdata); 1444 1445 /* Free the channel and ring structures */ 1446 xgbe_free_channels(pdata); 1447 1448 /* Disable the clocks */ 1449 clk_disable_unprepare(pdata->ptpclk); 1450 clk_disable_unprepare(pdata->sysclk); 1451 1452 /* Release the phy */ 1453 xgbe_phy_exit(pdata); 1454 1455 DBGPR("<--xgbe_close\n"); 1456 1457 return 0; 1458} 1459 1460static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) 1461{ 1462 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1463 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1464 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1465 struct xgbe_channel *channel; 1466 struct xgbe_ring *ring; 1467 struct xgbe_packet_data *packet; 1468 struct netdev_queue *txq; 1469 int ret; 1470 1471 DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); 1472 1473 channel = pdata->channel + skb->queue_mapping; 1474 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1475 ring = channel->tx_ring; 1476 packet = &ring->packet_data; 1477 1478 ret = NETDEV_TX_OK; 1479 1480 if (skb->len == 0) { 1481 netdev_err(netdev, "empty skb received from stack\n"); 1482 dev_kfree_skb_any(skb); 1483 goto tx_netdev_return; 1484 } 1485 1486 /* Calculate preliminary packet info */ 1487 memset(packet, 0, sizeof(*packet)); 1488 xgbe_packet_info(pdata, ring, skb, packet); 1489 1490 /* Check that there are enough descriptors available */ 1491 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); 1492 if (ret) 1493 goto tx_netdev_return; 1494 1495 ret = xgbe_prep_tso(skb, packet); 1496 if (ret) { 1497 netdev_err(netdev, "error processing TSO packet\n"); 1498 dev_kfree_skb_any(skb); 1499 goto tx_netdev_return; 1500 } 1501 xgbe_prep_vlan(skb, packet); 1502 1503 if (!desc_if->map_tx_skb(channel, skb)) { 1504 dev_kfree_skb_any(skb); 1505 goto tx_netdev_return; 1506 } 1507 1508 xgbe_prep_tx_tstamp(pdata, skb, packet); 1509 1510 /* Report on the actual number of bytes (to be) sent */ 1511 netdev_tx_sent_queue(txq, packet->tx_bytes); 1512 1513 /* Configure required descriptor fields for transmission */ 1514 hw_if->dev_xmit(channel); 1515 1516#ifdef XGMAC_ENABLE_TX_PKT_DUMP 1517 xgbe_print_pkt(netdev, skb, true); 1518#endif 1519 1520 /* Stop the queue in advance if there may not be enough descriptors */ 1521 xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); 1522 1523 ret = NETDEV_TX_OK; 1524 1525tx_netdev_return: 1526 return ret; 1527} 1528 1529static void xgbe_set_rx_mode(struct net_device *netdev) 1530{ 1531 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1532 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1533 1534 DBGPR("-->xgbe_set_rx_mode\n"); 1535 1536 hw_if->config_rx_mode(pdata); 1537 1538 DBGPR("<--xgbe_set_rx_mode\n"); 1539} 1540 1541static int xgbe_set_mac_address(struct net_device *netdev, void *addr) 1542{ 1543 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1544 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1545 struct sockaddr *saddr = addr; 1546 1547 DBGPR("-->xgbe_set_mac_address\n"); 1548 1549 if (!is_valid_ether_addr(saddr->sa_data)) 1550 return -EADDRNOTAVAIL; 1551 1552 memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); 1553 1554 hw_if->set_mac_address(pdata, netdev->dev_addr); 1555 1556 DBGPR("<--xgbe_set_mac_address\n"); 1557 1558 return 0; 1559} 1560 1561static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) 1562{ 1563 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1564 int ret; 1565 1566 switch (cmd) { 1567 case SIOCGHWTSTAMP: 1568 ret = xgbe_get_hwtstamp_settings(pdata, ifreq); 1569 break; 1570 1571 case SIOCSHWTSTAMP: 1572 ret = xgbe_set_hwtstamp_settings(pdata, ifreq); 1573 break; 1574 1575 default: 1576 ret = -EOPNOTSUPP; 1577 } 1578 1579 return ret; 1580} 1581 1582static int xgbe_change_mtu(struct net_device *netdev, int mtu) 1583{ 1584 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1585 int ret; 1586 1587 DBGPR("-->xgbe_change_mtu\n"); 1588 1589 ret = xgbe_calc_rx_buf_size(netdev, mtu); 1590 if (ret < 0) 1591 return ret; 1592 1593 pdata->rx_buf_size = ret; 1594 netdev->mtu = mtu; 1595 1596 xgbe_restart_dev(pdata); 1597 1598 DBGPR("<--xgbe_change_mtu\n"); 1599 1600 return 0; 1601} 1602 1603static void xgbe_tx_timeout(struct net_device *netdev) 1604{ 1605 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1606 1607 netdev_warn(netdev, "tx timeout, device restarting\n"); 1608 schedule_work(&pdata->restart_work); 1609} 1610 1611static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev, 1612 struct rtnl_link_stats64 *s) 1613{ 1614 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1615 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; 1616 1617 DBGPR("-->%s\n", __func__); 1618 1619 pdata->hw_if.read_mmc_stats(pdata); 1620 1621 s->rx_packets = pstats->rxframecount_gb; 1622 s->rx_bytes = pstats->rxoctetcount_gb; 1623 s->rx_errors = pstats->rxframecount_gb - 1624 pstats->rxbroadcastframes_g - 1625 pstats->rxmulticastframes_g - 1626 pstats->rxunicastframes_g; 1627 s->multicast = pstats->rxmulticastframes_g; 1628 s->rx_length_errors = pstats->rxlengtherror; 1629 s->rx_crc_errors = pstats->rxcrcerror; 1630 s->rx_fifo_errors = pstats->rxfifooverflow; 1631 1632 s->tx_packets = pstats->txframecount_gb; 1633 s->tx_bytes = pstats->txoctetcount_gb; 1634 s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; 1635 s->tx_dropped = netdev->stats.tx_dropped; 1636 1637 DBGPR("<--%s\n", __func__); 1638 1639 return s; 1640} 1641 1642static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1643 u16 vid) 1644{ 1645 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1646 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1647 1648 DBGPR("-->%s\n", __func__); 1649 1650 set_bit(vid, pdata->active_vlans); 1651 hw_if->update_vlan_hash_table(pdata); 1652 1653 DBGPR("<--%s\n", __func__); 1654 1655 return 0; 1656} 1657 1658static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1659 u16 vid) 1660{ 1661 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1662 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1663 1664 DBGPR("-->%s\n", __func__); 1665 1666 clear_bit(vid, pdata->active_vlans); 1667 hw_if->update_vlan_hash_table(pdata); 1668 1669 DBGPR("<--%s\n", __func__); 1670 1671 return 0; 1672} 1673 1674#ifdef CONFIG_NET_POLL_CONTROLLER 1675static void xgbe_poll_controller(struct net_device *netdev) 1676{ 1677 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1678 struct xgbe_channel *channel; 1679 unsigned int i; 1680 1681 DBGPR("-->xgbe_poll_controller\n"); 1682 1683 if (pdata->per_channel_irq) { 1684 channel = pdata->channel; 1685 for (i = 0; i < pdata->channel_count; i++, channel++) 1686 xgbe_dma_isr(channel->dma_irq, channel); 1687 } else { 1688 disable_irq(pdata->dev_irq); 1689 xgbe_isr(pdata->dev_irq, pdata); 1690 enable_irq(pdata->dev_irq); 1691 } 1692 1693 DBGPR("<--xgbe_poll_controller\n"); 1694} 1695#endif /* End CONFIG_NET_POLL_CONTROLLER */ 1696 1697static int xgbe_setup_tc(struct net_device *netdev, u8 tc) 1698{ 1699 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1700 unsigned int offset, queue; 1701 u8 i; 1702 1703 if (tc && (tc != pdata->hw_feat.tc_cnt)) 1704 return -EINVAL; 1705 1706 if (tc) { 1707 netdev_set_num_tc(netdev, tc); 1708 for (i = 0, queue = 0, offset = 0; i < tc; i++) { 1709 while ((queue < pdata->tx_q_count) && 1710 (pdata->q2tc_map[queue] == i)) 1711 queue++; 1712 1713 DBGPR(" TC%u using TXq%u-%u\n", i, offset, queue - 1); 1714 netdev_set_tc_queue(netdev, i, queue - offset, offset); 1715 offset = queue; 1716 } 1717 } else { 1718 netdev_reset_tc(netdev); 1719 } 1720 1721 return 0; 1722} 1723 1724static int xgbe_set_features(struct net_device *netdev, 1725 netdev_features_t features) 1726{ 1727 struct xgbe_prv_data *pdata = netdev_priv(netdev); 1728 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1729 netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; 1730 int ret = 0; 1731 1732 rxhash = pdata->netdev_features & NETIF_F_RXHASH; 1733 rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; 1734 rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; 1735 rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; 1736 1737 if ((features & NETIF_F_RXHASH) && !rxhash) 1738 ret = hw_if->enable_rss(pdata); 1739 else if (!(features & NETIF_F_RXHASH) && rxhash) 1740 ret = hw_if->disable_rss(pdata); 1741 if (ret) 1742 return ret; 1743 1744 if ((features & NETIF_F_RXCSUM) && !rxcsum) 1745 hw_if->enable_rx_csum(pdata); 1746 else if (!(features & NETIF_F_RXCSUM) && rxcsum) 1747 hw_if->disable_rx_csum(pdata); 1748 1749 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) 1750 hw_if->enable_rx_vlan_stripping(pdata); 1751 else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) 1752 hw_if->disable_rx_vlan_stripping(pdata); 1753 1754 if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) 1755 hw_if->enable_rx_vlan_filtering(pdata); 1756 else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) 1757 hw_if->disable_rx_vlan_filtering(pdata); 1758 1759 pdata->netdev_features = features; 1760 1761 DBGPR("<--xgbe_set_features\n"); 1762 1763 return 0; 1764} 1765 1766static const struct net_device_ops xgbe_netdev_ops = { 1767 .ndo_open = xgbe_open, 1768 .ndo_stop = xgbe_close, 1769 .ndo_start_xmit = xgbe_xmit, 1770 .ndo_set_rx_mode = xgbe_set_rx_mode, 1771 .ndo_set_mac_address = xgbe_set_mac_address, 1772 .ndo_validate_addr = eth_validate_addr, 1773 .ndo_do_ioctl = xgbe_ioctl, 1774 .ndo_change_mtu = xgbe_change_mtu, 1775 .ndo_tx_timeout = xgbe_tx_timeout, 1776 .ndo_get_stats64 = xgbe_get_stats64, 1777 .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, 1778 .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, 1779#ifdef CONFIG_NET_POLL_CONTROLLER 1780 .ndo_poll_controller = xgbe_poll_controller, 1781#endif 1782 .ndo_setup_tc = xgbe_setup_tc, 1783 .ndo_set_features = xgbe_set_features, 1784}; 1785 1786struct net_device_ops *xgbe_get_netdev_ops(void) 1787{ 1788 return (struct net_device_ops *)&xgbe_netdev_ops; 1789} 1790 1791static void xgbe_rx_refresh(struct xgbe_channel *channel) 1792{ 1793 struct xgbe_prv_data *pdata = channel->pdata; 1794 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1795 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1796 struct xgbe_ring *ring = channel->rx_ring; 1797 struct xgbe_ring_data *rdata; 1798 1799 while (ring->dirty != ring->cur) { 1800 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 1801 1802 /* Reset rdata values */ 1803 desc_if->unmap_rdata(pdata, rdata); 1804 1805 if (desc_if->map_rx_buffer(pdata, ring, rdata)) 1806 break; 1807 1808 hw_if->rx_desc_reset(pdata, rdata, ring->dirty); 1809 1810 ring->dirty++; 1811 } 1812 1813 /* Make sure everything is written before the register write */ 1814 wmb(); 1815 1816 /* Update the Rx Tail Pointer Register with address of 1817 * the last cleaned entry */ 1818 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); 1819 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, 1820 lower_32_bits(rdata->rdesc_dma)); 1821} 1822 1823static struct sk_buff *xgbe_create_skb(struct napi_struct *napi, 1824 struct xgbe_ring_data *rdata, 1825 unsigned int *len) 1826{ 1827 struct sk_buff *skb; 1828 u8 *packet; 1829 unsigned int copy_len; 1830 1831 skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); 1832 if (!skb) 1833 return NULL; 1834 1835 packet = page_address(rdata->rx.hdr.pa.pages) + 1836 rdata->rx.hdr.pa.pages_offset; 1837 copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : *len; 1838 copy_len = min(rdata->rx.hdr.dma_len, copy_len); 1839 skb_copy_to_linear_data(skb, packet, copy_len); 1840 skb_put(skb, copy_len); 1841 1842 *len -= copy_len; 1843 1844 return skb; 1845} 1846 1847static int xgbe_tx_poll(struct xgbe_channel *channel) 1848{ 1849 struct xgbe_prv_data *pdata = channel->pdata; 1850 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1851 struct xgbe_desc_if *desc_if = &pdata->desc_if; 1852 struct xgbe_ring *ring = channel->tx_ring; 1853 struct xgbe_ring_data *rdata; 1854 struct xgbe_ring_desc *rdesc; 1855 struct net_device *netdev = pdata->netdev; 1856 struct netdev_queue *txq; 1857 int processed = 0; 1858 unsigned int tx_packets = 0, tx_bytes = 0; 1859 1860 DBGPR("-->xgbe_tx_poll\n"); 1861 1862 /* Nothing to do if there isn't a Tx ring for this channel */ 1863 if (!ring) 1864 return 0; 1865 1866 txq = netdev_get_tx_queue(netdev, channel->queue_index); 1867 1868 while ((processed < XGBE_TX_DESC_MAX_PROC) && 1869 (ring->dirty != ring->cur)) { 1870 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); 1871 rdesc = rdata->rdesc; 1872 1873 if (!hw_if->tx_complete(rdesc)) 1874 break; 1875 1876 /* Make sure descriptor fields are read after reading the OWN 1877 * bit */ 1878 dma_rmb(); 1879 1880#ifdef XGMAC_ENABLE_TX_DESC_DUMP 1881 xgbe_dump_tx_desc(ring, ring->dirty, 1, 0); 1882#endif 1883 1884 if (hw_if->is_last_desc(rdesc)) { 1885 tx_packets += rdata->tx.packets; 1886 tx_bytes += rdata->tx.bytes; 1887 } 1888 1889 /* Free the SKB and reset the descriptor for re-use */ 1890 desc_if->unmap_rdata(pdata, rdata); 1891 hw_if->tx_desc_reset(rdata); 1892 1893 processed++; 1894 ring->dirty++; 1895 } 1896 1897 if (!processed) 1898 return 0; 1899 1900 netdev_tx_completed_queue(txq, tx_packets, tx_bytes); 1901 1902 if ((ring->tx.queue_stopped == 1) && 1903 (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { 1904 ring->tx.queue_stopped = 0; 1905 netif_tx_wake_queue(txq); 1906 } 1907 1908 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); 1909 1910 return processed; 1911} 1912 1913static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) 1914{ 1915 struct xgbe_prv_data *pdata = channel->pdata; 1916 struct xgbe_hw_if *hw_if = &pdata->hw_if; 1917 struct xgbe_ring *ring = channel->rx_ring; 1918 struct xgbe_ring_data *rdata; 1919 struct xgbe_packet_data *packet; 1920 struct net_device *netdev = pdata->netdev; 1921 struct napi_struct *napi; 1922 struct sk_buff *skb; 1923 struct skb_shared_hwtstamps *hwtstamps; 1924 unsigned int incomplete, error, context_next, context; 1925 unsigned int len, put_len, max_len; 1926 unsigned int received = 0; 1927 int packet_count = 0; 1928 1929 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); 1930 1931 /* Nothing to do if there isn't a Rx ring for this channel */ 1932 if (!ring) 1933 return 0; 1934 1935 napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; 1936 1937 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1938 packet = &ring->packet_data; 1939 while (packet_count < budget) { 1940 DBGPR(" cur = %d\n", ring->cur); 1941 1942 /* First time in loop see if we need to restore state */ 1943 if (!received && rdata->state_saved) { 1944 incomplete = rdata->state.incomplete; 1945 context_next = rdata->state.context_next; 1946 skb = rdata->state.skb; 1947 error = rdata->state.error; 1948 len = rdata->state.len; 1949 } else { 1950 memset(packet, 0, sizeof(*packet)); 1951 incomplete = 0; 1952 context_next = 0; 1953 skb = NULL; 1954 error = 0; 1955 len = 0; 1956 } 1957 1958read_again: 1959 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 1960 1961 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) 1962 xgbe_rx_refresh(channel); 1963 1964 if (hw_if->dev_read(channel)) 1965 break; 1966 1967 received++; 1968 ring->cur++; 1969 1970 incomplete = XGMAC_GET_BITS(packet->attributes, 1971 RX_PACKET_ATTRIBUTES, 1972 INCOMPLETE); 1973 context_next = XGMAC_GET_BITS(packet->attributes, 1974 RX_PACKET_ATTRIBUTES, 1975 CONTEXT_NEXT); 1976 context = XGMAC_GET_BITS(packet->attributes, 1977 RX_PACKET_ATTRIBUTES, 1978 CONTEXT); 1979 1980 /* Earlier error, just drain the remaining data */ 1981 if ((incomplete || context_next) && error) 1982 goto read_again; 1983 1984 if (error || packet->errors) { 1985 if (packet->errors) 1986 DBGPR("Error in received packet\n"); 1987 dev_kfree_skb(skb); 1988 goto next_packet; 1989 } 1990 1991 if (!context) { 1992 put_len = rdata->rx.len - len; 1993 len += put_len; 1994 1995 if (!skb) { 1996 dma_sync_single_for_cpu(pdata->dev, 1997 rdata->rx.hdr.dma, 1998 rdata->rx.hdr.dma_len, 1999 DMA_FROM_DEVICE); 2000 2001 skb = xgbe_create_skb(napi, rdata, &put_len); 2002 if (!skb) { 2003 error = 1; 2004 goto skip_data; 2005 } 2006 } 2007 2008 if (put_len) { 2009 dma_sync_single_for_cpu(pdata->dev, 2010 rdata->rx.buf.dma, 2011 rdata->rx.buf.dma_len, 2012 DMA_FROM_DEVICE); 2013 2014 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 2015 rdata->rx.buf.pa.pages, 2016 rdata->rx.buf.pa.pages_offset, 2017 put_len, rdata->rx.buf.dma_len); 2018 rdata->rx.buf.pa.pages = NULL; 2019 } 2020 } 2021 2022skip_data: 2023 if (incomplete || context_next) 2024 goto read_again; 2025 2026 if (!skb) 2027 goto next_packet; 2028 2029 /* Be sure we don't exceed the configured MTU */ 2030 max_len = netdev->mtu + ETH_HLEN; 2031 if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 2032 (skb->protocol == htons(ETH_P_8021Q))) 2033 max_len += VLAN_HLEN; 2034 2035 if (skb->len > max_len) { 2036 DBGPR("packet length exceeds configured MTU\n"); 2037 dev_kfree_skb(skb); 2038 goto next_packet; 2039 } 2040 2041#ifdef XGMAC_ENABLE_RX_PKT_DUMP 2042 xgbe_print_pkt(netdev, skb, false); 2043#endif 2044 2045 skb_checksum_none_assert(skb); 2046 if (XGMAC_GET_BITS(packet->attributes, 2047 RX_PACKET_ATTRIBUTES, CSUM_DONE)) 2048 skb->ip_summed = CHECKSUM_UNNECESSARY; 2049 2050 if (XGMAC_GET_BITS(packet->attributes, 2051 RX_PACKET_ATTRIBUTES, VLAN_CTAG)) 2052 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2053 packet->vlan_ctag); 2054 2055 if (XGMAC_GET_BITS(packet->attributes, 2056 RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { 2057 u64 nsec; 2058 2059 nsec = timecounter_cyc2time(&pdata->tstamp_tc, 2060 packet->rx_tstamp); 2061 hwtstamps = skb_hwtstamps(skb); 2062 hwtstamps->hwtstamp = ns_to_ktime(nsec); 2063 } 2064 2065 if (XGMAC_GET_BITS(packet->attributes, 2066 RX_PACKET_ATTRIBUTES, RSS_HASH)) 2067 skb_set_hash(skb, packet->rss_hash, 2068 packet->rss_hash_type); 2069 2070 skb->dev = netdev; 2071 skb->protocol = eth_type_trans(skb, netdev); 2072 skb_record_rx_queue(skb, channel->queue_index); 2073 skb_mark_napi_id(skb, napi); 2074 2075 netdev->last_rx = jiffies; 2076 napi_gro_receive(napi, skb); 2077 2078next_packet: 2079 packet_count++; 2080 } 2081 2082 /* Check if we need to save state before leaving */ 2083 if (received && (incomplete || context_next)) { 2084 rdata = XGBE_GET_DESC_DATA(ring, ring->cur); 2085 rdata->state_saved = 1; 2086 rdata->state.incomplete = incomplete; 2087 rdata->state.context_next = context_next; 2088 rdata->state.skb = skb; 2089 rdata->state.len = len; 2090 rdata->state.error = error; 2091 } 2092 2093 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); 2094 2095 return packet_count; 2096} 2097 2098static int xgbe_one_poll(struct napi_struct *napi, int budget) 2099{ 2100 struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, 2101 napi); 2102 int processed = 0; 2103 2104 DBGPR("-->xgbe_one_poll: budget=%d\n", budget); 2105 2106 /* Cleanup Tx ring first */ 2107 xgbe_tx_poll(channel); 2108 2109 /* Process Rx ring next */ 2110 processed = xgbe_rx_poll(channel, budget); 2111 2112 /* If we processed everything, we are done */ 2113 if (processed < budget) { 2114 /* Turn off polling */ 2115 napi_complete(napi); 2116 2117 /* Enable Tx and Rx interrupts */ 2118 enable_irq(channel->dma_irq); 2119 } 2120 2121 DBGPR("<--xgbe_one_poll: received = %d\n", processed); 2122 2123 return processed; 2124} 2125 2126static int xgbe_all_poll(struct napi_struct *napi, int budget) 2127{ 2128 struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, 2129 napi); 2130 struct xgbe_channel *channel; 2131 int ring_budget; 2132 int processed, last_processed; 2133 unsigned int i; 2134 2135 DBGPR("-->xgbe_all_poll: budget=%d\n", budget); 2136 2137 processed = 0; 2138 ring_budget = budget / pdata->rx_ring_count; 2139 do { 2140 last_processed = processed; 2141 2142 channel = pdata->channel; 2143 for (i = 0; i < pdata->channel_count; i++, channel++) { 2144 /* Cleanup Tx ring first */ 2145 xgbe_tx_poll(channel); 2146 2147 /* Process Rx ring next */ 2148 if (ring_budget > (budget - processed)) 2149 ring_budget = budget - processed; 2150 processed += xgbe_rx_poll(channel, ring_budget); 2151 } 2152 } while ((processed < budget) && (processed != last_processed)); 2153 2154 /* If we processed everything, we are done */ 2155 if (processed < budget) { 2156 /* Turn off polling */ 2157 napi_complete(napi); 2158 2159 /* Enable Tx and Rx interrupts */ 2160 xgbe_enable_rx_tx_ints(pdata); 2161 } 2162 2163 DBGPR("<--xgbe_all_poll: received = %d\n", processed); 2164 2165 return processed; 2166} 2167 2168void xgbe_dump_tx_desc(struct xgbe_ring *ring, unsigned int idx, 2169 unsigned int count, unsigned int flag) 2170{ 2171 struct xgbe_ring_data *rdata; 2172 struct xgbe_ring_desc *rdesc; 2173 2174 while (count--) { 2175 rdata = XGBE_GET_DESC_DATA(ring, idx); 2176 rdesc = rdata->rdesc; 2177 pr_alert("TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, 2178 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", 2179 le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), 2180 le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); 2181 idx++; 2182 } 2183} 2184 2185void xgbe_dump_rx_desc(struct xgbe_ring *ring, struct xgbe_ring_desc *desc, 2186 unsigned int idx) 2187{ 2188 pr_alert("RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", idx, 2189 le32_to_cpu(desc->desc0), le32_to_cpu(desc->desc1), 2190 le32_to_cpu(desc->desc2), le32_to_cpu(desc->desc3)); 2191} 2192 2193void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) 2194{ 2195 struct ethhdr *eth = (struct ethhdr *)skb->data; 2196 unsigned char *buf = skb->data; 2197 unsigned char buffer[128]; 2198 unsigned int i, j; 2199 2200 netdev_alert(netdev, "\n************** SKB dump ****************\n"); 2201 2202 netdev_alert(netdev, "%s packet of %d bytes\n", 2203 (tx_rx ? "TX" : "RX"), skb->len); 2204 2205 netdev_alert(netdev, "Dst MAC addr: %pM\n", eth->h_dest); 2206 netdev_alert(netdev, "Src MAC addr: %pM\n", eth->h_source); 2207 netdev_alert(netdev, "Protocol: 0x%04hx\n", ntohs(eth->h_proto)); 2208 2209 for (i = 0, j = 0; i < skb->len;) { 2210 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", 2211 buf[i++]); 2212 2213 if ((i % 32) == 0) { 2214 netdev_alert(netdev, " 0x%04x: %s\n", i - 32, buffer); 2215 j = 0; 2216 } else if ((i % 16) == 0) { 2217 buffer[j++] = ' '; 2218 buffer[j++] = ' '; 2219 } else if ((i % 4) == 0) { 2220 buffer[j++] = ' '; 2221 } 2222 } 2223 if (i % 32) 2224 netdev_alert(netdev, " 0x%04x: %s\n", i - (i % 32), buffer); 2225 2226 netdev_alert(netdev, "\n************** SKB dump ****************\n"); 2227} 2228