1/* 2 * Broadcom BCM7xxx System Port Ethernet MAC driver 3 * 4 * Copyright (C) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#ifndef __BCM_SYSPORT_H 12#define __BCM_SYSPORT_H 13 14#include <linux/if_vlan.h> 15 16/* Receive/transmit descriptor format */ 17#define DESC_ADDR_HI_STATUS_LEN 0x00 18#define DESC_ADDR_HI_SHIFT 0 19#define DESC_ADDR_HI_MASK 0xff 20#define DESC_STATUS_SHIFT 8 21#define DESC_STATUS_MASK 0x3ff 22#define DESC_LEN_SHIFT 18 23#define DESC_LEN_MASK 0x7fff 24#define DESC_ADDR_LO 0x04 25 26/* HW supports 40-bit addressing hence the */ 27#define DESC_SIZE (WORDS_PER_DESC * sizeof(u32)) 28 29/* Default RX buffer allocation size */ 30#define RX_BUF_LENGTH 2048 31 32/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. 33 * 1536 is multiple of 256 bytes 34 */ 35#define ENET_BRCM_TAG_LEN 4 36#define ENET_PAD 10 37#define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 38 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 39 40/* Transmit status block */ 41struct bcm_tsb { 42 u32 pcp_dei_vid; 43#define PCP_DEI_MASK 0xf 44#define VID_SHIFT 4 45#define VID_MASK 0xfff 46 u32 l4_ptr_dest_map; 47#define L4_CSUM_PTR_MASK 0x1ff 48#define L4_PTR_SHIFT 9 49#define L4_PTR_MASK 0x1ff 50#define L4_UDP (1 << 18) 51#define L4_LENGTH_VALID (1 << 19) 52#define DEST_MAP_SHIFT 20 53#define DEST_MAP_MASK 0x1ff 54}; 55 56/* Receive status block uses the same 57 * definitions as the DMA descriptor 58 */ 59struct bcm_rsb { 60 u32 rx_status_len; 61 u32 brcm_egress_tag; 62}; 63 64/* Common Receive/Transmit status bits */ 65#define DESC_L4_CSUM (1 << 7) 66#define DESC_SOP (1 << 8) 67#define DESC_EOP (1 << 9) 68 69/* Receive Status bits */ 70#define RX_STATUS_UCAST 0 71#define RX_STATUS_BCAST 0x04 72#define RX_STATUS_MCAST 0x08 73#define RX_STATUS_L2_MCAST 0x0c 74#define RX_STATUS_ERR (1 << 4) 75#define RX_STATUS_OVFLOW (1 << 5) 76#define RX_STATUS_PARSE_FAIL (1 << 6) 77 78/* Transmit Status bits */ 79#define TX_STATUS_VLAN_NO_ACT 0x00 80#define TX_STATUS_VLAN_PCP_TSB 0x01 81#define TX_STATUS_VLAN_QUEUE 0x02 82#define TX_STATUS_VLAN_VID_TSB 0x03 83#define TX_STATUS_OWR_CRC (1 << 2) 84#define TX_STATUS_APP_CRC (1 << 3) 85#define TX_STATUS_BRCM_TAG_NO_ACT 0 86#define TX_STATUS_BRCM_TAG_ZERO 0x10 87#define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 88#define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 89#define TX_STATUS_SKIP_BYTES (1 << 6) 90 91/* Specific register definitions */ 92#define SYS_PORT_TOPCTRL_OFFSET 0 93#define REV_CNTL 0x00 94#define REV_MASK 0xffff 95 96#define RX_FLUSH_CNTL 0x04 97#define RX_FLUSH (1 << 0) 98 99#define TX_FLUSH_CNTL 0x08 100#define TX_FLUSH (1 << 0) 101 102#define MISC_CNTL 0x0c 103#define SYS_CLK_SEL (1 << 0) 104#define TDMA_EOP_SEL (1 << 1) 105 106/* Level-2 Interrupt controller offsets and defines */ 107#define SYS_PORT_INTRL2_0_OFFSET 0x200 108#define SYS_PORT_INTRL2_1_OFFSET 0x240 109#define INTRL2_CPU_STATUS 0x00 110#define INTRL2_CPU_SET 0x04 111#define INTRL2_CPU_CLEAR 0x08 112#define INTRL2_CPU_MASK_STATUS 0x0c 113#define INTRL2_CPU_MASK_SET 0x10 114#define INTRL2_CPU_MASK_CLEAR 0x14 115 116/* Level-2 instance 0 interrupt bits */ 117#define INTRL2_0_GISB_ERR (1 << 0) 118#define INTRL2_0_RBUF_OVFLOW (1 << 1) 119#define INTRL2_0_TBUF_UNDFLOW (1 << 2) 120#define INTRL2_0_MPD (1 << 3) 121#define INTRL2_0_BRCM_MATCH_TAG (1 << 4) 122#define INTRL2_0_RDMA_MBDONE (1 << 5) 123#define INTRL2_0_OVER_MAX_THRESH (1 << 6) 124#define INTRL2_0_BELOW_HYST_THRESH (1 << 7) 125#define INTRL2_0_FREE_LIST_EMPTY (1 << 8) 126#define INTRL2_0_TX_RING_FULL (1 << 9) 127#define INTRL2_0_DESC_ALLOC_ERR (1 << 10) 128#define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11) 129 130/* RXCHK offset and defines */ 131#define SYS_PORT_RXCHK_OFFSET 0x300 132 133#define RXCHK_CONTROL 0x00 134#define RXCHK_EN (1 << 0) 135#define RXCHK_SKIP_FCS (1 << 1) 136#define RXCHK_BAD_CSUM_DIS (1 << 2) 137#define RXCHK_BRCM_TAG_EN (1 << 3) 138#define RXCHK_BRCM_TAG_MATCH_SHIFT 4 139#define RXCHK_BRCM_TAG_MATCH_MASK 0xff 140#define RXCHK_PARSE_TNL (1 << 12) 141#define RXCHK_VIOL_EN (1 << 13) 142#define RXCHK_VIOL_DIS (1 << 14) 143#define RXCHK_INCOM_PKT (1 << 15) 144#define RXCHK_V6_DUPEXT_EN (1 << 16) 145#define RXCHK_V6_DUPEXT_DIS (1 << 17) 146#define RXCHK_ETHERTYPE_DIS (1 << 18) 147#define RXCHK_L2_HDR_DIS (1 << 19) 148#define RXCHK_L3_HDR_DIS (1 << 20) 149#define RXCHK_MAC_RX_ERR_DIS (1 << 21) 150#define RXCHK_PARSE_AUTH (1 << 22) 151 152#define RXCHK_BRCM_TAG0 0x04 153#define RXCHK_BRCM_TAG(i) ((i) * RXCHK_BRCM_TAG0) 154#define RXCHK_BRCM_TAG0_MASK 0x24 155#define RXCHK_BRCM_TAG_MASK(i) ((i) * RXCHK_BRCM_TAG0_MASK) 156#define RXCHK_BRCM_TAG_MATCH_STATUS 0x44 157#define RXCHK_ETHERTYPE 0x48 158#define RXCHK_BAD_CSUM_CNTR 0x4C 159#define RXCHK_OTHER_DISC_CNTR 0x50 160 161/* TXCHCK offsets and defines */ 162#define SYS_PORT_TXCHK_OFFSET 0x380 163#define TXCHK_PKT_RDY_THRESH 0x00 164 165/* Receive buffer offset and defines */ 166#define SYS_PORT_RBUF_OFFSET 0x400 167 168#define RBUF_CONTROL 0x00 169#define RBUF_RSB_EN (1 << 0) 170#define RBUF_4B_ALGN (1 << 1) 171#define RBUF_BRCM_TAG_STRIP (1 << 2) 172#define RBUF_BAD_PKT_DISC (1 << 3) 173#define RBUF_RESUME_THRESH_SHIFT 4 174#define RBUF_RESUME_THRESH_MASK 0xff 175#define RBUF_OK_TO_SEND_SHIFT 12 176#define RBUF_OK_TO_SEND_MASK 0xff 177#define RBUF_CRC_REPLACE (1 << 20) 178#define RBUF_OK_TO_SEND_MODE (1 << 21) 179#define RBUF_RSB_SWAP (1 << 22) 180#define RBUF_ACPI_EN (1 << 23) 181 182#define RBUF_PKT_RDY_THRESH 0x04 183 184#define RBUF_STATUS 0x08 185#define RBUF_WOL_MODE (1 << 0) 186#define RBUF_MPD (1 << 1) 187#define RBUF_ACPI (1 << 2) 188 189#define RBUF_OVFL_DISC_CNTR 0x0c 190#define RBUF_ERR_PKT_CNTR 0x10 191 192/* Transmit buffer offset and defines */ 193#define SYS_PORT_TBUF_OFFSET 0x600 194 195#define TBUF_CONTROL 0x00 196#define TBUF_BP_EN (1 << 0) 197#define TBUF_MAX_PKT_THRESH_SHIFT 1 198#define TBUF_MAX_PKT_THRESH_MASK 0x1f 199#define TBUF_FULL_THRESH_SHIFT 8 200#define TBUF_FULL_THRESH_MASK 0x1f 201 202/* UniMAC offset and defines */ 203#define SYS_PORT_UMAC_OFFSET 0x800 204 205#define UMAC_CMD 0x008 206#define CMD_TX_EN (1 << 0) 207#define CMD_RX_EN (1 << 1) 208#define CMD_SPEED_SHIFT 2 209#define CMD_SPEED_10 0 210#define CMD_SPEED_100 1 211#define CMD_SPEED_1000 2 212#define CMD_SPEED_2500 3 213#define CMD_SPEED_MASK 3 214#define CMD_PROMISC (1 << 4) 215#define CMD_PAD_EN (1 << 5) 216#define CMD_CRC_FWD (1 << 6) 217#define CMD_PAUSE_FWD (1 << 7) 218#define CMD_RX_PAUSE_IGNORE (1 << 8) 219#define CMD_TX_ADDR_INS (1 << 9) 220#define CMD_HD_EN (1 << 10) 221#define CMD_SW_RESET (1 << 13) 222#define CMD_LCL_LOOP_EN (1 << 15) 223#define CMD_AUTO_CONFIG (1 << 22) 224#define CMD_CNTL_FRM_EN (1 << 23) 225#define CMD_NO_LEN_CHK (1 << 24) 226#define CMD_RMT_LOOP_EN (1 << 25) 227#define CMD_PRBL_EN (1 << 27) 228#define CMD_TX_PAUSE_IGNORE (1 << 28) 229#define CMD_TX_RX_EN (1 << 29) 230#define CMD_RUNT_FILTER_DIS (1 << 30) 231 232#define UMAC_MAC0 0x00c 233#define UMAC_MAC1 0x010 234#define UMAC_MAX_FRAME_LEN 0x014 235 236#define UMAC_TX_FLUSH 0x334 237 238#define UMAC_MIB_START 0x400 239 240/* There is a 0xC gap between the end of RX and beginning of TX stats and then 241 * between the end of TX stats and the beginning of the RX RUNT 242 */ 243#define UMAC_MIB_STAT_OFFSET 0xc 244 245#define UMAC_MIB_CTRL 0x580 246#define MIB_RX_CNT_RST (1 << 0) 247#define MIB_RUNT_CNT_RST (1 << 1) 248#define MIB_TX_CNT_RST (1 << 2) 249 250#define UMAC_MPD_CTRL 0x620 251#define MPD_EN (1 << 0) 252#define MSEQ_LEN_SHIFT 16 253#define MSEQ_LEN_MASK 0xff 254#define PSW_EN (1 << 27) 255 256#define UMAC_PSW_MS 0x624 257#define UMAC_PSW_LS 0x628 258#define UMAC_MDF_CTRL 0x650 259#define UMAC_MDF_ADDR 0x654 260 261/* Receive DMA offset and defines */ 262#define SYS_PORT_RDMA_OFFSET 0x2000 263 264#define RDMA_CONTROL 0x1000 265#define RDMA_EN (1 << 0) 266#define RDMA_RING_CFG (1 << 1) 267#define RDMA_DISC_EN (1 << 2) 268#define RDMA_BUF_DATA_OFFSET_SHIFT 4 269#define RDMA_BUF_DATA_OFFSET_MASK 0x3ff 270 271#define RDMA_STATUS 0x1004 272#define RDMA_DISABLED (1 << 0) 273#define RDMA_DESC_RAM_INIT_BUSY (1 << 1) 274#define RDMA_BP_STATUS (1 << 2) 275 276#define RDMA_SCB_BURST_SIZE 0x1008 277 278#define RDMA_RING_BUF_SIZE 0x100c 279#define RDMA_RING_SIZE_SHIFT 16 280 281#define RDMA_WRITE_PTR_HI 0x1010 282#define RDMA_WRITE_PTR_LO 0x1014 283#define RDMA_PROD_INDEX 0x1018 284#define RDMA_PROD_INDEX_MASK 0xffff 285 286#define RDMA_CONS_INDEX 0x101c 287#define RDMA_CONS_INDEX_MASK 0xffff 288 289#define RDMA_START_ADDR_HI 0x1020 290#define RDMA_START_ADDR_LO 0x1024 291#define RDMA_END_ADDR_HI 0x1028 292#define RDMA_END_ADDR_LO 0x102c 293 294#define RDMA_MBDONE_INTR 0x1030 295#define RDMA_INTR_THRESH_MASK 0xff 296#define RDMA_TIMEOUT_SHIFT 16 297#define RDMA_TIMEOUT_MASK 0xffff 298 299#define RDMA_XON_XOFF_THRESH 0x1034 300#define RDMA_XON_XOFF_THRESH_MASK 0xffff 301#define RDMA_XOFF_THRESH_SHIFT 16 302 303#define RDMA_READ_PTR_HI 0x1038 304#define RDMA_READ_PTR_LO 0x103c 305 306#define RDMA_OVERRIDE 0x1040 307#define RDMA_LE_MODE (1 << 0) 308#define RDMA_REG_MODE (1 << 1) 309 310#define RDMA_TEST 0x1044 311#define RDMA_TP_OUT_SEL (1 << 0) 312#define RDMA_MEM_SEL (1 << 1) 313 314#define RDMA_DEBUG 0x1048 315 316/* Transmit DMA offset and defines */ 317#define TDMA_NUM_RINGS 32 /* rings = queues */ 318#define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */ 319 320#define SYS_PORT_TDMA_OFFSET 0x4000 321#define TDMA_WRITE_PORT_OFFSET 0x0000 322#define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \ 323 (i) * TDMA_PORT_SIZE) 324#define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \ 325 sizeof(u32) + (i) * TDMA_PORT_SIZE) 326 327#define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \ 328 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 329#define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \ 330 (i) * TDMA_PORT_SIZE) 331#define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \ 332 sizeof(u32) + (i) * TDMA_PORT_SIZE) 333 334#define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \ 335 (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) 336#define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \ 337 (i) * sizeof(u32)) 338 339#define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \ 340 (TDMA_NUM_RINGS * sizeof(u32))) 341 342/* Register offsets and defines relatives to a specific ring number */ 343#define RING_HEAD_TAIL_PTR 0x00 344#define RING_HEAD_MASK 0x7ff 345#define RING_TAIL_SHIFT 11 346#define RING_TAIL_MASK 0x7ff 347#define RING_FLUSH (1 << 24) 348#define RING_EN (1 << 25) 349 350#define RING_COUNT 0x04 351#define RING_COUNT_MASK 0x7ff 352#define RING_BUFF_DONE_SHIFT 11 353#define RING_BUFF_DONE_MASK 0x7ff 354 355#define RING_MAX_HYST 0x08 356#define RING_MAX_THRESH_MASK 0x7ff 357#define RING_HYST_THRESH_SHIFT 11 358#define RING_HYST_THRESH_MASK 0x7ff 359 360#define RING_INTR_CONTROL 0x0c 361#define RING_INTR_THRESH_MASK 0x7ff 362#define RING_EMPTY_INTR_EN (1 << 15) 363#define RING_TIMEOUT_SHIFT 16 364#define RING_TIMEOUT_MASK 0xffff 365 366#define RING_PROD_CONS_INDEX 0x10 367#define RING_PROD_INDEX_MASK 0xffff 368#define RING_CONS_INDEX_SHIFT 16 369#define RING_CONS_INDEX_MASK 0xffff 370 371#define RING_MAPPING 0x14 372#define RING_QID_MASK 0x3 373#define RING_PORT_ID_SHIFT 3 374#define RING_PORT_ID_MASK 0x7 375#define RING_IGNORE_STATUS (1 << 6) 376#define RING_FAILOVER_EN (1 << 7) 377#define RING_CREDIT_SHIFT 8 378#define RING_CREDIT_MASK 0xffff 379 380#define RING_PCP_DEI_VID 0x18 381#define RING_VID_MASK 0x7ff 382#define RING_DEI (1 << 12) 383#define RING_PCP_SHIFT 13 384#define RING_PCP_MASK 0x7 385#define RING_PKT_SIZE_ADJ_SHIFT 16 386#define RING_PKT_SIZE_ADJ_MASK 0xf 387 388#define TDMA_DESC_RING_SIZE 28 389 390/* Defininition for a given TX ring base address */ 391#define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ 392 ((i) * TDMA_DESC_RING_SIZE)) 393 394/* Ring indexed register addreses */ 395#define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \ 396 RING_HEAD_TAIL_PTR) 397#define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ 398 RING_COUNT) 399#define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ 400 RING_MAX_HYST) 401#define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \ 402 RING_INTR_CONTROL) 403#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ 404 (TDMA_DESC_RING_BASE(i) + \ 405 RING_PROD_CONS_INDEX) 406#define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \ 407 RING_MAPPING) 408#define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \ 409 RING_PCP_DEI_VID) 410 411#define TDMA_CONTROL 0x600 412#define TDMA_EN (1 << 0) 413#define TSB_EN (1 << 1) 414#define TSB_SWAP (1 << 2) 415#define ACB_ALGO (1 << 3) 416#define BUF_DATA_OFFSET_SHIFT 4 417#define BUF_DATA_OFFSET_MASK 0x3ff 418#define VLAN_EN (1 << 14) 419#define SW_BRCM_TAG (1 << 15) 420#define WNC_KPT_SIZE_UPDATE (1 << 16) 421#define SYNC_PKT_SIZE (1 << 17) 422#define ACH_TXDONE_DELAY_SHIFT 18 423#define ACH_TXDONE_DELAY_MASK 0xff 424 425#define TDMA_STATUS 0x604 426#define TDMA_DISABLED (1 << 0) 427#define TDMA_LL_RAM_INIT_BUSY (1 << 1) 428 429#define TDMA_SCB_BURST_SIZE 0x608 430#define TDMA_OVER_MAX_THRESH_STATUS 0x60c 431#define TDMA_OVER_HYST_THRESH_STATUS 0x610 432#define TDMA_TPID 0x614 433 434#define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618 435#define TDMA_FREE_HEAD_MASK 0x7ff 436#define TDMA_FREE_TAIL_SHIFT 11 437#define TDMA_FREE_TAIL_MASK 0x7ff 438 439#define TDMA_FREE_LIST_COUNT 0x61c 440#define TDMA_FREE_LIST_COUNT_MASK 0x7ff 441 442#define TDMA_TIER2_ARB_CTRL 0x620 443#define TDMA_ARB_MODE_RR 0 444#define TDMA_ARB_MODE_WEIGHT_RR 0x1 445#define TDMA_ARB_MODE_STRICT 0x2 446#define TDMA_ARB_MODE_DEFICIT_RR 0x3 447#define TDMA_CREDIT_SHIFT 4 448#define TDMA_CREDIT_MASK 0xffff 449 450#define TDMA_TIER1_ARB_0_CTRL 0x624 451#define TDMA_ARB_EN (1 << 0) 452 453#define TDMA_TIER1_ARB_0_QUEUE_EN 0x628 454#define TDMA_TIER1_ARB_1_CTRL 0x62c 455#define TDMA_TIER1_ARB_1_QUEUE_EN 0x630 456#define TDMA_TIER1_ARB_2_CTRL 0x634 457#define TDMA_TIER1_ARB_2_QUEUE_EN 0x638 458#define TDMA_TIER1_ARB_3_CTRL 0x63c 459#define TDMA_TIER1_ARB_3_QUEUE_EN 0x640 460 461#define TDMA_SCB_ENDIAN_OVERRIDE 0x644 462#define TDMA_LE_MODE (1 << 0) 463#define TDMA_REG_MODE (1 << 1) 464 465#define TDMA_TEST 0x648 466#define TDMA_TP_OUT_SEL (1 << 0) 467#define TDMA_MEM_TM (1 << 1) 468 469#define TDMA_DEBUG 0x64c 470 471/* Transmit/Receive descriptor */ 472struct dma_desc { 473 u32 addr_status_len; 474 u32 addr_lo; 475}; 476 477/* Number of Receive hardware descriptor words */ 478#define NUM_HW_RX_DESC_WORDS 1024 479/* Real number of usable descriptors */ 480#define NUM_RX_DESC (NUM_HW_RX_DESC_WORDS / WORDS_PER_DESC) 481 482/* Internal linked-list RAM has up to 1536 entries */ 483#define NUM_TX_DESC 1536 484 485#define WORDS_PER_DESC (sizeof(struct dma_desc) / sizeof(u32)) 486 487/* Rx/Tx common counter group.*/ 488struct bcm_sysport_pkt_counters { 489 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 490 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 491 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 492 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 493 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 494 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 495 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 496 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 497 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 498 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 499}; 500 501/* RSV, Receive Status Vector */ 502struct bcm_sysport_rx_counters { 503 struct bcm_sysport_pkt_counters pkt_cnt; 504 u32 pkt; /* RO (0x428) Received pkt count*/ 505 u32 bytes; /* RO Received byte count */ 506 u32 mca; /* RO # of Received multicast pkt */ 507 u32 bca; /* RO # of Receive broadcast pkt */ 508 u32 fcs; /* RO # of Received FCS error */ 509 u32 cf; /* RO # of Received control frame pkt*/ 510 u32 pf; /* RO # of Received pause frame pkt */ 511 u32 uo; /* RO # of unknown op code pkt */ 512 u32 aln; /* RO # of alignment error count */ 513 u32 flr; /* RO # of frame length out of range count */ 514 u32 cde; /* RO # of code error pkt */ 515 u32 fcr; /* RO # of carrier sense error pkt */ 516 u32 ovr; /* RO # of oversize pkt*/ 517 u32 jbr; /* RO # of jabber count */ 518 u32 mtue; /* RO # of MTU error pkt*/ 519 u32 pok; /* RO # of Received good pkt */ 520 u32 uc; /* RO # of unicast pkt */ 521 u32 ppp; /* RO # of PPP pkt */ 522 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 523}; 524 525/* TSV, Transmit Status Vector */ 526struct bcm_sysport_tx_counters { 527 struct bcm_sysport_pkt_counters pkt_cnt; 528 u32 pkts; /* RO (0x4a8) Transmited pkt */ 529 u32 mca; /* RO # of xmited multicast pkt */ 530 u32 bca; /* RO # of xmited broadcast pkt */ 531 u32 pf; /* RO # of xmited pause frame count */ 532 u32 cf; /* RO # of xmited control frame count */ 533 u32 fcs; /* RO # of xmited FCS error count */ 534 u32 ovr; /* RO # of xmited oversize pkt */ 535 u32 drf; /* RO # of xmited deferral pkt */ 536 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 537 u32 scl; /* RO # of xmited single collision pkt */ 538 u32 mcl; /* RO # of xmited multiple collision pkt*/ 539 u32 lcl; /* RO # of xmited late collision pkt */ 540 u32 ecl; /* RO # of xmited excessive collision pkt*/ 541 u32 frg; /* RO # of xmited fragments pkt*/ 542 u32 ncl; /* RO # of xmited total collision count */ 543 u32 jbr; /* RO # of xmited jabber count*/ 544 u32 bytes; /* RO # of xmited byte count */ 545 u32 pok; /* RO # of xmited good pkt */ 546 u32 uc; /* RO (0x4f0) # of xmited unicast pkt */ 547}; 548 549struct bcm_sysport_mib { 550 struct bcm_sysport_rx_counters rx; 551 struct bcm_sysport_tx_counters tx; 552 u32 rx_runt_cnt; 553 u32 rx_runt_fcs; 554 u32 rx_runt_fcs_align; 555 u32 rx_runt_bytes; 556 u32 rxchk_bad_csum; 557 u32 rxchk_other_pkt_disc; 558 u32 rbuf_ovflow_cnt; 559 u32 rbuf_err_cnt; 560 u32 alloc_rx_buff_failed; 561 u32 rx_dma_failed; 562 u32 tx_dma_failed; 563}; 564 565/* HW maintains a large list of counters */ 566enum bcm_sysport_stat_type { 567 BCM_SYSPORT_STAT_NETDEV = -1, 568 BCM_SYSPORT_STAT_MIB_RX, 569 BCM_SYSPORT_STAT_MIB_TX, 570 BCM_SYSPORT_STAT_RUNT, 571 BCM_SYSPORT_STAT_RXCHK, 572 BCM_SYSPORT_STAT_RBUF, 573 BCM_SYSPORT_STAT_SOFT, 574}; 575 576/* Macros to help define ethtool statistics */ 577#define STAT_NETDEV(m) { \ 578 .stat_string = __stringify(m), \ 579 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 580 .stat_offset = offsetof(struct net_device_stats, m), \ 581 .type = BCM_SYSPORT_STAT_NETDEV, \ 582} 583 584#define STAT_MIB(str, m, _type) { \ 585 .stat_string = str, \ 586 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 587 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 588 .type = _type, \ 589} 590 591#define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX) 592#define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX) 593#define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT) 594#define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT) 595 596#define STAT_RXCHK(str, m, ofs) { \ 597 .stat_string = str, \ 598 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 599 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 600 .type = BCM_SYSPORT_STAT_RXCHK, \ 601 .reg_offset = ofs, \ 602} 603 604#define STAT_RBUF(str, m, ofs) { \ 605 .stat_string = str, \ 606 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ 607 .stat_offset = offsetof(struct bcm_sysport_priv, m), \ 608 .type = BCM_SYSPORT_STAT_RBUF, \ 609 .reg_offset = ofs, \ 610} 611 612struct bcm_sysport_stats { 613 char stat_string[ETH_GSTRING_LEN]; 614 int stat_sizeof; 615 int stat_offset; 616 enum bcm_sysport_stat_type type; 617 /* reg offset from UMAC base for misc counters */ 618 u16 reg_offset; 619}; 620 621/* Software house keeping helper structure */ 622struct bcm_sysport_cb { 623 struct sk_buff *skb; /* SKB for RX packets */ 624 void __iomem *bd_addr; /* Buffer descriptor PHYS addr */ 625 626 DEFINE_DMA_UNMAP_ADDR(dma_addr); 627 DEFINE_DMA_UNMAP_LEN(dma_len); 628}; 629 630/* Software view of the TX ring */ 631struct bcm_sysport_tx_ring { 632 spinlock_t lock; /* Ring lock for tx reclaim/xmit */ 633 struct napi_struct napi; /* NAPI per tx queue */ 634 dma_addr_t desc_dma; /* DMA cookie */ 635 unsigned int index; /* Ring index */ 636 unsigned int size; /* Ring current size */ 637 unsigned int alloc_size; /* Ring one-time allocated size */ 638 unsigned int desc_count; /* Number of descriptors */ 639 unsigned int curr_desc; /* Current descriptor */ 640 unsigned int c_index; /* Last consumer index */ 641 unsigned int p_index; /* Current producer index */ 642 struct bcm_sysport_cb *cbs; /* Transmit control blocks */ 643 struct dma_desc *desc_cpu; /* CPU view of the descriptor */ 644 struct bcm_sysport_priv *priv; /* private context backpointer */ 645}; 646 647/* Driver private structure */ 648struct bcm_sysport_priv { 649 void __iomem *base; 650 u32 irq0_stat; 651 u32 irq0_mask; 652 u32 irq1_stat; 653 u32 irq1_mask; 654 struct napi_struct napi ____cacheline_aligned; 655 struct net_device *netdev; 656 struct platform_device *pdev; 657 int irq0; 658 int irq1; 659 int wol_irq; 660 661 /* Transmit rings */ 662 struct bcm_sysport_tx_ring tx_rings[TDMA_NUM_RINGS]; 663 664 /* Receive queue */ 665 void __iomem *rx_bds; 666 void __iomem *rx_bd_assign_ptr; 667 unsigned int rx_bd_assign_index; 668 struct bcm_sysport_cb *rx_cbs; 669 unsigned int num_rx_bds; 670 unsigned int rx_read_ptr; 671 unsigned int rx_c_index; 672 673 /* PHY device */ 674 struct device_node *phy_dn; 675 struct phy_device *phydev; 676 phy_interface_t phy_interface; 677 int old_pause; 678 int old_link; 679 int old_duplex; 680 681 /* Misc fields */ 682 unsigned int rx_chk_en:1; 683 unsigned int tsb_en:1; 684 unsigned int crc_fwd:1; 685 u16 rev; 686 u32 wolopts; 687 unsigned int wol_irq_disabled:1; 688 689 /* MIB related fields */ 690 struct bcm_sysport_mib mib; 691 692 /* Ethtool */ 693 u32 msg_enable; 694}; 695#endif /* __BCM_SYSPORT_H */ 696