1/*****************************************************************************
2 *                                                                           *
3 * File: pm3393.c                                                            *
4 * $Revision: 1.16 $                                                         *
5 * $Date: 2005/05/14 00:59:32 $                                              *
6 * Description:                                                              *
7 *  PMC/SIERRA (pm3393) MAC-PHY functionality.                               *
8 *  part of the Chelsio 10Gb Ethernet Driver.                                *
9 *                                                                           *
10 * This program is free software; you can redistribute it and/or modify      *
11 * it under the terms of the GNU General Public License, version 2, as       *
12 * published by the Free Software Foundation.                                *
13 *                                                                           *
14 * You should have received a copy of the GNU General Public License along   *
15 * with this program; if not, see <http://www.gnu.org/licenses/>.            *
16 *                                                                           *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
18 * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
20 *                                                                           *
21 * http://www.chelsio.com                                                    *
22 *                                                                           *
23 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
24 * All rights reserved.                                                      *
25 *                                                                           *
26 * Maintainers: maintainers@chelsio.com                                      *
27 *                                                                           *
28 * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
29 *          Tina Yang               <tainay@chelsio.com>                     *
30 *          Felix Marti             <felix@chelsio.com>                      *
31 *          Scott Bardone           <sbardone@chelsio.com>                   *
32 *          Kurt Ottaway            <kottaway@chelsio.com>                   *
33 *          Frank DiMambro          <frank@chelsio.com>                      *
34 *                                                                           *
35 * History:                                                                  *
36 *                                                                           *
37 ****************************************************************************/
38
39#include "common.h"
40#include "regs.h"
41#include "gmac.h"
42#include "elmer0.h"
43#include "suni1x10gexp_regs.h"
44
45#include <linux/crc32.h>
46#include <linux/slab.h>
47
48#define OFFSET(REG_ADDR)    ((REG_ADDR) << 2)
49
50/* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
51#define MAX_FRAME_SIZE  9600
52
53#define IPG 12
54#define TXXG_CONF1_VAL ((IPG << SUNI1x10GEXP_BITOFF_TXXG_IPGT) | \
55	SUNI1x10GEXP_BITMSK_TXXG_32BIT_ALIGN | SUNI1x10GEXP_BITMSK_TXXG_CRCEN | \
56	SUNI1x10GEXP_BITMSK_TXXG_PADEN)
57#define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
58	SUNI1x10GEXP_BITMSK_RXXG_FLCHK | SUNI1x10GEXP_BITMSK_RXXG_CRC_STRIP)
59
60/* Update statistics every 15 minutes */
61#define STATS_TICK_SECS (15 * 60)
62
63enum {                     /* RMON registers */
64	RxOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_1_LOW,
65	RxUnicastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_4_LOW,
66	RxMulticastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_5_LOW,
67	RxBroadcastFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_6_LOW,
68	RxPAUSEMACCtrlFramesReceived = SUNI1x10GEXP_REG_MSTAT_COUNTER_8_LOW,
69	RxFrameCheckSequenceErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_10_LOW,
70	RxFramesLostDueToInternalMACErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_11_LOW,
71	RxSymbolErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_12_LOW,
72	RxInRangeLengthErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_13_LOW,
73	RxFramesTooLongErrors = SUNI1x10GEXP_REG_MSTAT_COUNTER_15_LOW,
74	RxJabbers = SUNI1x10GEXP_REG_MSTAT_COUNTER_16_LOW,
75	RxFragments = SUNI1x10GEXP_REG_MSTAT_COUNTER_17_LOW,
76	RxUndersizedFrames =  SUNI1x10GEXP_REG_MSTAT_COUNTER_18_LOW,
77	RxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_25_LOW,
78	RxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_26_LOW,
79
80	TxOctetsTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_33_LOW,
81	TxFramesLostDueToInternalMACTransmissionError = SUNI1x10GEXP_REG_MSTAT_COUNTER_35_LOW,
82	TxTransmitSystemError = SUNI1x10GEXP_REG_MSTAT_COUNTER_36_LOW,
83	TxUnicastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_38_LOW,
84	TxMulticastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_40_LOW,
85	TxBroadcastFramesTransmittedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_42_LOW,
86	TxPAUSEMACCtrlFramesTransmitted = SUNI1x10GEXP_REG_MSTAT_COUNTER_43_LOW,
87	TxJumboFramesReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_51_LOW,
88	TxJumboOctetsReceivedOK = SUNI1x10GEXP_REG_MSTAT_COUNTER_52_LOW
89};
90
91struct _cmac_instance {
92	u8 enabled;
93	u8 fc;
94	u8 mac_addr[6];
95};
96
97static int pmread(struct cmac *cmac, u32 reg, u32 * data32)
98{
99	t1_tpi_read(cmac->adapter, OFFSET(reg), data32);
100	return 0;
101}
102
103static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)
104{
105	t1_tpi_write(cmac->adapter, OFFSET(reg), data32);
106	return 0;
107}
108
109/* Port reset. */
110static int pm3393_reset(struct cmac *cmac)
111{
112	return 0;
113}
114
115/*
116 * Enable interrupts for the PM3393
117 *
118 *	1. Enable PM3393 BLOCK interrupts.
119 *	2. Enable PM3393 Master Interrupt bit(INTE)
120 *	3. Enable ELMER's PM3393 bit.
121 *	4. Enable Terminator external interrupt.
122 */
123static int pm3393_interrupt_enable(struct cmac *cmac)
124{
125	u32 pl_intr;
126
127	/* PM3393 - Enabling all hardware block interrupts.
128	 */
129	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);
130	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);
131	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);
132	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);
133
134	/* Don't interrupt on statistics overflow, we are polling */
135	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
136	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
137	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
138	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
139
140	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);
141	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);
142	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);
143	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);
144	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);
145	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);
146	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);
147	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);
148	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);
149
150	/* PM3393 - Global interrupt enable
151	 */
152	/* TBD XXX Disable for now until we figure out why error interrupts keep asserting. */
153	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,
154		0 /*SUNI1x10GEXP_BITMSK_TOP_INTE */ );
155
156	/* TERMINATOR - PL_INTERUPTS_EXT */
157	pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);
158	pl_intr |= F_PL_INTR_EXT;
159	writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);
160	return 0;
161}
162
163static int pm3393_interrupt_disable(struct cmac *cmac)
164{
165	u32 elmer;
166
167	/* PM3393 - Enabling HW interrupt blocks. */
168	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);
169	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);
170	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);
171	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);
172	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);
173	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);
174	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);
175	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);
176	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);
177	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);
178	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);
179	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);
180	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);
181	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);
182	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);
183	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);
184	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);
185
186	/* PM3393 - Global interrupt enable */
187	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);
188
189	/* ELMER - External chip interrupts. */
190	t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);
191	elmer &= ~ELMER0_GP_BIT1;
192	t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);
193
194	/* TERMINATOR - PL_INTERUPTS_EXT */
195	/* DO NOT DISABLE TERMINATOR's EXTERNAL INTERRUPTS. ANOTHER CHIP
196	 * COULD WANT THEM ENABLED. We disable PM3393 at the ELMER level.
197	 */
198
199	return 0;
200}
201
202static int pm3393_interrupt_clear(struct cmac *cmac)
203{
204	u32 elmer;
205	u32 pl_intr;
206	u32 val32;
207
208	/* PM3393 - Clearing HW interrupt blocks. Note, this assumes
209	 *          bit WCIMODE=0 for a clear-on-read.
210	 */
211	pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);
212	pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);
213	pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);
214	pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);
215	pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);
216	pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);
217	pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);
218	pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);
219	pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);
220	pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);
221	pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);
222	pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,
223	       &val32);
224	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);
225	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);
226
227	/* PM3393 - Global interrupt status
228	 */
229	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);
230
231	/* ELMER - External chip interrupts.
232	 */
233	t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);
234	elmer |= ELMER0_GP_BIT1;
235	t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);
236
237	/* TERMINATOR - PL_INTERUPTS_EXT
238	 */
239	pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);
240	pl_intr |= F_PL_INTR_EXT;
241	writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);
242
243	return 0;
244}
245
246/* Interrupt handler */
247static int pm3393_interrupt_handler(struct cmac *cmac)
248{
249	u32 master_intr_status;
250
251	/* Read the master interrupt status register. */
252	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,
253	       &master_intr_status);
254	if (netif_msg_intr(cmac->adapter))
255		dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",
256			master_intr_status);
257
258	/* TBD XXX Lets just clear everything for now */
259	pm3393_interrupt_clear(cmac);
260
261	return 0;
262}
263
264static int pm3393_enable(struct cmac *cmac, int which)
265{
266	if (which & MAC_DIRECTION_RX)
267		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,
268			(RXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_RXXG_RXEN));
269
270	if (which & MAC_DIRECTION_TX) {
271		u32 val = TXXG_CONF1_VAL | SUNI1x10GEXP_BITMSK_TXXG_TXEN0;
272
273		if (cmac->instance->fc & PAUSE_RX)
274			val |= SUNI1x10GEXP_BITMSK_TXXG_FCRX;
275		if (cmac->instance->fc & PAUSE_TX)
276			val |= SUNI1x10GEXP_BITMSK_TXXG_FCTX;
277		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);
278	}
279
280	cmac->instance->enabled |= which;
281	return 0;
282}
283
284static int pm3393_enable_port(struct cmac *cmac, int which)
285{
286	/* Clear port statistics */
287	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
288		SUNI1x10GEXP_BITMSK_MSTAT_CLEAR);
289	udelay(2);
290	memset(&cmac->stats, 0, sizeof(struct cmac_statistics));
291
292	pm3393_enable(cmac, which);
293
294	/*
295	 * XXX This should be done by the PHY and preferably not at all.
296	 * The PHY doesn't give us link status indication on its own so have
297	 * the link management code query it instead.
298	 */
299	t1_link_changed(cmac->adapter, 0);
300	return 0;
301}
302
303static int pm3393_disable(struct cmac *cmac, int which)
304{
305	if (which & MAC_DIRECTION_RX)
306		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);
307	if (which & MAC_DIRECTION_TX)
308		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);
309
310	/*
311	 * The disable is graceful. Give the PM3393 time.  Can't wait very
312	 * long here, we may be holding locks.
313	 */
314	udelay(20);
315
316	cmac->instance->enabled &= ~which;
317	return 0;
318}
319
320static int pm3393_loopback_enable(struct cmac *cmac)
321{
322	return 0;
323}
324
325static int pm3393_loopback_disable(struct cmac *cmac)
326{
327	return 0;
328}
329
330static int pm3393_set_mtu(struct cmac *cmac, int mtu)
331{
332	int enabled = cmac->instance->enabled;
333
334	/* MAX_FRAME_SIZE includes header + FCS, mtu doesn't */
335	mtu += 14 + 4;
336	if (mtu > MAX_FRAME_SIZE)
337		return -EINVAL;
338
339	/* Disable Rx/Tx MAC before configuring it. */
340	if (enabled)
341		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
342
343	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);
344	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);
345
346	if (enabled)
347		pm3393_enable(cmac, enabled);
348	return 0;
349}
350
351static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)
352{
353	int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;
354	u32 rx_mode;
355
356	/* Disable MAC RX before reconfiguring it */
357	if (enabled)
358		pm3393_disable(cmac, MAC_DIRECTION_RX);
359
360	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);
361	rx_mode &= ~(SUNI1x10GEXP_BITMSK_RXXG_PMODE |
362		     SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN);
363	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,
364		(u16)rx_mode);
365
366	if (t1_rx_mode_promisc(rm)) {
367		/* Promiscuous mode. */
368		rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_PMODE;
369	}
370	if (t1_rx_mode_allmulti(rm)) {
371		/* Accept all multicast. */
372		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);
373		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);
374		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);
375		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);
376		rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
377	} else if (t1_rx_mode_mc_cnt(rm)) {
378		/* Accept one or more multicast(s). */
379		struct netdev_hw_addr *ha;
380		int bit;
381		u16 mc_filter[4] = { 0, };
382
383		netdev_for_each_mc_addr(ha, t1_get_netdev(rm)) {
384			/* bit[23:28] */
385			bit = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x3f;
386			mc_filter[bit >> 4] |= 1 << (bit & 0xf);
387		}
388		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);
389		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);
390		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);
391		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);
392		rx_mode |= SUNI1x10GEXP_BITMSK_RXXG_MHASH_EN;
393	}
394
395	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);
396
397	if (enabled)
398		pm3393_enable(cmac, MAC_DIRECTION_RX);
399
400	return 0;
401}
402
403static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,
404				      int *duplex, int *fc)
405{
406	if (speed)
407		*speed = SPEED_10000;
408	if (duplex)
409		*duplex = DUPLEX_FULL;
410	if (fc)
411		*fc = cmac->instance->fc;
412	return 0;
413}
414
415static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,
416				      int fc)
417{
418	if (speed >= 0 && speed != SPEED_10000)
419		return -1;
420	if (duplex >= 0 && duplex != DUPLEX_FULL)
421		return -1;
422	if (fc & ~(PAUSE_TX | PAUSE_RX))
423		return -1;
424
425	if (fc != cmac->instance->fc) {
426		cmac->instance->fc = (u8) fc;
427		if (cmac->instance->enabled & MAC_DIRECTION_TX)
428			pm3393_enable(cmac, MAC_DIRECTION_TX);
429	}
430	return 0;
431}
432
433#define RMON_UPDATE(mac, name, stat_name) \
434{ \
435	t1_tpi_read((mac)->adapter, OFFSET(name), &val0);     \
436	t1_tpi_read((mac)->adapter, OFFSET((name)+1), &val1); \
437	t1_tpi_read((mac)->adapter, OFFSET((name)+2), &val2); \
438	(mac)->stats.stat_name = (u64)(val0 & 0xffff) | \
439				 ((u64)(val1 & 0xffff) << 16) | \
440				 ((u64)(val2 & 0xff) << 32) | \
441				 ((mac)->stats.stat_name & \
442					0xffffff0000000000ULL); \
443	if (ro & \
444	    (1ULL << ((name - SUNI1x10GEXP_REG_MSTAT_COUNTER_0_LOW) >> 2))) \
445		(mac)->stats.stat_name += 1ULL << 40; \
446}
447
448static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,
449							      int flag)
450{
451	u64	ro;
452	u32	val0, val1, val2, val3;
453
454	/* Snap the counters */
455	pmwrite(mac, SUNI1x10GEXP_REG_MSTAT_CONTROL,
456		SUNI1x10GEXP_BITMSK_MSTAT_SNAP);
457
458	/* Counter rollover, clear on read */
459	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_0, &val0);
460	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_1, &val1);
461	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_2, &val2);
462	pmread(mac, SUNI1x10GEXP_REG_MSTAT_COUNTER_ROLLOVER_3, &val3);
463	ro = ((u64)val0 & 0xffff) | (((u64)val1 & 0xffff) << 16) |
464		(((u64)val2 & 0xffff) << 32) | (((u64)val3 & 0xffff) << 48);
465
466	/* Rx stats */
467	RMON_UPDATE(mac, RxOctetsReceivedOK, RxOctetsOK);
468	RMON_UPDATE(mac, RxUnicastFramesReceivedOK, RxUnicastFramesOK);
469	RMON_UPDATE(mac, RxMulticastFramesReceivedOK, RxMulticastFramesOK);
470	RMON_UPDATE(mac, RxBroadcastFramesReceivedOK, RxBroadcastFramesOK);
471	RMON_UPDATE(mac, RxPAUSEMACCtrlFramesReceived, RxPauseFrames);
472	RMON_UPDATE(mac, RxFrameCheckSequenceErrors, RxFCSErrors);
473	RMON_UPDATE(mac, RxFramesLostDueToInternalMACErrors,
474				RxInternalMACRcvError);
475	RMON_UPDATE(mac, RxSymbolErrors, RxSymbolErrors);
476	RMON_UPDATE(mac, RxInRangeLengthErrors, RxInRangeLengthErrors);
477	RMON_UPDATE(mac, RxFramesTooLongErrors , RxFrameTooLongErrors);
478	RMON_UPDATE(mac, RxJabbers, RxJabberErrors);
479	RMON_UPDATE(mac, RxFragments, RxRuntErrors);
480	RMON_UPDATE(mac, RxUndersizedFrames, RxRuntErrors);
481	RMON_UPDATE(mac, RxJumboFramesReceivedOK, RxJumboFramesOK);
482	RMON_UPDATE(mac, RxJumboOctetsReceivedOK, RxJumboOctetsOK);
483
484	/* Tx stats */
485	RMON_UPDATE(mac, TxOctetsTransmittedOK, TxOctetsOK);
486	RMON_UPDATE(mac, TxFramesLostDueToInternalMACTransmissionError,
487				TxInternalMACXmitError);
488	RMON_UPDATE(mac, TxTransmitSystemError, TxFCSErrors);
489	RMON_UPDATE(mac, TxUnicastFramesTransmittedOK, TxUnicastFramesOK);
490	RMON_UPDATE(mac, TxMulticastFramesTransmittedOK, TxMulticastFramesOK);
491	RMON_UPDATE(mac, TxBroadcastFramesTransmittedOK, TxBroadcastFramesOK);
492	RMON_UPDATE(mac, TxPAUSEMACCtrlFramesTransmitted, TxPauseFrames);
493	RMON_UPDATE(mac, TxJumboFramesReceivedOK, TxJumboFramesOK);
494	RMON_UPDATE(mac, TxJumboOctetsReceivedOK, TxJumboOctetsOK);
495
496	return &mac->stats;
497}
498
499static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])
500{
501	memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN);
502	return 0;
503}
504
505static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])
506{
507	u32 val, lo, mid, hi, enabled = cmac->instance->enabled;
508
509	/*
510	 * MAC addr: 00:07:43:00:13:09
511	 *
512	 * ma[5] = 0x09
513	 * ma[4] = 0x13
514	 * ma[3] = 0x00
515	 * ma[2] = 0x43
516	 * ma[1] = 0x07
517	 * ma[0] = 0x00
518	 *
519	 * The PM3393 requires byte swapping and reverse order entry
520	 * when programming MAC addresses:
521	 *
522	 * low_bits[15:0]    = ma[1]:ma[0]
523	 * mid_bits[31:16]   = ma[3]:ma[2]
524	 * high_bits[47:32]  = ma[5]:ma[4]
525	 */
526
527	/* Store local copy */
528	memcpy(cmac->instance->mac_addr, ma, ETH_ALEN);
529
530	lo  = ((u32) ma[1] << 8) | (u32) ma[0];
531	mid = ((u32) ma[3] << 8) | (u32) ma[2];
532	hi  = ((u32) ma[5] << 8) | (u32) ma[4];
533
534	/* Disable Rx/Tx MAC before configuring it. */
535	if (enabled)
536		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
537
538	/* Set RXXG Station Address */
539	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);
540	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);
541	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);
542
543	/* Set TXXG Station Address */
544	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);
545	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);
546	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);
547
548	/* Setup Exact Match Filter 1 with our MAC address
549	 *
550	 * Must disable exact match filter before configuring it.
551	 */
552	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);
553	val &= 0xff0f;
554	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
555
556	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);
557	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);
558	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);
559
560	val |= 0x0090;
561	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);
562
563	if (enabled)
564		pm3393_enable(cmac, enabled);
565	return 0;
566}
567
568static void pm3393_destroy(struct cmac *cmac)
569{
570	kfree(cmac);
571}
572
573static struct cmac_ops pm3393_ops = {
574	.destroy                 = pm3393_destroy,
575	.reset                   = pm3393_reset,
576	.interrupt_enable        = pm3393_interrupt_enable,
577	.interrupt_disable       = pm3393_interrupt_disable,
578	.interrupt_clear         = pm3393_interrupt_clear,
579	.interrupt_handler       = pm3393_interrupt_handler,
580	.enable                  = pm3393_enable_port,
581	.disable                 = pm3393_disable,
582	.loopback_enable         = pm3393_loopback_enable,
583	.loopback_disable        = pm3393_loopback_disable,
584	.set_mtu                 = pm3393_set_mtu,
585	.set_rx_mode             = pm3393_set_rx_mode,
586	.get_speed_duplex_fc     = pm3393_get_speed_duplex_fc,
587	.set_speed_duplex_fc     = pm3393_set_speed_duplex_fc,
588	.statistics_update       = pm3393_update_statistics,
589	.macaddress_get          = pm3393_macaddress_get,
590	.macaddress_set          = pm3393_macaddress_set
591};
592
593static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)
594{
595	struct cmac *cmac;
596
597	cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);
598	if (!cmac)
599		return NULL;
600
601	cmac->ops = &pm3393_ops;
602	cmac->instance = (cmac_instance *) (cmac + 1);
603	cmac->adapter = adapter;
604	cmac->instance->fc = PAUSE_TX | PAUSE_RX;
605
606	t1_tpi_write(adapter, OFFSET(0x0001), 0x00008000);
607	t1_tpi_write(adapter, OFFSET(0x0001), 0x00000000);
608	t1_tpi_write(adapter, OFFSET(0x2308), 0x00009800);
609	t1_tpi_write(adapter, OFFSET(0x2305), 0x00001001);   /* PL4IO Enable */
610	t1_tpi_write(adapter, OFFSET(0x2320), 0x00008800);
611	t1_tpi_write(adapter, OFFSET(0x2321), 0x00008800);
612	t1_tpi_write(adapter, OFFSET(0x2322), 0x00008800);
613	t1_tpi_write(adapter, OFFSET(0x2323), 0x00008800);
614	t1_tpi_write(adapter, OFFSET(0x2324), 0x00008800);
615	t1_tpi_write(adapter, OFFSET(0x2325), 0x00008800);
616	t1_tpi_write(adapter, OFFSET(0x2326), 0x00008800);
617	t1_tpi_write(adapter, OFFSET(0x2327), 0x00008800);
618	t1_tpi_write(adapter, OFFSET(0x2328), 0x00008800);
619	t1_tpi_write(adapter, OFFSET(0x2329), 0x00008800);
620	t1_tpi_write(adapter, OFFSET(0x232a), 0x00008800);
621	t1_tpi_write(adapter, OFFSET(0x232b), 0x00008800);
622	t1_tpi_write(adapter, OFFSET(0x232c), 0x00008800);
623	t1_tpi_write(adapter, OFFSET(0x232d), 0x00008800);
624	t1_tpi_write(adapter, OFFSET(0x232e), 0x00008800);
625	t1_tpi_write(adapter, OFFSET(0x232f), 0x00008800);
626	t1_tpi_write(adapter, OFFSET(0x230d), 0x00009c00);
627	t1_tpi_write(adapter, OFFSET(0x2304), 0x00000202);	/* PL4IO Calendar Repetitions */
628
629	t1_tpi_write(adapter, OFFSET(0x3200), 0x00008080);	/* EFLX Enable */
630	t1_tpi_write(adapter, OFFSET(0x3210), 0x00000000);	/* EFLX Channel Deprovision */
631	t1_tpi_write(adapter, OFFSET(0x3203), 0x00000000);	/* EFLX Low Limit */
632	t1_tpi_write(adapter, OFFSET(0x3204), 0x00000040);	/* EFLX High Limit */
633	t1_tpi_write(adapter, OFFSET(0x3205), 0x000002cc);	/* EFLX Almost Full */
634	t1_tpi_write(adapter, OFFSET(0x3206), 0x00000199);	/* EFLX Almost Empty */
635	t1_tpi_write(adapter, OFFSET(0x3207), 0x00000240);	/* EFLX Cut Through Threshold */
636	t1_tpi_write(adapter, OFFSET(0x3202), 0x00000000);	/* EFLX Indirect Register Update */
637	t1_tpi_write(adapter, OFFSET(0x3210), 0x00000001);	/* EFLX Channel Provision */
638	t1_tpi_write(adapter, OFFSET(0x3208), 0x0000ffff);	/* EFLX Undocumented */
639	t1_tpi_write(adapter, OFFSET(0x320a), 0x0000ffff);	/* EFLX Undocumented */
640	t1_tpi_write(adapter, OFFSET(0x320c), 0x0000ffff);	/* EFLX enable overflow interrupt The other bit are undocumented */
641	t1_tpi_write(adapter, OFFSET(0x320e), 0x0000ffff);	/* EFLX Undocumented */
642
643	t1_tpi_write(adapter, OFFSET(0x2200), 0x0000c000);	/* IFLX Configuration - enable */
644	t1_tpi_write(adapter, OFFSET(0x2201), 0x00000000);	/* IFLX Channel Deprovision */
645	t1_tpi_write(adapter, OFFSET(0x220e), 0x00000000);	/* IFLX Low Limit */
646	t1_tpi_write(adapter, OFFSET(0x220f), 0x00000100);	/* IFLX High Limit */
647	t1_tpi_write(adapter, OFFSET(0x2210), 0x00000c00);	/* IFLX Almost Full Limit */
648	t1_tpi_write(adapter, OFFSET(0x2211), 0x00000599);	/* IFLX Almost Empty Limit */
649	t1_tpi_write(adapter, OFFSET(0x220d), 0x00000000);	/* IFLX Indirect Register Update */
650	t1_tpi_write(adapter, OFFSET(0x2201), 0x00000001);	/* IFLX Channel Provision */
651	t1_tpi_write(adapter, OFFSET(0x2203), 0x0000ffff);	/* IFLX Undocumented */
652	t1_tpi_write(adapter, OFFSET(0x2205), 0x0000ffff);	/* IFLX Undocumented */
653	t1_tpi_write(adapter, OFFSET(0x2209), 0x0000ffff);	/* IFLX Enable overflow interrupt.  The other bit are undocumented */
654
655	t1_tpi_write(adapter, OFFSET(0x2241), 0xfffffffe);	/* PL4MOS Undocumented */
656	t1_tpi_write(adapter, OFFSET(0x2242), 0x0000ffff);	/* PL4MOS Undocumented */
657	t1_tpi_write(adapter, OFFSET(0x2243), 0x00000008);	/* PL4MOS Starving Burst Size */
658	t1_tpi_write(adapter, OFFSET(0x2244), 0x00000008);	/* PL4MOS Hungry Burst Size */
659	t1_tpi_write(adapter, OFFSET(0x2245), 0x00000008);	/* PL4MOS Transfer Size */
660	t1_tpi_write(adapter, OFFSET(0x2240), 0x00000005);	/* PL4MOS Disable */
661
662	t1_tpi_write(adapter, OFFSET(0x2280), 0x00002103);	/* PL4ODP Training Repeat and SOP rule */
663	t1_tpi_write(adapter, OFFSET(0x2284), 0x00000000);	/* PL4ODP MAX_T setting */
664
665	t1_tpi_write(adapter, OFFSET(0x3280), 0x00000087);	/* PL4IDU Enable data forward, port state machine. Set ALLOW_NON_ZERO_OLB */
666	t1_tpi_write(adapter, OFFSET(0x3282), 0x0000001f);	/* PL4IDU Enable Dip4 check error interrupts */
667
668	t1_tpi_write(adapter, OFFSET(0x3040), 0x0c32);	/* # TXXG Config */
669	/* For T1 use timer based Mac flow control. */
670	t1_tpi_write(adapter, OFFSET(0x304d), 0x8000);
671	t1_tpi_write(adapter, OFFSET(0x2040), 0x059c);	/* # RXXG Config */
672	t1_tpi_write(adapter, OFFSET(0x2049), 0x0001);	/* # RXXG Cut Through */
673	t1_tpi_write(adapter, OFFSET(0x2070), 0x0000);	/* # Disable promiscuous mode */
674
675	/* Setup Exact Match Filter 0 to allow broadcast packets.
676	 */
677	t1_tpi_write(adapter, OFFSET(0x206e), 0x0000);	/* # Disable Match Enable bit */
678	t1_tpi_write(adapter, OFFSET(0x204a), 0xffff);	/* # low addr */
679	t1_tpi_write(adapter, OFFSET(0x204b), 0xffff);	/* # mid addr */
680	t1_tpi_write(adapter, OFFSET(0x204c), 0xffff);	/* # high addr */
681	t1_tpi_write(adapter, OFFSET(0x206e), 0x0009);	/* # Enable Match Enable bit */
682
683	t1_tpi_write(adapter, OFFSET(0x0003), 0x0000);	/* # NO SOP/ PAD_EN setup */
684	t1_tpi_write(adapter, OFFSET(0x0100), 0x0ff0);	/* # RXEQB disabled */
685	t1_tpi_write(adapter, OFFSET(0x0101), 0x0f0f);	/* # No Preemphasis */
686
687	return cmac;
688}
689
690static int pm3393_mac_reset(adapter_t * adapter)
691{
692	u32 val;
693	u32 x;
694	u32 is_pl4_reset_finished;
695	u32 is_pl4_outof_lock;
696	u32 is_xaui_mabc_pll_locked;
697	u32 successful_reset;
698	int i;
699
700	/* The following steps are required to properly reset
701	 * the PM3393. This information is provided in the
702	 * PM3393 datasheet (Issue 2: November 2002)
703	 * section 13.1 -- Device Reset.
704	 *
705	 * The PM3393 has three types of components that are
706	 * individually reset:
707	 *
708	 * DRESETB      - Digital circuitry
709	 * PL4_ARESETB  - PL4 analog circuitry
710	 * XAUI_ARESETB - XAUI bus analog circuitry
711	 *
712	 * Steps to reset PM3393 using RSTB pin:
713	 *
714	 * 1. Assert RSTB pin low ( write 0 )
715	 * 2. Wait at least 1ms to initiate a complete initialization of device.
716	 * 3. Wait until all external clocks and REFSEL are stable.
717	 * 4. Wait minimum of 1ms. (after external clocks and REFEL are stable)
718	 * 5. De-assert RSTB ( write 1 )
719	 * 6. Wait until internal timers to expires after ~14ms.
720	 *    - Allows analog clock synthesizer(PL4CSU) to stabilize to
721	 *      selected reference frequency before allowing the digital
722	 *      portion of the device to operate.
723	 * 7. Wait at least 200us for XAUI interface to stabilize.
724	 * 8. Verify the PM3393 came out of reset successfully.
725	 *    Set successful reset flag if everything worked else try again
726	 *    a few more times.
727	 */
728
729	successful_reset = 0;
730	for (i = 0; i < 3 && !successful_reset; i++) {
731		/* 1 */
732		t1_tpi_read(adapter, A_ELMER0_GPO, &val);
733		val &= ~1;
734		t1_tpi_write(adapter, A_ELMER0_GPO, val);
735
736		/* 2 */
737		msleep(1);
738
739		/* 3 */
740		msleep(1);
741
742		/* 4 */
743		msleep(2 /*1 extra ms for safety */ );
744
745		/* 5 */
746		val |= 1;
747		t1_tpi_write(adapter, A_ELMER0_GPO, val);
748
749		/* 6 */
750		msleep(15 /*1 extra ms for safety */ );
751
752		/* 7 */
753		msleep(1);
754
755		/* 8 */
756
757		/* Has PL4 analog block come out of reset correctly? */
758		t1_tpi_read(adapter, OFFSET(SUNI1x10GEXP_REG_DEVICE_STATUS), &val);
759		is_pl4_reset_finished = (val & SUNI1x10GEXP_BITMSK_TOP_EXPIRED);
760
761		/* TBD XXX SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL gets locked later in the init sequence
762		 *         figure out why? */
763
764		/* Have all PL4 block clocks locked? */
765		x = (SUNI1x10GEXP_BITMSK_TOP_PL4_ID_DOOL
766		     /*| SUNI1x10GEXP_BITMSK_TOP_PL4_IS_DOOL */  |
767		     SUNI1x10GEXP_BITMSK_TOP_PL4_ID_ROOL |
768		     SUNI1x10GEXP_BITMSK_TOP_PL4_IS_ROOL |
769		     SUNI1x10GEXP_BITMSK_TOP_PL4_OUT_ROOL);
770		is_pl4_outof_lock = (val & x);
771
772		/* ??? If this fails, might be able to software reset the XAUI part
773		 *     and try to recover... thus saving us from doing another HW reset */
774		/* Has the XAUI MABC PLL circuitry stablized? */
775		is_xaui_mabc_pll_locked =
776		    (val & SUNI1x10GEXP_BITMSK_TOP_SXRA_EXPIRED);
777
778		successful_reset = (is_pl4_reset_finished && !is_pl4_outof_lock
779				    && is_xaui_mabc_pll_locked);
780
781		if (netif_msg_hw(adapter))
782			dev_dbg(&adapter->pdev->dev,
783				"PM3393 HW reset %d: pl4_reset 0x%x, val 0x%x, "
784				"is_pl4_outof_lock 0x%x, xaui_locked 0x%x\n",
785				i, is_pl4_reset_finished, val,
786				is_pl4_outof_lock, is_xaui_mabc_pll_locked);
787	}
788	return successful_reset ? 0 : 1;
789}
790
791const struct gmac t1_pm3393_ops = {
792	.stats_update_period = STATS_TICK_SECS,
793	.create              = pm3393_mac_create,
794	.reset               = pm3393_mac_reset,
795};
796