1/* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#ifndef __T4_MSG_H 36#define __T4_MSG_H 37 38#include <linux/types.h> 39 40enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 55 CPL_CLOSE_LISTSRV_RPL = 0x20, 56 CPL_L2T_WRITE_RPL = 0x23, 57 CPL_PASS_OPEN_RPL = 0x24, 58 CPL_ACT_OPEN_RPL = 0x25, 59 CPL_PEER_CLOSE = 0x26, 60 CPL_ABORT_REQ_RSS = 0x2B, 61 CPL_ABORT_RPL_RSS = 0x2D, 62 63 CPL_CLOSE_CON_RPL = 0x32, 64 CPL_ISCSI_HDR = 0x33, 65 CPL_RDMA_CQE = 0x35, 66 CPL_RDMA_CQE_READ_RSP = 0x36, 67 CPL_RDMA_CQE_ERR = 0x37, 68 CPL_RX_DATA = 0x39, 69 CPL_SET_TCB_RPL = 0x3A, 70 CPL_RX_PKT = 0x3B, 71 CPL_RX_DDP_COMPLETE = 0x3F, 72 73 CPL_ACT_ESTABLISH = 0x40, 74 CPL_PASS_ESTABLISH = 0x41, 75 CPL_RX_DATA_DDP = 0x42, 76 CPL_PASS_ACCEPT_REQ = 0x44, 77 CPL_TRACE_PKT_T5 = 0x48, 78 CPL_RX_ISCSI_DDP = 0x49, 79 80 CPL_RDMA_READ_REQ = 0x60, 81 82 CPL_PASS_OPEN_REQ6 = 0x81, 83 CPL_ACT_OPEN_REQ6 = 0x83, 84 85 CPL_RDMA_TERMINATE = 0xA2, 86 CPL_RDMA_WRITE = 0xA4, 87 CPL_SGE_EGR_UPDATE = 0xA5, 88 89 CPL_TRACE_PKT = 0xB0, 90 CPL_ISCSI_DATA = 0xB2, 91 92 CPL_FW4_MSG = 0xC0, 93 CPL_FW4_PLD = 0xC1, 94 CPL_FW4_ACK = 0xC3, 95 96 CPL_FW6_MSG = 0xE0, 97 CPL_FW6_PLD = 0xE1, 98 CPL_TX_PKT_LSO = 0xED, 99 CPL_TX_PKT_XT = 0xEE, 100 101 NUM_CPL_CMDS 102}; 103 104enum CPL_error { 105 CPL_ERR_NONE = 0, 106 CPL_ERR_TCAM_FULL = 3, 107 CPL_ERR_BAD_LENGTH = 15, 108 CPL_ERR_BAD_ROUTE = 18, 109 CPL_ERR_CONN_RESET = 20, 110 CPL_ERR_CONN_EXIST_SYNRECV = 21, 111 CPL_ERR_CONN_EXIST = 22, 112 CPL_ERR_ARP_MISS = 23, 113 CPL_ERR_BAD_SYN = 24, 114 CPL_ERR_CONN_TIMEDOUT = 30, 115 CPL_ERR_XMIT_TIMEDOUT = 31, 116 CPL_ERR_PERSIST_TIMEDOUT = 32, 117 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 118 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 119 CPL_ERR_RTX_NEG_ADVICE = 35, 120 CPL_ERR_PERSIST_NEG_ADVICE = 36, 121 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 122 CPL_ERR_ABORT_FAILED = 42, 123 CPL_ERR_IWARP_FLM = 50, 124}; 125 126enum { 127 CPL_CONN_POLICY_AUTO = 0, 128 CPL_CONN_POLICY_ASK = 1, 129 CPL_CONN_POLICY_FILTER = 2, 130 CPL_CONN_POLICY_DENY = 3 131}; 132 133enum { 134 ULP_MODE_NONE = 0, 135 ULP_MODE_ISCSI = 2, 136 ULP_MODE_RDMA = 4, 137 ULP_MODE_TCPDDP = 5, 138 ULP_MODE_FCOE = 6, 139}; 140 141enum { 142 ULP_CRC_HEADER = 1 << 0, 143 ULP_CRC_DATA = 1 << 1 144}; 145 146enum { 147 CPL_ABORT_SEND_RST = 0, 148 CPL_ABORT_NO_RST, 149}; 150 151enum { /* TX_PKT_XT checksum types */ 152 TX_CSUM_TCP = 0, 153 TX_CSUM_UDP = 1, 154 TX_CSUM_CRC16 = 4, 155 TX_CSUM_CRC32 = 5, 156 TX_CSUM_CRC32C = 6, 157 TX_CSUM_FCOE = 7, 158 TX_CSUM_TCPIP = 8, 159 TX_CSUM_UDPIP = 9, 160 TX_CSUM_TCPIP6 = 10, 161 TX_CSUM_UDPIP6 = 11, 162 TX_CSUM_IP = 12, 163}; 164 165union opcode_tid { 166 __be32 opcode_tid; 167 u8 opcode; 168}; 169 170#define CPL_OPCODE_S 24 171#define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 172#define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 173#define TID_G(x) ((x) & 0xFFFFFF) 174 175/* tid is assumed to be 24-bits */ 176#define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 177 178#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 179 180/* extract the TID from a CPL command */ 181#define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 182 183/* partitioning of TID fields that also carry a queue id */ 184#define TID_TID_S 0 185#define TID_TID_M 0x3fff 186#define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 187 188#define TID_QID_S 14 189#define TID_QID_M 0x3ff 190#define TID_QID_V(x) ((x) << TID_QID_S) 191#define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 192 193struct rss_header { 194 u8 opcode; 195#if defined(__LITTLE_ENDIAN_BITFIELD) 196 u8 channel:2; 197 u8 filter_hit:1; 198 u8 filter_tid:1; 199 u8 hash_type:2; 200 u8 ipv6:1; 201 u8 send2fw:1; 202#else 203 u8 send2fw:1; 204 u8 ipv6:1; 205 u8 hash_type:2; 206 u8 filter_tid:1; 207 u8 filter_hit:1; 208 u8 channel:2; 209#endif 210 __be16 qid; 211 __be32 hash_val; 212}; 213 214struct work_request_hdr { 215 __be32 wr_hi; 216 __be32 wr_mid; 217 __be64 wr_lo; 218}; 219 220/* wr_hi fields */ 221#define WR_OP_S 24 222#define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 223 224#define WR_HDR struct work_request_hdr wr 225 226/* option 0 fields */ 227#define TX_CHAN_S 2 228#define TX_CHAN_V(x) ((x) << TX_CHAN_S) 229 230#define ULP_MODE_S 8 231#define ULP_MODE_V(x) ((x) << ULP_MODE_S) 232 233#define RCV_BUFSIZ_S 12 234#define RCV_BUFSIZ_M 0x3FFU 235#define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 236 237#define SMAC_SEL_S 28 238#define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 239 240#define L2T_IDX_S 36 241#define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 242 243#define WND_SCALE_S 50 244#define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 245 246#define KEEP_ALIVE_S 54 247#define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 248#define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 249 250#define MSS_IDX_S 60 251#define MSS_IDX_M 0xF 252#define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 253#define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 254 255/* option 2 fields */ 256#define RSS_QUEUE_S 0 257#define RSS_QUEUE_M 0x3FF 258#define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 259#define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 260 261#define RSS_QUEUE_VALID_S 10 262#define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 263#define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 264 265#define RX_FC_DISABLE_S 20 266#define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 267#define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 268 269#define RX_FC_VALID_S 22 270#define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 271#define RX_FC_VALID_F RX_FC_VALID_V(1U) 272 273#define RX_CHANNEL_S 26 274#define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 275 276#define WND_SCALE_EN_S 28 277#define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 278#define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 279 280#define T5_OPT_2_VALID_S 31 281#define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 282#define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 283 284struct cpl_pass_open_req { 285 WR_HDR; 286 union opcode_tid ot; 287 __be16 local_port; 288 __be16 peer_port; 289 __be32 local_ip; 290 __be32 peer_ip; 291 __be64 opt0; 292 __be64 opt1; 293}; 294 295/* option 0 fields */ 296#define NO_CONG_S 4 297#define NO_CONG_V(x) ((x) << NO_CONG_S) 298#define NO_CONG_F NO_CONG_V(1U) 299 300#define DELACK_S 5 301#define DELACK_V(x) ((x) << DELACK_S) 302#define DELACK_F DELACK_V(1U) 303 304#define DSCP_S 22 305#define DSCP_M 0x3F 306#define DSCP_V(x) ((x) << DSCP_S) 307#define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 308 309#define TCAM_BYPASS_S 48 310#define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 311#define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 312 313#define NAGLE_S 49 314#define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 315#define NAGLE_F NAGLE_V(1ULL) 316 317/* option 1 fields */ 318#define SYN_RSS_ENABLE_S 0 319#define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 320#define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 321 322#define SYN_RSS_QUEUE_S 2 323#define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 324 325#define CONN_POLICY_S 22 326#define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 327 328struct cpl_pass_open_req6 { 329 WR_HDR; 330 union opcode_tid ot; 331 __be16 local_port; 332 __be16 peer_port; 333 __be64 local_ip_hi; 334 __be64 local_ip_lo; 335 __be64 peer_ip_hi; 336 __be64 peer_ip_lo; 337 __be64 opt0; 338 __be64 opt1; 339}; 340 341struct cpl_pass_open_rpl { 342 union opcode_tid ot; 343 u8 rsvd[3]; 344 u8 status; 345}; 346 347struct cpl_pass_accept_rpl { 348 WR_HDR; 349 union opcode_tid ot; 350 __be32 opt2; 351 __be64 opt0; 352}; 353 354/* option 2 fields */ 355#define RX_COALESCE_VALID_S 11 356#define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 357#define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 358 359#define RX_COALESCE_S 12 360#define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 361 362#define PACE_S 16 363#define PACE_V(x) ((x) << PACE_S) 364 365#define TX_QUEUE_S 23 366#define TX_QUEUE_M 0x7 367#define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 368#define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 369 370#define CCTRL_ECN_S 27 371#define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 372#define CCTRL_ECN_F CCTRL_ECN_V(1U) 373 374#define TSTAMPS_EN_S 29 375#define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 376#define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 377 378#define SACK_EN_S 30 379#define SACK_EN_V(x) ((x) << SACK_EN_S) 380#define SACK_EN_F SACK_EN_V(1U) 381 382struct cpl_t5_pass_accept_rpl { 383 WR_HDR; 384 union opcode_tid ot; 385 __be32 opt2; 386 __be64 opt0; 387 __be32 iss; 388 __be32 rsvd; 389}; 390 391struct cpl_act_open_req { 392 WR_HDR; 393 union opcode_tid ot; 394 __be16 local_port; 395 __be16 peer_port; 396 __be32 local_ip; 397 __be32 peer_ip; 398 __be64 opt0; 399 __be32 params; 400 __be32 opt2; 401}; 402 403#define FILTER_TUPLE_S 24 404#define FILTER_TUPLE_M 0xFFFFFFFFFF 405#define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 406#define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 407struct cpl_t5_act_open_req { 408 WR_HDR; 409 union opcode_tid ot; 410 __be16 local_port; 411 __be16 peer_port; 412 __be32 local_ip; 413 __be32 peer_ip; 414 __be64 opt0; 415 __be32 rsvd; 416 __be32 opt2; 417 __be64 params; 418}; 419 420struct cpl_act_open_req6 { 421 WR_HDR; 422 union opcode_tid ot; 423 __be16 local_port; 424 __be16 peer_port; 425 __be64 local_ip_hi; 426 __be64 local_ip_lo; 427 __be64 peer_ip_hi; 428 __be64 peer_ip_lo; 429 __be64 opt0; 430 __be32 params; 431 __be32 opt2; 432}; 433 434struct cpl_t5_act_open_req6 { 435 WR_HDR; 436 union opcode_tid ot; 437 __be16 local_port; 438 __be16 peer_port; 439 __be64 local_ip_hi; 440 __be64 local_ip_lo; 441 __be64 peer_ip_hi; 442 __be64 peer_ip_lo; 443 __be64 opt0; 444 __be32 rsvd; 445 __be32 opt2; 446 __be64 params; 447}; 448 449struct cpl_act_open_rpl { 450 union opcode_tid ot; 451 __be32 atid_status; 452}; 453 454/* cpl_act_open_rpl.atid_status fields */ 455#define AOPEN_STATUS_S 0 456#define AOPEN_STATUS_M 0xFF 457#define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 458 459#define AOPEN_ATID_S 8 460#define AOPEN_ATID_M 0xFFFFFF 461#define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 462 463struct cpl_pass_establish { 464 union opcode_tid ot; 465 __be32 rsvd; 466 __be32 tos_stid; 467 __be16 mac_idx; 468 __be16 tcp_opt; 469 __be32 snd_isn; 470 __be32 rcv_isn; 471}; 472 473/* cpl_pass_establish.tos_stid fields */ 474#define PASS_OPEN_TID_S 0 475#define PASS_OPEN_TID_M 0xFFFFFF 476#define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 477#define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 478 479#define PASS_OPEN_TOS_S 24 480#define PASS_OPEN_TOS_M 0xFF 481#define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 482#define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 483 484/* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 485#define TCPOPT_WSCALE_OK_S 5 486#define TCPOPT_WSCALE_OK_M 0x1 487#define TCPOPT_WSCALE_OK_G(x) \ 488 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 489 490#define TCPOPT_SACK_S 6 491#define TCPOPT_SACK_M 0x1 492#define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 493 494#define TCPOPT_TSTAMP_S 7 495#define TCPOPT_TSTAMP_M 0x1 496#define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 497 498#define TCPOPT_SND_WSCALE_S 8 499#define TCPOPT_SND_WSCALE_M 0xF 500#define TCPOPT_SND_WSCALE_G(x) \ 501 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 502 503#define TCPOPT_MSS_S 12 504#define TCPOPT_MSS_M 0xF 505#define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 506 507struct cpl_act_establish { 508 union opcode_tid ot; 509 __be32 rsvd; 510 __be32 tos_atid; 511 __be16 mac_idx; 512 __be16 tcp_opt; 513 __be32 snd_isn; 514 __be32 rcv_isn; 515}; 516 517struct cpl_get_tcb { 518 WR_HDR; 519 union opcode_tid ot; 520 __be16 reply_ctrl; 521 __be16 cookie; 522}; 523 524/* cpl_get_tcb.reply_ctrl fields */ 525#define QUEUENO_S 0 526#define QUEUENO_V(x) ((x) << QUEUENO_S) 527 528#define REPLY_CHAN_S 14 529#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 530#define REPLY_CHAN_F REPLY_CHAN_V(1U) 531 532#define NO_REPLY_S 15 533#define NO_REPLY_V(x) ((x) << NO_REPLY_S) 534#define NO_REPLY_F NO_REPLY_V(1U) 535 536struct cpl_set_tcb_field { 537 WR_HDR; 538 union opcode_tid ot; 539 __be16 reply_ctrl; 540 __be16 word_cookie; 541 __be64 mask; 542 __be64 val; 543}; 544 545/* cpl_set_tcb_field.word_cookie fields */ 546#define TCB_WORD_S 0 547#define TCB_WORD(x) ((x) << TCB_WORD_S) 548 549#define TCB_COOKIE_S 5 550#define TCB_COOKIE_M 0x7 551#define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 552#define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 553 554struct cpl_set_tcb_rpl { 555 union opcode_tid ot; 556 __be16 rsvd; 557 u8 cookie; 558 u8 status; 559 __be64 oldval; 560}; 561 562struct cpl_close_con_req { 563 WR_HDR; 564 union opcode_tid ot; 565 __be32 rsvd; 566}; 567 568struct cpl_close_con_rpl { 569 union opcode_tid ot; 570 u8 rsvd[3]; 571 u8 status; 572 __be32 snd_nxt; 573 __be32 rcv_nxt; 574}; 575 576struct cpl_close_listsvr_req { 577 WR_HDR; 578 union opcode_tid ot; 579 __be16 reply_ctrl; 580 __be16 rsvd; 581}; 582 583/* additional cpl_close_listsvr_req.reply_ctrl field */ 584#define LISTSVR_IPV6_S 14 585#define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 586#define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 587 588struct cpl_close_listsvr_rpl { 589 union opcode_tid ot; 590 u8 rsvd[3]; 591 u8 status; 592}; 593 594struct cpl_abort_req_rss { 595 union opcode_tid ot; 596 u8 rsvd[3]; 597 u8 status; 598}; 599 600struct cpl_abort_req { 601 WR_HDR; 602 union opcode_tid ot; 603 __be32 rsvd0; 604 u8 rsvd1; 605 u8 cmd; 606 u8 rsvd2[6]; 607}; 608 609struct cpl_abort_rpl_rss { 610 union opcode_tid ot; 611 u8 rsvd[3]; 612 u8 status; 613}; 614 615struct cpl_abort_rpl { 616 WR_HDR; 617 union opcode_tid ot; 618 __be32 rsvd0; 619 u8 rsvd1; 620 u8 cmd; 621 u8 rsvd2[6]; 622}; 623 624struct cpl_peer_close { 625 union opcode_tid ot; 626 __be32 rcv_nxt; 627}; 628 629struct cpl_tid_release { 630 WR_HDR; 631 union opcode_tid ot; 632 __be32 rsvd; 633}; 634 635struct cpl_tx_pkt_core { 636 __be32 ctrl0; 637#define TXPKT_VF(x) ((x) << 0) 638#define TXPKT_PF(x) ((x) << 8) 639#define TXPKT_VF_VLD (1 << 11) 640#define TXPKT_OVLAN_IDX(x) ((x) << 12) 641#define TXPKT_INTF(x) ((x) << 16) 642#define TXPKT_INS_OVLAN (1 << 21) 643#define TXPKT_OPCODE(x) ((x) << 24) 644 __be16 pack; 645 __be16 len; 646 __be64 ctrl1; 647#define TXPKT_CSUM_END(x) ((x) << 12) 648#define TXPKT_CSUM_START(x) ((x) << 20) 649#define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20) 650#define TXPKT_CSUM_LOC(x) ((u64)(x) << 30) 651#define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34) 652#define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40) 653#define TXPKT_VLAN(x) ((u64)(x) << 44) 654#define TXPKT_VLAN_VLD (1ULL << 60) 655#define TXPKT_IPCSUM_DIS (1ULL << 62) 656#define TXPKT_L4CSUM_DIS (1ULL << 63) 657}; 658 659struct cpl_tx_pkt { 660 WR_HDR; 661 struct cpl_tx_pkt_core c; 662}; 663 664#define cpl_tx_pkt_xt cpl_tx_pkt 665 666struct cpl_tx_pkt_lso_core { 667 __be32 lso_ctrl; 668#define LSO_TCPHDR_LEN(x) ((x) << 0) 669#define LSO_IPHDR_LEN(x) ((x) << 4) 670#define LSO_ETHHDR_LEN(x) ((x) << 16) 671#define LSO_IPV6(x) ((x) << 20) 672#define LSO_LAST_SLICE (1 << 22) 673#define LSO_FIRST_SLICE (1 << 23) 674#define LSO_OPCODE(x) ((x) << 24) 675#define LSO_T5_XFER_SIZE(x) ((x) << 0) 676 __be16 ipid_ofst; 677 __be16 mss; 678 __be32 seqno_offset; 679 __be32 len; 680 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 681}; 682 683/* cpl_tx_pkt_lso_core.lso_ctrl fields */ 684#define LSO_TCPHDR_LEN_S 0 685#define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 686 687#define LSO_IPHDR_LEN_S 4 688#define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 689 690#define LSO_ETHHDR_LEN_S 16 691#define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 692 693#define LSO_IPV6_S 20 694#define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 695#define LSO_IPV6_F LSO_IPV6_V(1U) 696 697#define LSO_LAST_SLICE_S 22 698#define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 699#define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 700 701#define LSO_FIRST_SLICE_S 23 702#define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 703#define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 704 705#define LSO_OPCODE_S 24 706#define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 707 708#define LSO_T5_XFER_SIZE_S 0 709#define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 710 711struct cpl_tx_pkt_lso { 712 WR_HDR; 713 struct cpl_tx_pkt_lso_core c; 714 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 715}; 716 717struct cpl_iscsi_hdr { 718 union opcode_tid ot; 719 __be16 pdu_len_ddp; 720 __be16 len; 721 __be32 seq; 722 __be16 urg; 723 u8 rsvd; 724 u8 status; 725}; 726 727/* cpl_iscsi_hdr.pdu_len_ddp fields */ 728#define ISCSI_PDU_LEN_S 0 729#define ISCSI_PDU_LEN_M 0x7FFF 730#define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 731#define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 732 733#define ISCSI_DDP_S 15 734#define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 735#define ISCSI_DDP_F ISCSI_DDP_V(1U) 736 737struct cpl_rx_data { 738 union opcode_tid ot; 739 __be16 rsvd; 740 __be16 len; 741 __be32 seq; 742 __be16 urg; 743#if defined(__LITTLE_ENDIAN_BITFIELD) 744 u8 dack_mode:2; 745 u8 psh:1; 746 u8 heartbeat:1; 747 u8 ddp_off:1; 748 u8 :3; 749#else 750 u8 :3; 751 u8 ddp_off:1; 752 u8 heartbeat:1; 753 u8 psh:1; 754 u8 dack_mode:2; 755#endif 756 u8 status; 757}; 758 759struct cpl_rx_data_ack { 760 WR_HDR; 761 union opcode_tid ot; 762 __be32 credit_dack; 763}; 764 765/* cpl_rx_data_ack.ack_seq fields */ 766#define RX_CREDITS_S 0 767#define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 768 769#define RX_FORCE_ACK_S 28 770#define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 771#define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 772 773struct cpl_rx_pkt { 774 struct rss_header rsshdr; 775 u8 opcode; 776#if defined(__LITTLE_ENDIAN_BITFIELD) 777 u8 iff:4; 778 u8 csum_calc:1; 779 u8 ipmi_pkt:1; 780 u8 vlan_ex:1; 781 u8 ip_frag:1; 782#else 783 u8 ip_frag:1; 784 u8 vlan_ex:1; 785 u8 ipmi_pkt:1; 786 u8 csum_calc:1; 787 u8 iff:4; 788#endif 789 __be16 csum; 790 __be16 vlan; 791 __be16 len; 792 __be32 l2info; 793 __be16 hdr_len; 794 __be16 err_vec; 795}; 796 797#define RXF_PSH_S 20 798#define RXF_PSH_V(x) ((x) << RXF_PSH_S) 799#define RXF_PSH_F RXF_PSH_V(1U) 800 801#define RXF_SYN_S 21 802#define RXF_SYN_V(x) ((x) << RXF_SYN_S) 803#define RXF_SYN_F RXF_SYN_V(1U) 804 805#define RXF_UDP_S 22 806#define RXF_UDP_V(x) ((x) << RXF_UDP_S) 807#define RXF_UDP_F RXF_UDP_V(1U) 808 809#define RXF_TCP_S 23 810#define RXF_TCP_V(x) ((x) << RXF_TCP_S) 811#define RXF_TCP_F RXF_TCP_V(1U) 812 813#define RXF_IP_S 24 814#define RXF_IP_V(x) ((x) << RXF_IP_S) 815#define RXF_IP_F RXF_IP_V(1U) 816 817#define RXF_IP6_S 25 818#define RXF_IP6_V(x) ((x) << RXF_IP6_S) 819#define RXF_IP6_F RXF_IP6_V(1U) 820 821#define RXF_SYN_COOKIE_S 26 822#define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 823#define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 824 825#define RXF_FCOE_S 26 826#define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 827#define RXF_FCOE_F RXF_FCOE_V(1U) 828 829#define RXF_LRO_S 27 830#define RXF_LRO_V(x) ((x) << RXF_LRO_S) 831#define RXF_LRO_F RXF_LRO_V(1U) 832 833/* rx_pkt.l2info fields */ 834#define RX_ETHHDR_LEN_S 0 835#define RX_ETHHDR_LEN_M 0x1F 836#define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 837#define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 838 839#define RX_T5_ETHHDR_LEN_S 0 840#define RX_T5_ETHHDR_LEN_M 0x3F 841#define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 842#define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 843 844#define RX_MACIDX_S 8 845#define RX_MACIDX_M 0x1FF 846#define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 847#define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 848 849#define RXF_SYN_S 21 850#define RXF_SYN_V(x) ((x) << RXF_SYN_S) 851#define RXF_SYN_F RXF_SYN_V(1U) 852 853#define RX_CHAN_S 28 854#define RX_CHAN_M 0xF 855#define RX_CHAN_V(x) ((x) << RX_CHAN_S) 856#define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 857 858/* rx_pkt.hdr_len fields */ 859#define RX_TCPHDR_LEN_S 0 860#define RX_TCPHDR_LEN_M 0x3F 861#define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 862#define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 863 864#define RX_IPHDR_LEN_S 6 865#define RX_IPHDR_LEN_M 0x3FF 866#define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 867#define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 868 869/* rx_pkt.err_vec fields */ 870#define RXERR_CSUM_S 13 871#define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 872#define RXERR_CSUM_F RXERR_CSUM_V(1U) 873 874struct cpl_trace_pkt { 875 u8 opcode; 876 u8 intf; 877#if defined(__LITTLE_ENDIAN_BITFIELD) 878 u8 runt:4; 879 u8 filter_hit:4; 880 u8 :6; 881 u8 err:1; 882 u8 trunc:1; 883#else 884 u8 filter_hit:4; 885 u8 runt:4; 886 u8 trunc:1; 887 u8 err:1; 888 u8 :6; 889#endif 890 __be16 rsvd; 891 __be16 len; 892 __be64 tstamp; 893}; 894 895struct cpl_t5_trace_pkt { 896 __u8 opcode; 897 __u8 intf; 898#if defined(__LITTLE_ENDIAN_BITFIELD) 899 __u8 runt:4; 900 __u8 filter_hit:4; 901 __u8:6; 902 __u8 err:1; 903 __u8 trunc:1; 904#else 905 __u8 filter_hit:4; 906 __u8 runt:4; 907 __u8 trunc:1; 908 __u8 err:1; 909 __u8:6; 910#endif 911 __be16 rsvd; 912 __be16 len; 913 __be64 tstamp; 914 __be64 rsvd1; 915}; 916 917struct cpl_l2t_write_req { 918 WR_HDR; 919 union opcode_tid ot; 920 __be16 params; 921 __be16 l2t_idx; 922 __be16 vlan; 923 u8 dst_mac[6]; 924}; 925 926/* cpl_l2t_write_req.params fields */ 927#define L2T_W_INFO_S 2 928#define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 929 930#define L2T_W_PORT_S 8 931#define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 932 933#define L2T_W_NOREPLY_S 15 934#define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 935#define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 936 937struct cpl_l2t_write_rpl { 938 union opcode_tid ot; 939 u8 status; 940 u8 rsvd[3]; 941}; 942 943struct cpl_rdma_terminate { 944 union opcode_tid ot; 945 __be16 rsvd; 946 __be16 len; 947}; 948 949struct cpl_sge_egr_update { 950 __be32 opcode_qid; 951 __be16 cidx; 952 __be16 pidx; 953}; 954 955/* cpl_sge_egr_update.ot fields */ 956#define EGR_QID_S 0 957#define EGR_QID_M 0x1FFFF 958#define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 959 960/* cpl_fw*.type values */ 961enum { 962 FW_TYPE_CMD_RPL = 0, 963 FW_TYPE_WR_RPL = 1, 964 FW_TYPE_CQE = 2, 965 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 966 FW_TYPE_RSSCPL = 4, 967}; 968 969struct cpl_fw4_pld { 970 u8 opcode; 971 u8 rsvd0[3]; 972 u8 type; 973 u8 rsvd1; 974 __be16 len; 975 __be64 data; 976 __be64 rsvd2; 977}; 978 979struct cpl_fw6_pld { 980 u8 opcode; 981 u8 rsvd[5]; 982 __be16 len; 983 __be64 data[4]; 984}; 985 986struct cpl_fw4_msg { 987 u8 opcode; 988 u8 type; 989 __be16 rsvd0; 990 __be32 rsvd1; 991 __be64 data[2]; 992}; 993 994struct cpl_fw4_ack { 995 union opcode_tid ot; 996 u8 credits; 997 u8 rsvd0[2]; 998 u8 seq_vld; 999 __be32 snd_nxt; 1000 __be32 snd_una; 1001 __be64 rsvd1; 1002}; 1003 1004struct cpl_fw6_msg { 1005 u8 opcode; 1006 u8 type; 1007 __be16 rsvd0; 1008 __be32 rsvd1; 1009 __be64 data[4]; 1010}; 1011 1012/* cpl_fw6_msg.type values */ 1013enum { 1014 FW6_TYPE_CMD_RPL = 0, 1015 FW6_TYPE_WR_RPL = 1, 1016 FW6_TYPE_CQE = 2, 1017 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1018 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1019}; 1020 1021struct cpl_fw6_msg_ofld_connection_wr_rpl { 1022 __u64 cookie; 1023 __be32 tid; /* or atid in case of active failure */ 1024 __u8 t_state; 1025 __u8 retval; 1026 __u8 rsvd[2]; 1027}; 1028 1029enum { 1030 ULP_TX_MEM_READ = 2, 1031 ULP_TX_MEM_WRITE = 3, 1032 ULP_TX_PKT = 4 1033}; 1034 1035enum { 1036 ULP_TX_SC_NOOP = 0x80, 1037 ULP_TX_SC_IMM = 0x81, 1038 ULP_TX_SC_DSGL = 0x82, 1039 ULP_TX_SC_ISGL = 0x83 1040}; 1041 1042#define ULPTX_CMD_S 24 1043#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1044 1045struct ulptx_sge_pair { 1046 __be32 len[2]; 1047 __be64 addr[2]; 1048}; 1049 1050struct ulptx_sgl { 1051 __be32 cmd_nsge; 1052 __be32 len0; 1053 __be64 addr0; 1054 struct ulptx_sge_pair sge[0]; 1055}; 1056 1057#define ULPTX_NSGE_S 0 1058#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1059 1060#define ULPTX_MORE_S 23 1061#define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1062#define ULPTX_MORE_F ULPTX_MORE_V(1U) 1063 1064struct ulp_mem_io { 1065 WR_HDR; 1066 __be32 cmd; 1067 __be32 len16; /* command length */ 1068 __be32 dlen; /* data length in 32-byte units */ 1069 __be32 lock_addr; 1070}; 1071 1072#define ULP_MEMIO_LOCK_S 31 1073#define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1074#define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1075 1076/* additional ulp_mem_io.cmd fields */ 1077#define ULP_MEMIO_ORDER_S 23 1078#define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1079#define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1080 1081#define T5_ULP_MEMIO_IMM_S 23 1082#define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1083#define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1084 1085#define T5_ULP_MEMIO_ORDER_S 22 1086#define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1087#define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1088 1089/* ulp_mem_io.lock_addr fields */ 1090#define ULP_MEMIO_ADDR_S 0 1091#define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1092 1093/* ulp_mem_io.dlen fields */ 1094#define ULP_MEMIO_DATA_LEN_S 0 1095#define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1096 1097#endif /* __T4_MSG_H */ 1098