1/* 2 * Copyright (C) 2005 - 2014 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18#ifndef BE_H 19#define BE_H 20 21#include <linux/pci.h> 22#include <linux/etherdevice.h> 23#include <linux/delay.h> 24#include <net/tcp.h> 25#include <net/ip.h> 26#include <net/ipv6.h> 27#include <linux/if_vlan.h> 28#include <linux/workqueue.h> 29#include <linux/interrupt.h> 30#include <linux/firmware.h> 31#include <linux/slab.h> 32#include <linux/u64_stats_sync.h> 33#include <linux/cpumask.h> 34 35#include "be_hw.h" 36#include "be_roce.h" 37 38#define DRV_VER "10.6.0.1" 39#define DRV_NAME "be2net" 40#define BE_NAME "Emulex BladeEngine2" 41#define BE3_NAME "Emulex BladeEngine3" 42#define OC_NAME "Emulex OneConnect" 43#define OC_NAME_BE OC_NAME "(be3)" 44#define OC_NAME_LANCER OC_NAME "(Lancer)" 45#define OC_NAME_SH OC_NAME "(Skyhawk)" 46#define DRV_DESC "Emulex OneConnect NIC Driver" 47 48#define BE_VENDOR_ID 0x19a2 49#define EMULEX_VENDOR_ID 0x10df 50#define BE_DEVICE_ID1 0x211 51#define BE_DEVICE_ID2 0x221 52#define OC_DEVICE_ID1 0x700 /* Device Id for BE2 cards */ 53#define OC_DEVICE_ID2 0x710 /* Device Id for BE3 cards */ 54#define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ 55#define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ 56#define OC_DEVICE_ID5 0x720 /* Device Id for Skyhawk cards */ 57#define OC_DEVICE_ID6 0x728 /* Device id for VF in SkyHawk */ 58#define OC_SUBSYS_DEVICE_ID1 0xE602 59#define OC_SUBSYS_DEVICE_ID2 0xE642 60#define OC_SUBSYS_DEVICE_ID3 0xE612 61#define OC_SUBSYS_DEVICE_ID4 0xE652 62 63/* Number of bytes of an RX frame that are copied to skb->data */ 64#define BE_HDR_LEN ((u16) 64) 65/* allocate extra space to allow tunneling decapsulation without head reallocation */ 66#define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64) 67 68#define BE_MAX_JUMBO_FRAME_SIZE 9018 69#define BE_MIN_MTU 256 70#define BE_MAX_MTU (BE_MAX_JUMBO_FRAME_SIZE - \ 71 (ETH_HLEN + ETH_FCS_LEN)) 72 73#define BE_NUM_VLANS_SUPPORTED 64 74#define BE_MAX_EQD 128u 75#define BE_MAX_TX_FRAG_COUNT 30 76 77#define EVNT_Q_LEN 1024 78#define TX_Q_LEN 2048 79#define TX_CQ_LEN 1024 80#define RX_Q_LEN 1024 /* Does not support any other value */ 81#define RX_CQ_LEN 1024 82#define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ 83#define MCC_CQ_LEN 256 84 85#define BE2_MAX_RSS_QS 4 86#define BE3_MAX_RSS_QS 16 87#define BE3_MAX_TX_QS 16 88#define BE3_MAX_EVT_QS 16 89#define BE3_SRIOV_MAX_EVT_QS 8 90 91#define MAX_RSS_IFACES 15 92#define MAX_RX_QS 32 93#define MAX_EVT_QS 32 94#define MAX_TX_QS 32 95 96#define MAX_ROCE_EQS 5 97#define MAX_MSIX_VECTORS 32 98#define MIN_MSIX_VECTORS 1 99#define BE_NAPI_WEIGHT 64 100#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ 101#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) 102#define MAX_NUM_POST_ERX_DB 255u 103 104#define MAX_VFS 30 /* Max VFs supported by BE3 FW */ 105#define FW_VER_LEN 32 106 107#define RSS_INDIR_TABLE_LEN 128 108#define RSS_HASH_KEY_LEN 40 109 110struct be_dma_mem { 111 void *va; 112 dma_addr_t dma; 113 u32 size; 114}; 115 116struct be_queue_info { 117 struct be_dma_mem dma_mem; 118 u16 len; 119 u16 entry_size; /* Size of an element in the queue */ 120 u16 id; 121 u16 tail, head; 122 bool created; 123 atomic_t used; /* Number of valid elements in the queue */ 124}; 125 126static inline u32 MODULO(u16 val, u16 limit) 127{ 128 BUG_ON(limit & (limit - 1)); 129 return val & (limit - 1); 130} 131 132static inline void index_adv(u16 *index, u16 val, u16 limit) 133{ 134 *index = MODULO((*index + val), limit); 135} 136 137static inline void index_inc(u16 *index, u16 limit) 138{ 139 *index = MODULO((*index + 1), limit); 140} 141 142static inline void *queue_head_node(struct be_queue_info *q) 143{ 144 return q->dma_mem.va + q->head * q->entry_size; 145} 146 147static inline void *queue_tail_node(struct be_queue_info *q) 148{ 149 return q->dma_mem.va + q->tail * q->entry_size; 150} 151 152static inline void *queue_index_node(struct be_queue_info *q, u16 index) 153{ 154 return q->dma_mem.va + index * q->entry_size; 155} 156 157static inline void queue_head_inc(struct be_queue_info *q) 158{ 159 index_inc(&q->head, q->len); 160} 161 162static inline void index_dec(u16 *index, u16 limit) 163{ 164 *index = MODULO((*index - 1), limit); 165} 166 167static inline void queue_tail_inc(struct be_queue_info *q) 168{ 169 index_inc(&q->tail, q->len); 170} 171 172struct be_eq_obj { 173 struct be_queue_info q; 174 char desc[32]; 175 176 /* Adaptive interrupt coalescing (AIC) info */ 177 bool enable_aic; 178 u32 min_eqd; /* in usecs */ 179 u32 max_eqd; /* in usecs */ 180 u32 eqd; /* configured val when aic is off */ 181 u32 cur_eqd; /* in usecs */ 182 183 u8 idx; /* array index */ 184 u8 msix_idx; 185 u16 spurious_intr; 186 struct napi_struct napi; 187 struct be_adapter *adapter; 188 cpumask_var_t affinity_mask; 189 190#ifdef CONFIG_NET_RX_BUSY_POLL 191#define BE_EQ_IDLE 0 192#define BE_EQ_NAPI 1 /* napi owns this EQ */ 193#define BE_EQ_POLL 2 /* poll owns this EQ */ 194#define BE_EQ_LOCKED (BE_EQ_NAPI | BE_EQ_POLL) 195#define BE_EQ_NAPI_YIELD 4 /* napi yielded this EQ */ 196#define BE_EQ_POLL_YIELD 8 /* poll yielded this EQ */ 197#define BE_EQ_YIELD (BE_EQ_NAPI_YIELD | BE_EQ_POLL_YIELD) 198#define BE_EQ_USER_PEND (BE_EQ_POLL | BE_EQ_POLL_YIELD) 199 unsigned int state; 200 spinlock_t lock; /* lock to serialize napi and busy-poll */ 201#endif /* CONFIG_NET_RX_BUSY_POLL */ 202} ____cacheline_aligned_in_smp; 203 204struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 205 bool enable; 206 u32 min_eqd; /* in usecs */ 207 u32 max_eqd; /* in usecs */ 208 u32 prev_eqd; /* in usecs */ 209 u32 et_eqd; /* configured val when aic is off */ 210 ulong jiffies; 211 u64 rx_pkts_prev; /* Used to calculate RX pps */ 212 u64 tx_reqs_prev; /* Used to calculate TX pps */ 213}; 214 215enum { 216 NAPI_POLLING, 217 BUSY_POLLING 218}; 219 220struct be_mcc_obj { 221 struct be_queue_info q; 222 struct be_queue_info cq; 223 bool rearm_cq; 224}; 225 226struct be_tx_stats { 227 u64 tx_bytes; 228 u64 tx_pkts; 229 u64 tx_reqs; 230 u64 tx_compl; 231 ulong tx_jiffies; 232 u32 tx_stops; 233 u32 tx_drv_drops; /* pkts dropped by driver */ 234 /* the error counters are described in be_ethtool.c */ 235 u32 tx_hdr_parse_err; 236 u32 tx_dma_err; 237 u32 tx_tso_err; 238 u32 tx_spoof_check_err; 239 u32 tx_qinq_err; 240 u32 tx_internal_parity_err; 241 struct u64_stats_sync sync; 242 struct u64_stats_sync sync_compl; 243}; 244 245/* Structure to hold some data of interest obtained from a TX CQE */ 246struct be_tx_compl_info { 247 u8 status; /* Completion status */ 248 u16 end_index; /* Completed TXQ Index */ 249}; 250 251struct be_tx_obj { 252 u32 db_offset; 253 struct be_queue_info q; 254 struct be_queue_info cq; 255 struct be_tx_compl_info txcp; 256 /* Remember the skbs that were transmitted */ 257 struct sk_buff *sent_skb_list[TX_Q_LEN]; 258 struct be_tx_stats stats; 259 u16 pend_wrb_cnt; /* Number of WRBs yet to be given to HW */ 260 u16 last_req_wrb_cnt; /* wrb cnt of the last req in the Q */ 261 u16 last_req_hdr; /* index of the last req's hdr-wrb */ 262} ____cacheline_aligned_in_smp; 263 264/* Struct to remember the pages posted for rx frags */ 265struct be_rx_page_info { 266 struct page *page; 267 /* set to page-addr for last frag of the page & frag-addr otherwise */ 268 DEFINE_DMA_UNMAP_ADDR(bus); 269 u16 page_offset; 270 bool last_frag; /* last frag of the page */ 271}; 272 273struct be_rx_stats { 274 u64 rx_bytes; 275 u64 rx_pkts; 276 u32 rx_drops_no_skbs; /* skb allocation errors */ 277 u32 rx_drops_no_frags; /* HW has no fetched frags */ 278 u32 rx_post_fail; /* page post alloc failures */ 279 u32 rx_compl; 280 u32 rx_mcast_pkts; 281 u32 rx_compl_err; /* completions with err set */ 282 struct u64_stats_sync sync; 283}; 284 285struct be_rx_compl_info { 286 u32 rss_hash; 287 u16 vlan_tag; 288 u16 pkt_size; 289 u16 port; 290 u8 vlanf; 291 u8 num_rcvd; 292 u8 err; 293 u8 ipf; 294 u8 tcpf; 295 u8 udpf; 296 u8 ip_csum; 297 u8 l4_csum; 298 u8 ipv6; 299 u8 qnq; 300 u8 pkt_type; 301 u8 ip_frag; 302 u8 tunneled; 303}; 304 305struct be_rx_obj { 306 struct be_adapter *adapter; 307 struct be_queue_info q; 308 struct be_queue_info cq; 309 struct be_rx_compl_info rxcp; 310 struct be_rx_page_info page_info_tbl[RX_Q_LEN]; 311 struct be_rx_stats stats; 312 u8 rss_id; 313 bool rx_post_starved; /* Zero rx frags have been posted to BE */ 314} ____cacheline_aligned_in_smp; 315 316struct be_drv_stats { 317 u32 be_on_die_temperature; 318 u32 eth_red_drops; 319 u32 dma_map_errors; 320 u32 rx_drops_no_pbuf; 321 u32 rx_drops_no_txpb; 322 u32 rx_drops_no_erx_descr; 323 u32 rx_drops_no_tpre_descr; 324 u32 rx_drops_too_many_frags; 325 u32 forwarded_packets; 326 u32 rx_drops_mtu; 327 u32 rx_crc_errors; 328 u32 rx_alignment_symbol_errors; 329 u32 rx_pause_frames; 330 u32 rx_priority_pause_frames; 331 u32 rx_control_frames; 332 u32 rx_in_range_errors; 333 u32 rx_out_range_errors; 334 u32 rx_frame_too_long; 335 u32 rx_address_filtered; 336 u32 rx_dropped_too_small; 337 u32 rx_dropped_too_short; 338 u32 rx_dropped_header_too_small; 339 u32 rx_dropped_tcp_length; 340 u32 rx_dropped_runt; 341 u32 rx_ip_checksum_errs; 342 u32 rx_tcp_checksum_errs; 343 u32 rx_udp_checksum_errs; 344 u32 tx_pauseframes; 345 u32 tx_priority_pauseframes; 346 u32 tx_controlframes; 347 u32 rxpp_fifo_overflow_drop; 348 u32 rx_input_fifo_overflow_drop; 349 u32 pmem_fifo_overflow_drop; 350 u32 jabber_events; 351 u32 rx_roce_bytes_lsd; 352 u32 rx_roce_bytes_msd; 353 u32 rx_roce_frames; 354 u32 roce_drops_payload_len; 355 u32 roce_drops_crc; 356}; 357 358/* A vlan-id of 0xFFFF must be used to clear transparent vlan-tagging */ 359#define BE_RESET_VLAN_TAG_ID 0xFFFF 360 361struct be_vf_cfg { 362 unsigned char mac_addr[ETH_ALEN]; 363 int if_handle; 364 int pmac_id; 365 u16 vlan_tag; 366 u32 tx_rate; 367 u32 plink_tracking; 368 u32 privileges; 369}; 370 371enum vf_state { 372 ENABLED = 0, 373 ASSIGNED = 1 374}; 375 376#define BE_FLAGS_LINK_STATUS_INIT BIT(1) 377#define BE_FLAGS_SRIOV_ENABLED BIT(2) 378#define BE_FLAGS_WORKER_SCHEDULED BIT(3) 379#define BE_FLAGS_NAPI_ENABLED BIT(6) 380#define BE_FLAGS_QNQ_ASYNC_EVT_RCVD BIT(7) 381#define BE_FLAGS_VXLAN_OFFLOADS BIT(8) 382#define BE_FLAGS_SETUP_DONE BIT(9) 383#define BE_FLAGS_EVT_INCOMPATIBLE_SFP BIT(10) 384#define BE_FLAGS_ERR_DETECTION_SCHEDULED BIT(11) 385 386#define BE_UC_PMAC_COUNT 30 387#define BE_VF_UC_PMAC_COUNT 2 388 389/* Ethtool set_dump flags */ 390#define LANCER_INITIATE_FW_DUMP 0x1 391#define LANCER_DELETE_FW_DUMP 0x2 392 393struct phy_info { 394/* From SFF-8472 spec */ 395#define SFP_VENDOR_NAME_LEN 17 396 u8 transceiver; 397 u8 autoneg; 398 u8 fc_autoneg; 399 u8 port_type; 400 u16 phy_type; 401 u16 interface_type; 402 u32 misc_params; 403 u16 auto_speeds_supported; 404 u16 fixed_speeds_supported; 405 int link_speed; 406 u32 advertising; 407 u32 supported; 408 u8 cable_type; 409 u8 vendor_name[SFP_VENDOR_NAME_LEN]; 410 u8 vendor_pn[SFP_VENDOR_NAME_LEN]; 411}; 412 413struct be_resources { 414 u16 max_vfs; /* Total VFs "really" supported by FW/HW */ 415 u16 max_mcast_mac; 416 u16 max_tx_qs; 417 u16 max_rss_qs; 418 u16 max_rx_qs; 419 u16 max_cq_count; 420 u16 max_uc_mac; /* Max UC MACs programmable */ 421 u16 max_vlans; /* Number of vlans supported */ 422 u16 max_iface_count; 423 u16 max_mcc_count; 424 u16 max_evt_qs; 425 u32 if_cap_flags; 426 u32 vf_if_cap_flags; /* VF if capability flags */ 427}; 428 429struct rss_info { 430 u64 rss_flags; 431 u8 rsstable[RSS_INDIR_TABLE_LEN]; 432 u8 rss_queue[RSS_INDIR_TABLE_LEN]; 433 u8 rss_hkey[RSS_HASH_KEY_LEN]; 434}; 435 436/* Macros to read/write the 'features' word of be_wrb_params structure. 437 */ 438#define BE_WRB_F_BIT(name) BE_WRB_F_##name##_BIT 439#define BE_WRB_F_MASK(name) BIT_MASK(BE_WRB_F_##name##_BIT) 440 441#define BE_WRB_F_GET(word, name) \ 442 (((word) & (BE_WRB_F_MASK(name))) >> BE_WRB_F_BIT(name)) 443 444#define BE_WRB_F_SET(word, name, val) \ 445 ((word) |= (((val) << BE_WRB_F_BIT(name)) & BE_WRB_F_MASK(name))) 446 447/* Feature/offload bits */ 448enum { 449 BE_WRB_F_CRC_BIT, /* Ethernet CRC */ 450 BE_WRB_F_IPCS_BIT, /* IP csum */ 451 BE_WRB_F_TCPCS_BIT, /* TCP csum */ 452 BE_WRB_F_UDPCS_BIT, /* UDP csum */ 453 BE_WRB_F_LSO_BIT, /* LSO */ 454 BE_WRB_F_LSO6_BIT, /* LSO6 */ 455 BE_WRB_F_VLAN_BIT, /* VLAN */ 456 BE_WRB_F_VLAN_SKIP_HW_BIT /* Skip VLAN tag (workaround) */ 457}; 458 459/* The structure below provides a HW-agnostic abstraction of WRB params 460 * retrieved from a TX skb. This is in turn passed to chip specific routines 461 * during transmit, to set the corresponding params in the WRB. 462 */ 463struct be_wrb_params { 464 u32 features; /* Feature bits */ 465 u16 vlan_tag; /* VLAN tag */ 466 u16 lso_mss; /* MSS for LSO */ 467}; 468 469struct be_adapter { 470 struct pci_dev *pdev; 471 struct net_device *netdev; 472 473 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */ 474 u8 __iomem *db; /* Door Bell */ 475 u8 __iomem *pcicfg; /* On SH,BEx only. Shadow of PCI config space */ 476 477 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 478 struct be_dma_mem mbox_mem; 479 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 480 * is stored for freeing purpose */ 481 struct be_dma_mem mbox_mem_alloced; 482 483 struct be_mcc_obj mcc_obj; 484 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 485 spinlock_t mcc_cq_lock; 486 487 u16 cfg_num_qs; /* configured via set-channels */ 488 u16 num_evt_qs; 489 u16 num_msix_vec; 490 struct be_eq_obj eq_obj[MAX_EVT_QS]; 491 struct msix_entry msix_entries[MAX_MSIX_VECTORS]; 492 bool isr_registered; 493 494 /* TX Rings */ 495 u16 num_tx_qs; 496 struct be_tx_obj tx_obj[MAX_TX_QS]; 497 498 /* Rx rings */ 499 u16 num_rx_qs; 500 u16 num_rss_qs; 501 u16 need_def_rxq; 502 struct be_rx_obj rx_obj[MAX_RX_QS]; 503 u32 big_page_size; /* Compounded page size shared by rx wrbs */ 504 505 struct be_drv_stats drv_stats; 506 struct be_aic_obj aic_obj[MAX_EVT_QS]; 507 u8 vlan_prio_bmap; /* Available Priority BitMap */ 508 u16 recommended_prio; /* Recommended Priority */ 509 struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */ 510 511 struct be_dma_mem stats_cmd; 512 /* Work queue used to perform periodic tasks like getting statistics */ 513 struct delayed_work work; 514 u16 work_counter; 515 516 struct delayed_work be_err_detection_work; 517 u32 flags; 518 u32 cmd_privileges; 519 /* Ethtool knobs and info */ 520 char fw_ver[FW_VER_LEN]; 521 char fw_on_flash[FW_VER_LEN]; 522 523 /* IFACE filtering fields */ 524 int if_handle; /* Used to configure filtering */ 525 u32 if_flags; /* Interface filtering flags */ 526 u32 *pmac_id; /* MAC addr handle used by BE card */ 527 u32 uc_macs; /* Count of secondary UC MAC programmed */ 528 unsigned long vids[BITS_TO_LONGS(VLAN_N_VID)]; 529 u16 vlans_added; 530 531 u32 beacon_state; /* for set_phys_id */ 532 533 bool eeh_error; 534 bool fw_timeout; 535 bool hw_error; 536 537 u32 port_num; 538 char port_name; 539 u8 mc_type; 540 u32 function_mode; 541 u32 function_caps; 542 u32 rx_fc; /* Rx flow control */ 543 u32 tx_fc; /* Tx flow control */ 544 bool stats_cmd_sent; 545 struct { 546 u32 size; 547 u32 total_size; 548 u64 io_addr; 549 } roce_db; 550 u32 num_msix_roce_vec; 551 struct ocrdma_dev *ocrdma_dev; 552 struct list_head entry; 553 554 u32 flash_status; 555 struct completion et_cmd_compl; 556 557 struct be_resources pool_res; /* resources available for the port */ 558 struct be_resources res; /* resources available for the func */ 559 u16 num_vfs; /* Number of VFs provisioned by PF */ 560 u8 virtfn; 561 struct be_vf_cfg *vf_cfg; 562 bool be3_native; 563 u32 sli_family; 564 u8 hba_port_num; 565 u16 pvid; 566 __be16 vxlan_port; 567 int vxlan_port_count; 568 struct phy_info phy; 569 u8 wol_cap; 570 bool wol_en; 571 u16 asic_rev; 572 u16 qnq_vid; 573 u32 msg_enable; 574 int be_get_temp_freq; 575 u8 pf_number; 576 struct rss_info rss_info; 577}; 578 579#define be_physfn(adapter) (!adapter->virtfn) 580#define be_virtfn(adapter) (adapter->virtfn) 581#define sriov_enabled(adapter) (adapter->flags & \ 582 BE_FLAGS_SRIOV_ENABLED) 583 584#define for_all_vfs(adapter, vf_cfg, i) \ 585 for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ 586 i++, vf_cfg++) 587 588#define ON 1 589#define OFF 0 590 591#define be_max_vlans(adapter) (adapter->res.max_vlans) 592#define be_max_uc(adapter) (adapter->res.max_uc_mac) 593#define be_max_mc(adapter) (adapter->res.max_mcast_mac) 594#define be_max_vfs(adapter) (adapter->pool_res.max_vfs) 595#define be_max_rss(adapter) (adapter->res.max_rss_qs) 596#define be_max_txqs(adapter) (adapter->res.max_tx_qs) 597#define be_max_prio_txqs(adapter) (adapter->res.max_prio_tx_qs) 598#define be_max_rxqs(adapter) (adapter->res.max_rx_qs) 599#define be_max_eqs(adapter) (adapter->res.max_evt_qs) 600#define be_if_cap_flags(adapter) (adapter->res.if_cap_flags) 601 602static inline u16 be_max_qs(struct be_adapter *adapter) 603{ 604 /* If no RSS, need atleast the one def RXQ */ 605 u16 num = max_t(u16, be_max_rss(adapter), 1); 606 607 num = min(num, be_max_eqs(adapter)); 608 return min_t(u16, num, num_online_cpus()); 609} 610 611/* Is BE in pvid_tagging mode */ 612#define be_pvid_tagging_enabled(adapter) (adapter->pvid) 613 614/* Is BE in QNQ multi-channel mode */ 615#define be_is_qnq_mode(adapter) (adapter->function_mode & QNQ_MODE) 616 617#define lancer_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID3 || \ 618 adapter->pdev->device == OC_DEVICE_ID4) 619 620#define skyhawk_chip(adapter) (adapter->pdev->device == OC_DEVICE_ID5 || \ 621 adapter->pdev->device == OC_DEVICE_ID6) 622 623#define BE3_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID2 || \ 624 adapter->pdev->device == OC_DEVICE_ID2) 625 626#define BE2_chip(adapter) (adapter->pdev->device == BE_DEVICE_ID1 || \ 627 adapter->pdev->device == OC_DEVICE_ID1) 628 629#define BEx_chip(adapter) (BE3_chip(adapter) || BE2_chip(adapter)) 630 631#define be_roce_supported(adapter) (skyhawk_chip(adapter) && \ 632 (adapter->function_mode & RDMA_ENABLED)) 633 634extern const struct ethtool_ops be_ethtool_ops; 635 636#define msix_enabled(adapter) (adapter->num_msix_vec > 0) 637#define num_irqs(adapter) (msix_enabled(adapter) ? \ 638 adapter->num_msix_vec : 1) 639#define tx_stats(txo) (&(txo)->stats) 640#define rx_stats(rxo) (&(rxo)->stats) 641 642/* The default RXQ is the last RXQ */ 643#define default_rxo(adpt) (&adpt->rx_obj[adpt->num_rx_qs - 1]) 644 645#define for_all_rx_queues(adapter, rxo, i) \ 646 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs; \ 647 i++, rxo++) 648 649#define for_all_rss_queues(adapter, rxo, i) \ 650 for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rss_qs; \ 651 i++, rxo++) 652 653#define for_all_tx_queues(adapter, txo, i) \ 654 for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs; \ 655 i++, txo++) 656 657#define for_all_evt_queues(adapter, eqo, i) \ 658 for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \ 659 i++, eqo++) 660 661#define for_all_rx_queues_on_eq(adapter, eqo, rxo, i) \ 662 for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\ 663 i += adapter->num_evt_qs, rxo += adapter->num_evt_qs) 664 665#define for_all_tx_queues_on_eq(adapter, eqo, txo, i) \ 666 for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\ 667 i += adapter->num_evt_qs, txo += adapter->num_evt_qs) 668 669#define is_mcc_eqo(eqo) (eqo->idx == 0) 670#define mcc_eqo(adapter) (&adapter->eq_obj[0]) 671 672#define PAGE_SHIFT_4K 12 673#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 674 675/* Returns number of pages spanned by the data starting at the given addr */ 676#define PAGES_4K_SPANNED(_address, size) \ 677 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 678 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 679 680/* Returns bit offset within a DWORD of a bitfield */ 681#define AMAP_BIT_OFFSET(_struct, field) \ 682 (((size_t)&(((_struct *)0)->field))%32) 683 684/* Returns the bit mask of the field that is NOT shifted into location. */ 685static inline u32 amap_mask(u32 bitsize) 686{ 687 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 688} 689 690static inline void 691amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) 692{ 693 u32 *dw = (u32 *) ptr + dw_offset; 694 *dw &= ~(mask << offset); 695 *dw |= (mask & value) << offset; 696} 697 698#define AMAP_SET_BITS(_struct, field, ptr, val) \ 699 amap_set(ptr, \ 700 offsetof(_struct, field)/32, \ 701 amap_mask(sizeof(((_struct *)0)->field)), \ 702 AMAP_BIT_OFFSET(_struct, field), \ 703 val) 704 705static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 706{ 707 u32 *dw = (u32 *) ptr; 708 return mask & (*(dw + dw_offset) >> offset); 709} 710 711#define AMAP_GET_BITS(_struct, field, ptr) \ 712 amap_get(ptr, \ 713 offsetof(_struct, field)/32, \ 714 amap_mask(sizeof(((_struct *)0)->field)), \ 715 AMAP_BIT_OFFSET(_struct, field)) 716 717#define GET_RX_COMPL_V0_BITS(field, ptr) \ 718 AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr) 719 720#define GET_RX_COMPL_V1_BITS(field, ptr) \ 721 AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr) 722 723#define GET_TX_COMPL_BITS(field, ptr) \ 724 AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr) 725 726#define SET_TX_WRB_HDR_BITS(field, ptr, val) \ 727 AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val) 728 729#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 730#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 731static inline void swap_dws(void *wrb, int len) 732{ 733#ifdef __BIG_ENDIAN 734 u32 *dw = wrb; 735 BUG_ON(len % 4); 736 do { 737 *dw = cpu_to_le32(*dw); 738 dw++; 739 len -= 4; 740 } while (len); 741#endif /* __BIG_ENDIAN */ 742} 743 744#define be_cmd_status(status) (status > 0 ? -EIO : status) 745 746static inline u8 is_tcp_pkt(struct sk_buff *skb) 747{ 748 u8 val = 0; 749 750 if (ip_hdr(skb)->version == 4) 751 val = (ip_hdr(skb)->protocol == IPPROTO_TCP); 752 else if (ip_hdr(skb)->version == 6) 753 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); 754 755 return val; 756} 757 758static inline u8 is_udp_pkt(struct sk_buff *skb) 759{ 760 u8 val = 0; 761 762 if (ip_hdr(skb)->version == 4) 763 val = (ip_hdr(skb)->protocol == IPPROTO_UDP); 764 else if (ip_hdr(skb)->version == 6) 765 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); 766 767 return val; 768} 769 770static inline bool is_ipv4_pkt(struct sk_buff *skb) 771{ 772 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4; 773} 774 775static inline bool be_multi_rxq(const struct be_adapter *adapter) 776{ 777 return adapter->num_rx_qs > 1; 778} 779 780static inline bool be_error(struct be_adapter *adapter) 781{ 782 return adapter->eeh_error || adapter->hw_error || adapter->fw_timeout; 783} 784 785static inline bool be_hw_error(struct be_adapter *adapter) 786{ 787 return adapter->eeh_error || adapter->hw_error; 788} 789 790static inline void be_clear_all_error(struct be_adapter *adapter) 791{ 792 adapter->eeh_error = false; 793 adapter->hw_error = false; 794 adapter->fw_timeout = false; 795} 796 797void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, 798 u16 num_popped); 799void be_link_status_update(struct be_adapter *adapter, u8 link_status); 800void be_parse_stats(struct be_adapter *adapter); 801int be_load_fw(struct be_adapter *adapter, u8 *func); 802bool be_is_wol_supported(struct be_adapter *adapter); 803bool be_pause_supported(struct be_adapter *adapter); 804u32 be_get_fw_log_level(struct be_adapter *adapter); 805int be_update_queues(struct be_adapter *adapter); 806int be_poll(struct napi_struct *napi, int budget); 807 808/* 809 * internal function to initialize-cleanup roce device. 810 */ 811void be_roce_dev_add(struct be_adapter *); 812void be_roce_dev_remove(struct be_adapter *); 813 814/* 815 * internal function to open-close roce device during ifup-ifdown. 816 */ 817void be_roce_dev_open(struct be_adapter *); 818void be_roce_dev_close(struct be_adapter *); 819void be_roce_dev_shutdown(struct be_adapter *); 820 821#endif /* BE_H */ 822